[mirror_ubuntu-kernels.git] / arch / arm / mach-ep93xx / clock.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * arch/arm/mach-ep93xx/clock.c
 * Clock control for Cirrus EP93xx chips.
 *
 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
 */

#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt

#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/io.h>
#include <linux/spinlock.h>
#include <linux/clkdev.h>
#include <linux/soc/cirrus/ep93xx.h>

#include "hardware.h"

#include <asm/div64.h>

#include "soc.h"

struct clk {
	struct clk	*parent;
	unsigned long	rate;
	int		users;
	int		sw_locked;
	void __iomem	*enable_reg;
	u32		enable_mask;

	unsigned long	(*get_rate)(struct clk *clk);
	int		(*set_rate)(struct clk *clk, unsigned long rate);
};


static unsigned long get_uart_rate(struct clk *clk);

static int set_keytchclk_rate(struct clk *clk, unsigned long rate);
static int set_div_rate(struct clk *clk, unsigned long rate);
static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate);
static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate);

static struct clk clk_xtali = {
	.rate		= EP93XX_EXT_CLK_RATE,
};
static struct clk clk_uart1 = {
	.parent		= &clk_xtali,
	.sw_locked	= 1,
	.enable_reg	= EP93XX_SYSCON_DEVCFG,
	.enable_mask	= EP93XX_SYSCON_DEVCFG_U1EN,
	.get_rate	= get_uart_rate,
};
static struct clk clk_uart2 = {
	.parent		= &clk_xtali,
	.sw_locked	= 1,
	.enable_reg	= EP93XX_SYSCON_DEVCFG,
	.enable_mask	= EP93XX_SYSCON_DEVCFG_U2EN,
	.get_rate	= get_uart_rate,
};
static struct clk clk_uart3 = {
	.parent		= &clk_xtali,
	.sw_locked	= 1,
	.enable_reg	= EP93XX_SYSCON_DEVCFG,
	.enable_mask	= EP93XX_SYSCON_DEVCFG_U3EN,
	.get_rate	= get_uart_rate,
};
static struct clk clk_pll1 = {
	.parent		= &clk_xtali,
};
static struct clk clk_f = {
	.parent		= &clk_pll1,
};
static struct clk clk_h = {
	.parent		= &clk_pll1,
};
static struct clk clk_p = {
	.parent		= &clk_pll1,
};
static struct clk clk_pll2 = {
	.parent		= &clk_xtali,
};
static struct clk clk_usb_host = {
	.parent		= &clk_pll2,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_USH_EN,
};
static struct clk clk_keypad = {
	.parent		= &clk_xtali,
	.sw_locked	= 1,
	.enable_reg	= EP93XX_SYSCON_KEYTCHCLKDIV,
	.enable_mask	= EP93XX_SYSCON_KEYTCHCLKDIV_KEN,
	.set_rate	= set_keytchclk_rate,
};
static struct clk clk_adc = {
	.parent		= &clk_xtali,
	.sw_locked	= 1,
	.enable_reg	= EP93XX_SYSCON_KEYTCHCLKDIV,
	.enable_mask	= EP93XX_SYSCON_KEYTCHCLKDIV_TSEN,
	.set_rate	= set_keytchclk_rate,
};
static struct clk clk_spi = {
	.parent		= &clk_xtali,
	.rate		= EP93XX_EXT_CLK_RATE,
};
static struct clk clk_pwm = {
	.parent		= &clk_xtali,
	.rate		= EP93XX_EXT_CLK_RATE,
};

static struct clk clk_video = {
	.sw_locked	= 1,
	.enable_reg     = EP93XX_SYSCON_VIDCLKDIV,
	.enable_mask    = EP93XX_SYSCON_CLKDIV_ENABLE,
	.set_rate	= set_div_rate,
};

static struct clk clk_i2s_mclk = {
	.sw_locked	= 1,
	.enable_reg	= EP93XX_SYSCON_I2SCLKDIV,
	.enable_mask	= EP93XX_SYSCON_CLKDIV_ENABLE,
	.set_rate	= set_div_rate,
};

static struct clk clk_i2s_sclk = {
	.sw_locked	= 1,
	.parent		= &clk_i2s_mclk,
	.enable_reg	= EP93XX_SYSCON_I2SCLKDIV,
	.enable_mask	= EP93XX_SYSCON_I2SCLKDIV_SENA,
	.set_rate	= set_i2s_sclk_rate,
};

static struct clk clk_i2s_lrclk = {
	.sw_locked	= 1,
	.parent		= &clk_i2s_sclk,
	.enable_reg	= EP93XX_SYSCON_I2SCLKDIV,
	.enable_mask	= EP93XX_SYSCON_I2SCLKDIV_SENA,
	.set_rate	= set_i2s_lrclk_rate,
};

/* DMA Clocks */
static struct clk clk_m2p0 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P0,
};
static struct clk clk_m2p1 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P1,
};
static struct clk clk_m2p2 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P2,
};
static struct clk clk_m2p3 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P3,
};
static struct clk clk_m2p4 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P4,
};
static struct clk clk_m2p5 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P5,
};
static struct clk clk_m2p6 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P6,
};
static struct clk clk_m2p7 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P7,
};
static struct clk clk_m2p8 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P8,
};
static struct clk clk_m2p9 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P9,
};
static struct clk clk_m2m0 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2M0,
};
static struct clk clk_m2m1 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2M1,
};

#define INIT_CK(dev,con,ck)					\
	{ .dev_id = dev, .con_id = con, .clk = ck }

static struct clk_lookup clocks[] = {
	INIT_CK(NULL,			"xtali",	&clk_xtali),
	INIT_CK("apb:uart1",		NULL,		&clk_uart1),
	INIT_CK("apb:uart2",		NULL,		&clk_uart2),
	INIT_CK("apb:uart3",		NULL,		&clk_uart3),
	INIT_CK(NULL,			"pll1",		&clk_pll1),
	INIT_CK(NULL,			"fclk",		&clk_f),
	INIT_CK(NULL,			"hclk",		&clk_h),
	INIT_CK(NULL,			"apb_pclk",	&clk_p),
	INIT_CK(NULL,			"pll2",		&clk_pll2),
	INIT_CK("ohci-platform",	NULL,		&clk_usb_host),
	INIT_CK("ep93xx-keypad",	NULL,		&clk_keypad),
	INIT_CK("ep93xx-adc",		NULL,		&clk_adc),
	INIT_CK("ep93xx-fb",		NULL,		&clk_video),
	INIT_CK("ep93xx-spi.0",		NULL,		&clk_spi),
	INIT_CK("ep93xx-i2s",		"mclk",		&clk_i2s_mclk),
	INIT_CK("ep93xx-i2s",		"sclk",		&clk_i2s_sclk),
	INIT_CK("ep93xx-i2s",		"lrclk",	&clk_i2s_lrclk),
	INIT_CK(NULL,			"pwm_clk",	&clk_pwm),
	INIT_CK(NULL,			"m2p0",		&clk_m2p0),
	INIT_CK(NULL,			"m2p1",		&clk_m2p1),
	INIT_CK(NULL,			"m2p2",		&clk_m2p2),
	INIT_CK(NULL,			"m2p3",		&clk_m2p3),
	INIT_CK(NULL,			"m2p4",		&clk_m2p4),
	INIT_CK(NULL,			"m2p5",		&clk_m2p5),
	INIT_CK(NULL,			"m2p6",		&clk_m2p6),
	INIT_CK(NULL,			"m2p7",		&clk_m2p7),
	INIT_CK(NULL,			"m2p8",		&clk_m2p8),
	INIT_CK(NULL,			"m2p9",		&clk_m2p9),
	INIT_CK(NULL,			"m2m0",		&clk_m2m0),
	INIT_CK(NULL,			"m2m1",		&clk_m2m1),
};

static DEFINE_SPINLOCK(clk_lock);

static void __clk_enable(struct clk *clk)
{
	if (!clk->users++) {
		if (clk->parent)
			__clk_enable(clk->parent);

		if (clk->enable_reg) {
			u32 v;

			v = __raw_readl(clk->enable_reg);
			v |= clk->enable_mask;
			if (clk->sw_locked)
				ep93xx_syscon_swlocked_write(v, clk->enable_reg);
			else
				__raw_writel(v, clk->enable_reg);
		}
	}
}

int clk_enable(struct clk *clk)
{
	unsigned long flags;

	if (!clk)
		return -EINVAL;

	spin_lock_irqsave(&clk_lock, flags);
	__clk_enable(clk);
	spin_unlock_irqrestore(&clk_lock, flags);

	return 0;
}
EXPORT_SYMBOL(clk_enable);

static void __clk_disable(struct clk *clk)
{
	if (!--clk->users) {
		if (clk->enable_reg) {
			u32 v;

			v = __raw_readl(clk->enable_reg);
			v &= ~clk->enable_mask;
			if (clk->sw_locked)
				ep93xx_syscon_swlocked_write(v, clk->enable_reg);
			else
				__raw_writel(v, clk->enable_reg);
		}

		if (clk->parent)
			__clk_disable(clk->parent);
	}
}

void clk_disable(struct clk *clk)
{
	unsigned long flags;

	if (!clk)
		return;

	spin_lock_irqsave(&clk_lock, flags);
	__clk_disable(clk);
	spin_unlock_irqrestore(&clk_lock, flags);
}
EXPORT_SYMBOL(clk_disable);

static unsigned long get_uart_rate(struct clk *clk)
{
	unsigned long rate = clk_get_rate(clk->parent);
	u32 value;

	value = __raw_readl(EP93XX_SYSCON_PWRCNT);
	if (value & EP93XX_SYSCON_PWRCNT_UARTBAUD)
		return rate;
	else
		return rate / 2;
}

unsigned long clk_get_rate(struct clk *clk)
{
	if (clk->get_rate)
		return clk->get_rate(clk);

	return clk->rate;
}
EXPORT_SYMBOL(clk_get_rate);

static int set_keytchclk_rate(struct clk *clk, unsigned long rate)
{
	u32 val;
	u32 div_bit;

	val = __raw_readl(clk->enable_reg);

	/*
	 * The Key Matrix and ADC clocks are configured using the same
	 * System Controller register.  The clock used will be either
	 * 1/4 or 1/16 the external clock rate depending on the
	 * EP93XX_SYSCON_KEYTCHCLKDIV_KDIV/EP93XX_SYSCON_KEYTCHCLKDIV_ADIV
	 * bit being set or cleared.
	 */
	div_bit = clk->enable_mask >> 15;

	if (rate == EP93XX_KEYTCHCLK_DIV4)
		val |= div_bit;
	else if (rate == EP93XX_KEYTCHCLK_DIV16)
		val &= ~div_bit;
	else
		return -EINVAL;

	ep93xx_syscon_swlocked_write(val, clk->enable_reg);
	clk->rate = rate;
	return 0;
}

static int calc_clk_div(struct clk *clk, unsigned long rate,
			int *psel, int *esel, int *pdiv, int *div)
{
	struct clk *mclk;
	unsigned long max_rate, actual_rate, mclk_rate, rate_err = -1;
	int i, found = 0, __div = 0, __pdiv = 0;

	/* Don't exceed the maximum rate */
	max_rate = max3(clk_pll1.rate / 4, clk_pll2.rate / 4, clk_xtali.rate / 4);
	rate = min(rate, max_rate);

	/*
	 * Try the two pll's and the external clock
	 * Because the valid predividers are 2, 2.5 and 3, we multiply
	 * all the clocks by 2 to avoid floating point math.
	 *
	 * This is based on the algorithm in the ep93xx raster guide:
	 * http://be-a-maverick.com/en/pubs/appNote/AN269REV1.pdf
	 *
	 */
	for (i = 0; i < 3; i++) {
		if (i == 0)
			mclk = &clk_xtali;
		else if (i == 1)
			mclk = &clk_pll1;
		else
			mclk = &clk_pll2;
		mclk_rate = mclk->rate * 2;

		/* Try each predivider value */
		for (__pdiv = 4; __pdiv <= 6; __pdiv++) {
			__div = mclk_rate / (rate * __pdiv);
			if (__div < 2 || __div > 127)
				continue;

			actual_rate = mclk_rate / (__pdiv * __div);

			if (!found || abs(actual_rate - rate) < rate_err) {
				*pdiv = __pdiv - 3;
				*div = __div;
				*psel = (i == 2);
				*esel = (i != 0);
				clk->parent = mclk;
				clk->rate = actual_rate;
				rate_err = abs(actual_rate - rate);
				found = 1;
			}
		}
	}

	if (!found)
		return -EINVAL;

	return 0;
}

static int set_div_rate(struct clk *clk, unsigned long rate)
{
	int err, psel = 0, esel = 0, pdiv = 0, div = 0;
	u32 val;

	err = calc_clk_div(clk, rate, &psel, &esel, &pdiv, &div);
	if (err)
		return err;

	/* Clear the esel, psel, pdiv and div bits */
	val = __raw_readl(clk->enable_reg);
	val &= ~0x7fff;

	/* Set the new esel, psel, pdiv and div bits for the new clock rate */
	val |= (esel ? EP93XX_SYSCON_CLKDIV_ESEL : 0) |
		(psel ? EP93XX_SYSCON_CLKDIV_PSEL : 0) |
		(pdiv << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | div;
	ep93xx_syscon_swlocked_write(val, clk->enable_reg);
	return 0;
}

static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate)
{
	unsigned val = __raw_readl(clk->enable_reg);

	if (rate == clk_i2s_mclk.rate / 2)
		ep93xx_syscon_swlocked_write(val & ~EP93XX_I2SCLKDIV_SDIV, 
					     clk->enable_reg);
	else if (rate == clk_i2s_mclk.rate / 4)
		ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_SDIV, 
					     clk->enable_reg);
	else
		return -EINVAL;

	clk_i2s_sclk.rate = rate;
	return 0;
}

static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate)
{
	unsigned val = __raw_readl(clk->enable_reg) & 
		~EP93XX_I2SCLKDIV_LRDIV_MASK;
	
	if (rate == clk_i2s_sclk.rate / 32)
		ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV32,
					     clk->enable_reg);
	else if (rate == clk_i2s_sclk.rate / 64)
		ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV64,
					     clk->enable_reg);
	else if (rate == clk_i2s_sclk.rate / 128)
		ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV128,
					     clk->enable_reg);
	else
		return -EINVAL;

	clk_i2s_lrclk.rate = rate;
	return 0;
}

int clk_set_rate(struct clk *clk, unsigned long rate)
{
	if (clk->set_rate)
		return clk->set_rate(clk, rate);

	return -EINVAL;
}
EXPORT_SYMBOL(clk_set_rate);

long clk_round_rate(struct clk *clk, unsigned long rate)
{
	WARN_ON(clk);
	return 0;
}
EXPORT_SYMBOL(clk_round_rate);

int clk_set_parent(struct clk *clk, struct clk *parent)
{
	WARN_ON(clk);
	return 0;
}
EXPORT_SYMBOL(clk_set_parent);

struct clk *clk_get_parent(struct clk *clk)
{
	return clk->parent;
}
EXPORT_SYMBOL(clk_get_parent);


static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
static char pclk_divisors[] = { 1, 2, 4, 8 };

/*
 * PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS
 */
static unsigned long calc_pll_rate(u32 config_word)
{
	unsigned long long rate;
	int i;

	rate = clk_xtali.rate;
	rate *= ((config_word >> 11) & 0x1f) + 1;		/* X1FBD */
	rate *= ((config_word >> 5) & 0x3f) + 1;		/* X2FBD */
	do_div(rate, (config_word & 0x1f) + 1);			/* X2IPD */
	for (i = 0; i < ((config_word >> 16) & 3); i++)		/* PS */
		rate >>= 1;

	return (unsigned long)rate;
}

static void __init ep93xx_dma_clock_init(void)
{
	clk_m2p0.rate = clk_h.rate;
	clk_m2p1.rate = clk_h.rate;
	clk_m2p2.rate = clk_h.rate;
	clk_m2p3.rate = clk_h.rate;
	clk_m2p4.rate = clk_h.rate;
	clk_m2p5.rate = clk_h.rate;
	clk_m2p6.rate = clk_h.rate;
	clk_m2p7.rate = clk_h.rate;
	clk_m2p8.rate = clk_h.rate;
	clk_m2p9.rate = clk_h.rate;
	clk_m2m0.rate = clk_h.rate;
	clk_m2m1.rate = clk_h.rate;
}

static int __init ep93xx_clock_init(void)
{
	u32 value;

	/* Determine the bootloader configured pll1 rate */
	value = __raw_readl(EP93XX_SYSCON_CLKSET1);
	if (!(value & EP93XX_SYSCON_CLKSET1_NBYP1))
		clk_pll1.rate = clk_xtali.rate;
	else
		clk_pll1.rate = calc_pll_rate(value);

	/* Initialize the pll1 derived clocks */
	clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7];
	clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7];
	clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3];
	ep93xx_dma_clock_init();

	/* Determine the bootloader configured pll2 rate */
	value = __raw_readl(EP93XX_SYSCON_CLKSET2);
	if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2))
		clk_pll2.rate = clk_xtali.rate;
	else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN)
		clk_pll2.rate = calc_pll_rate(value);
	else
		clk_pll2.rate = 0;

	/* Initialize the pll2 derived clocks */
	clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1);

	/*
	 * EP93xx SSP clock rate was doubled in version E2. For more information
	 * see:
	 *     http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
	 */
	if (ep93xx_chip_revision() < EP93XX_CHIP_REV_E2)
		clk_spi.rate /= 2;

	pr_info("PLL1 running at %ld MHz, PLL2 at %ld MHz\n",
		clk_pll1.rate / 1000000, clk_pll2.rate / 1000000);
	pr_info("FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n",
		clk_f.rate / 1000000, clk_h.rate / 1000000,
		clk_p.rate / 1000000);

	clkdev_add_table(clocks, ARRAY_SIZE(clocks));
	return 0;
}
postcore_initcall(ep93xx_clock_init);
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
1d81eedb LB	2	/*
	3	* arch/arm/mach-ep93xx/clock.c
	4	* Clock control for Cirrus EP93xx chips.
	5	*
	6	* Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
1d81eedb LB	7	*/
1d81eedb LB	8
99acbb90 HS	9	#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
99acbb90 HS	10
1d81eedb LB	11	#include <linux/kernel.h>
	12	#include <linux/clk.h>
	13	#include <linux/err.h>
51dd249e	14	#include <linux/module.h>
1d81eedb	15	#include <linux/string.h>
fced80c7	16	#include <linux/io.h>
ebd00c08	17	#include <linux/spinlock.h>
6d803ba7	18	#include <linux/clkdev.h>
67e38f57	19	#include <linux/soc/cirrus/ep93xx.h>
ebd00c08	20
5b7cc904	21	#include "hardware.h"
ae696fd5	22
1d81eedb	23	#include <asm/div64.h>
1d81eedb	24
999c53fb	25	#include "soc.h"
ff05c033	26
1d81eedb	27	struct clk {
ebd00c08	28	struct clk *parent;
1d81eedb LB	29	unsigned long rate;
1d81eedb LB	30	int users;
ff05c033	31	int sw_locked;
c3e3badd	32	void __iomem *enable_reg;
1d81eedb	33	u32 enable_mask;
ff05c033 HS	34
ff05c033 HS	35	unsigned long (get_rate)(struct clk clk);
701fac82	36	int (set_rate)(struct clk clk, unsigned long rate);
1d81eedb LB	37	};
1d81eedb LB	38
ff05c033 HS	39
	40	static unsigned long get_uart_rate(struct clk *clk);
	41
701fac82	42	static int set_keytchclk_rate(struct clk *clk, unsigned long rate);
c6012189	43	static int set_div_rate(struct clk *clk, unsigned long rate);
ed67ea82 RM	44	static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate);
ed67ea82 RM	45	static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate);
ebd00c08 HS	46
	47	static struct clk clk_xtali = {
	48	.rate = EP93XX_EXT_CLK_RATE,
	49	};
ff05c033	50	static struct clk clk_uart1 = {
ebd00c08	51	.parent = &clk_xtali,
ff05c033	52	.sw_locked = 1,
02239f0a HS	53	.enable_reg = EP93XX_SYSCON_DEVCFG,
02239f0a HS	54	.enable_mask = EP93XX_SYSCON_DEVCFG_U1EN,
ff05c033 HS	55	.get_rate = get_uart_rate,
	56	};
	57	static struct clk clk_uart2 = {
ebd00c08	58	.parent = &clk_xtali,
ff05c033	59	.sw_locked = 1,
02239f0a HS	60	.enable_reg = EP93XX_SYSCON_DEVCFG,
02239f0a HS	61	.enable_mask = EP93XX_SYSCON_DEVCFG_U2EN,
ff05c033 HS	62	.get_rate = get_uart_rate,
	63	};
	64	static struct clk clk_uart3 = {
ebd00c08	65	.parent = &clk_xtali,
ff05c033	66	.sw_locked = 1,
02239f0a HS	67	.enable_reg = EP93XX_SYSCON_DEVCFG,
02239f0a HS	68	.enable_mask = EP93XX_SYSCON_DEVCFG_U3EN,
ff05c033	69	.get_rate = get_uart_rate,
ed519ded	70	};
ebd00c08 HS	71	static struct clk clk_pll1 = {
	72	.parent = &clk_xtali,
	73	};
	74	static struct clk clk_f = {
	75	.parent = &clk_pll1,
	76	};
	77	static struct clk clk_h = {
	78	.parent = &clk_pll1,
	79	};
	80	static struct clk clk_p = {
	81	.parent = &clk_pll1,
	82	};
	83	static struct clk clk_pll2 = {
	84	.parent = &clk_xtali,
	85	};
1d81eedb	86	static struct clk clk_usb_host = {
ebd00c08	87	.parent = &clk_pll2,
40702432 HS	88	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	89	.enable_mask = EP93XX_SYSCON_PWRCNT_USH_EN,
1d81eedb	90	};
701fac82	91	static struct clk clk_keypad = {
ebd00c08	92	.parent = &clk_xtali,
701fac82 HS	93	.sw_locked = 1,
	94	.enable_reg = EP93XX_SYSCON_KEYTCHCLKDIV,
	95	.enable_mask = EP93XX_SYSCON_KEYTCHCLKDIV_KEN,
	96	.set_rate = set_keytchclk_rate,
	97	};
f2322451 AS	98	static struct clk clk_adc = {
	99	.parent = &clk_xtali,
	100	.sw_locked = 1,
	101	.enable_reg = EP93XX_SYSCON_KEYTCHCLKDIV,
	102	.enable_mask = EP93XX_SYSCON_KEYTCHCLKDIV_TSEN,
	103	.set_rate = set_keytchclk_rate,
	104	};
4fec9978 MW	105	static struct clk clk_spi = {
	106	.parent = &clk_xtali,
	107	.rate = EP93XX_EXT_CLK_RATE,
	108	};
ef12379f	109	static struct clk clk_pwm = {
ebd00c08	110	.parent = &clk_xtali,
ef12379f HS	111	.rate = EP93XX_EXT_CLK_RATE,
ef12379f HS	112	};
1d81eedb	113
c6012189 RM	114	static struct clk clk_video = {
	115	.sw_locked = 1,
	116	.enable_reg = EP93XX_SYSCON_VIDCLKDIV,
	117	.enable_mask = EP93XX_SYSCON_CLKDIV_ENABLE,
	118	.set_rate = set_div_rate,
	119	};
	120
ed67ea82 RM	121	static struct clk clk_i2s_mclk = {
	122	.sw_locked = 1,
	123	.enable_reg = EP93XX_SYSCON_I2SCLKDIV,
	124	.enable_mask = EP93XX_SYSCON_CLKDIV_ENABLE,
	125	.set_rate = set_div_rate,
	126	};
	127
	128	static struct clk clk_i2s_sclk = {
	129	.sw_locked = 1,
	130	.parent = &clk_i2s_mclk,
	131	.enable_reg = EP93XX_SYSCON_I2SCLKDIV,
	132	.enable_mask = EP93XX_SYSCON_I2SCLKDIV_SENA,
	133	.set_rate = set_i2s_sclk_rate,
	134	};
	135
	136	static struct clk clk_i2s_lrclk = {
	137	.sw_locked = 1,
	138	.parent = &clk_i2s_sclk,
	139	.enable_reg = EP93XX_SYSCON_I2SCLKDIV,
	140	.enable_mask = EP93XX_SYSCON_I2SCLKDIV_SENA,
	141	.set_rate = set_i2s_lrclk_rate,
	142	};
	143
1c8daabe RM	144	/* DMA Clocks */
1c8daabe RM	145	static struct clk clk_m2p0 = {
ebd00c08	146	.parent = &clk_h,
40702432 HS	147	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	148	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P0,
1c8daabe RM	149	};
1c8daabe RM	150	static struct clk clk_m2p1 = {
ebd00c08	151	.parent = &clk_h,
40702432 HS	152	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	153	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P1,
1c8daabe RM	154	};
1c8daabe RM	155	static struct clk clk_m2p2 = {
ebd00c08	156	.parent = &clk_h,
40702432 HS	157	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	158	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P2,
1c8daabe RM	159	};
1c8daabe RM	160	static struct clk clk_m2p3 = {
ebd00c08	161	.parent = &clk_h,
40702432 HS	162	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	163	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P3,
1c8daabe RM	164	};
1c8daabe RM	165	static struct clk clk_m2p4 = {
ebd00c08	166	.parent = &clk_h,
40702432 HS	167	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	168	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P4,
1c8daabe RM	169	};
1c8daabe RM	170	static struct clk clk_m2p5 = {
ebd00c08	171	.parent = &clk_h,
40702432 HS	172	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	173	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P5,
1c8daabe RM	174	};
1c8daabe RM	175	static struct clk clk_m2p6 = {
ebd00c08	176	.parent = &clk_h,
40702432 HS	177	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	178	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P6,
1c8daabe RM	179	};
1c8daabe RM	180	static struct clk clk_m2p7 = {
ebd00c08	181	.parent = &clk_h,
40702432 HS	182	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	183	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P7,
1c8daabe RM	184	};
1c8daabe RM	185	static struct clk clk_m2p8 = {
ebd00c08	186	.parent = &clk_h,
40702432 HS	187	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	188	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P8,
1c8daabe RM	189	};
1c8daabe RM	190	static struct clk clk_m2p9 = {
ebd00c08	191	.parent = &clk_h,
40702432 HS	192	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	193	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P9,
1c8daabe RM	194	};
1c8daabe RM	195	static struct clk clk_m2m0 = {
ebd00c08	196	.parent = &clk_h,
40702432 HS	197	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	198	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M0,
1c8daabe RM	199	};
1c8daabe RM	200	static struct clk clk_m2m1 = {
ebd00c08	201	.parent = &clk_h,
40702432 HS	202	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	203	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M1,
1c8daabe RM	204	};
1c8daabe RM	205
ae696fd5 RK	206	#define INIT_CK(dev,con,ck) \
	207	{ .dev_id = dev, .con_id = con, .clk = ck }
	208
	209	static struct clk_lookup clocks[] = {
ebd00c08	210	INIT_CK(NULL, "xtali", &clk_xtali),
701fac82 HS	211	INIT_CK("apb:uart1", NULL, &clk_uart1),
	212	INIT_CK("apb:uart2", NULL, &clk_uart2),
	213	INIT_CK("apb:uart3", NULL, &clk_uart3),
	214	INIT_CK(NULL, "pll1", &clk_pll1),
	215	INIT_CK(NULL, "fclk", &clk_f),
	216	INIT_CK(NULL, "hclk", &clk_h),
3126c7bc	217	INIT_CK(NULL, "apb_pclk", &clk_p),
701fac82	218	INIT_CK(NULL, "pll2", &clk_pll2),
e55f7cd2	219	INIT_CK("ohci-platform", NULL, &clk_usb_host),
701fac82	220	INIT_CK("ep93xx-keypad", NULL, &clk_keypad),
f2322451	221	INIT_CK("ep93xx-adc", NULL, &clk_adc),
c6012189	222	INIT_CK("ep93xx-fb", NULL, &clk_video),
4fec9978	223	INIT_CK("ep93xx-spi.0", NULL, &clk_spi),
ed67ea82 RM	224	INIT_CK("ep93xx-i2s", "mclk", &clk_i2s_mclk),
	225	INIT_CK("ep93xx-i2s", "sclk", &clk_i2s_sclk),
	226	INIT_CK("ep93xx-i2s", "lrclk", &clk_i2s_lrclk),
ef12379f	227	INIT_CK(NULL, "pwm_clk", &clk_pwm),
701fac82 HS	228	INIT_CK(NULL, "m2p0", &clk_m2p0),
	229	INIT_CK(NULL, "m2p1", &clk_m2p1),
	230	INIT_CK(NULL, "m2p2", &clk_m2p2),
	231	INIT_CK(NULL, "m2p3", &clk_m2p3),
	232	INIT_CK(NULL, "m2p4", &clk_m2p4),
	233	INIT_CK(NULL, "m2p5", &clk_m2p5),
	234	INIT_CK(NULL, "m2p6", &clk_m2p6),
	235	INIT_CK(NULL, "m2p7", &clk_m2p7),
	236	INIT_CK(NULL, "m2p8", &clk_m2p8),
	237	INIT_CK(NULL, "m2p9", &clk_m2p9),
	238	INIT_CK(NULL, "m2m0", &clk_m2m0),
	239	INIT_CK(NULL, "m2m1", &clk_m2m1),
1d81eedb LB	240	};
1d81eedb LB	241
ebd00c08 HS	242	static DEFINE_SPINLOCK(clk_lock);
	243
	244	static void __clk_enable(struct clk *clk)
	245	{
	246	if (!clk->users++) {
	247	if (clk->parent)
	248	__clk_enable(clk->parent);
	249
	250	if (clk->enable_reg) {
	251	u32 v;
	252
	253	v = __raw_readl(clk->enable_reg);
	254	v \|= clk->enable_mask;
	255	if (clk->sw_locked)
	256	ep93xx_syscon_swlocked_write(v, clk->enable_reg);
	257	else
	258	__raw_writel(v, clk->enable_reg);
	259	}
	260	}
	261	}
1d81eedb LB	262
	263	int clk_enable(struct clk *clk)
	264	{
ebd00c08	265	unsigned long flags;
1d81eedb	266
ebd00c08 HS	267	if (!clk)
	268	return -EINVAL;
	269
	270	spin_lock_irqsave(&clk_lock, flags);
	271	__clk_enable(clk);
	272	spin_unlock_irqrestore(&clk_lock, flags);
1d81eedb LB	273
	274	return 0;
	275	}
0c5d5b70	276	EXPORT_SYMBOL(clk_enable);
1d81eedb	277
ebd00c08	278	static void __clk_disable(struct clk *clk)
1d81eedb	279	{
ebd00c08 HS	280	if (!--clk->users) {
	281	if (clk->enable_reg) {
	282	u32 v;
	283
	284	v = __raw_readl(clk->enable_reg);
	285	v &= ~clk->enable_mask;
	286	if (clk->sw_locked)
	287	ep93xx_syscon_swlocked_write(v, clk->enable_reg);
	288	else
	289	__raw_writel(v, clk->enable_reg);
	290	}
1d81eedb	291
ebd00c08 HS	292	if (clk->parent)
ebd00c08 HS	293	__clk_disable(clk->parent);
1d81eedb LB	294	}
1d81eedb LB	295	}
ebd00c08 HS	296
	297	void clk_disable(struct clk *clk)
	298	{
	299	unsigned long flags;
	300
	301	if (!clk)
	302	return;
	303
	304	spin_lock_irqsave(&clk_lock, flags);
	305	__clk_disable(clk);
	306	spin_unlock_irqrestore(&clk_lock, flags);
	307	}
0c5d5b70	308	EXPORT_SYMBOL(clk_disable);
1d81eedb	309
ff05c033 HS	310	static unsigned long get_uart_rate(struct clk *clk)
ff05c033 HS	311	{
ebd00c08	312	unsigned long rate = clk_get_rate(clk->parent);
ff05c033 HS	313	u32 value;
ff05c033 HS	314
ca8cbc83 MK	315	value = __raw_readl(EP93XX_SYSCON_PWRCNT);
ca8cbc83 MK	316	if (value & EP93XX_SYSCON_PWRCNT_UARTBAUD)
ebd00c08	317	return rate;
ff05c033	318	else
ebd00c08	319	return rate / 2;
ff05c033 HS	320	}
ff05c033 HS	321
1d81eedb LB	322	unsigned long clk_get_rate(struct clk *clk)
1d81eedb LB	323	{
ff05c033 HS	324	if (clk->get_rate)
	325	return clk->get_rate(clk);
	326
1d81eedb LB	327	return clk->rate;
1d81eedb LB	328	}
0c5d5b70	329	EXPORT_SYMBOL(clk_get_rate);
1d81eedb	330
701fac82 HS	331	static int set_keytchclk_rate(struct clk *clk, unsigned long rate)
	332	{
	333	u32 val;
	334	u32 div_bit;
	335
	336	val = __raw_readl(clk->enable_reg);
	337
	338	/*
	339	* The Key Matrix and ADC clocks are configured using the same
	340	* System Controller register. The clock used will be either
	341	* 1/4 or 1/16 the external clock rate depending on the
	342	* EP93XX_SYSCON_KEYTCHCLKDIV_KDIV/EP93XX_SYSCON_KEYTCHCLKDIV_ADIV
	343	* bit being set or cleared.
	344	*/
	345	div_bit = clk->enable_mask >> 15;
	346
	347	if (rate == EP93XX_KEYTCHCLK_DIV4)
	348	val \|= div_bit;
	349	else if (rate == EP93XX_KEYTCHCLK_DIV16)
	350	val &= ~div_bit;
	351	else
	352	return -EINVAL;
	353
	354	ep93xx_syscon_swlocked_write(val, clk->enable_reg);
	355	clk->rate = rate;
	356	return 0;
	357	}
	358
ebd00c08 HS	359	static int calc_clk_div(struct clk *clk, unsigned long rate,
ebd00c08 HS	360	int psel, int esel, int pdiv, int div)
c6012189	361	{
ebd00c08 HS	362	struct clk *mclk;
ebd00c08 HS	363	unsigned long max_rate, actual_rate, mclk_rate, rate_err = -1;
c6012189 RM	364	int i, found = 0, __div = 0, __pdiv = 0;
	365
	366	/* Don't exceed the maximum rate */
732eacc0	367	max_rate = max3(clk_pll1.rate / 4, clk_pll2.rate / 4, clk_xtali.rate / 4);
c6012189 RM	368	rate = min(rate, max_rate);
	369
	370	/*
	371	* Try the two pll's and the external clock
	372	* Because the valid predividers are 2, 2.5 and 3, we multiply
	373	* all the clocks by 2 to avoid floating point math.
	374	*
	375	* This is based on the algorithm in the ep93xx raster guide:
	376	* http://be-a-maverick.com/en/pubs/appNote/AN269REV1.pdf
	377	*
	378	*/
	379	for (i = 0; i < 3; i++) {
	380	if (i == 0)
ebd00c08	381	mclk = &clk_xtali;
c6012189	382	else if (i == 1)
ebd00c08 HS	383	mclk = &clk_pll1;
	384	else
	385	mclk = &clk_pll2;
	386	mclk_rate = mclk->rate * 2;
c6012189 RM	387
	388	/* Try each predivider value */
	389	for (__pdiv = 4; __pdiv <= 6; __pdiv++) {
	390	__div = mclk_rate / (rate * __pdiv);
	391	if (__div < 2 \|\| __div > 127)
	392	continue;
	393
	394	actual_rate = mclk_rate / (__pdiv * __div);
	395
	396	if (!found \|\| abs(actual_rate - rate) < rate_err) {
	397	*pdiv = __pdiv - 3;
	398	*div = __div;
	399	*psel = (i == 2);
	400	*esel = (i != 0);
ebd00c08 HS	401	clk->parent = mclk;
ebd00c08 HS	402	clk->rate = actual_rate;
c6012189 RM	403	rate_err = abs(actual_rate - rate);
	404	found = 1;
	405	}
	406	}
	407	}
	408
	409	if (!found)
ebd00c08	410	return -EINVAL;
c6012189	411
ebd00c08	412	return 0;
c6012189 RM	413	}
	414
	415	static int set_div_rate(struct clk *clk, unsigned long rate)
	416	{
ebd00c08	417	int err, psel = 0, esel = 0, pdiv = 0, div = 0;
c6012189 RM	418	u32 val;
c6012189 RM	419
ebd00c08 HS	420	err = calc_clk_div(clk, rate, &psel, &esel, &pdiv, &div);
	421	if (err)
	422	return err;
c6012189 RM	423
	424	/* Clear the esel, psel, pdiv and div bits */
	425	val = __raw_readl(clk->enable_reg);
	426	val &= ~0x7fff;
	427
	428	/* Set the new esel, psel, pdiv and div bits for the new clock rate */
	429	val \|= (esel ? EP93XX_SYSCON_CLKDIV_ESEL : 0) \|
	430	(psel ? EP93XX_SYSCON_CLKDIV_PSEL : 0) \|
	431	(pdiv << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) \| div;
	432	ep93xx_syscon_swlocked_write(val, clk->enable_reg);
	433	return 0;
	434	}
	435
ed67ea82 RM	436	static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate)
	437	{
	438	unsigned val = __raw_readl(clk->enable_reg);
	439
	440	if (rate == clk_i2s_mclk.rate / 2)
	441	ep93xx_syscon_swlocked_write(val & ~EP93XX_I2SCLKDIV_SDIV,
	442	clk->enable_reg);
	443	else if (rate == clk_i2s_mclk.rate / 4)
	444	ep93xx_syscon_swlocked_write(val \| EP93XX_I2SCLKDIV_SDIV,
	445	clk->enable_reg);
	446	else
	447	return -EINVAL;
	448
	449	clk_i2s_sclk.rate = rate;
	450	return 0;
	451	}
	452
	453	static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate)
	454	{
	455	unsigned val = __raw_readl(clk->enable_reg) &
	456	~EP93XX_I2SCLKDIV_LRDIV_MASK;
	457
	458	if (rate == clk_i2s_sclk.rate / 32)
	459	ep93xx_syscon_swlocked_write(val \| EP93XX_I2SCLKDIV_LRDIV32,
	460	clk->enable_reg);
	461	else if (rate == clk_i2s_sclk.rate / 64)
	462	ep93xx_syscon_swlocked_write(val \| EP93XX_I2SCLKDIV_LRDIV64,
	463	clk->enable_reg);
	464	else if (rate == clk_i2s_sclk.rate / 128)
	465	ep93xx_syscon_swlocked_write(val \| EP93XX_I2SCLKDIV_LRDIV128,
	466	clk->enable_reg);
	467	else
	468	return -EINVAL;
	469
	470	clk_i2s_lrclk.rate = rate;
	471	return 0;
	472	}
	473
701fac82 HS	474	int clk_set_rate(struct clk *clk, unsigned long rate)
	475	{
	476	if (clk->set_rate)
	477	return clk->set_rate(clk, rate);
	478
	479	return -EINVAL;
	480	}
	481	EXPORT_SYMBOL(clk_set_rate);
	482
ef8aa4e0 AS	483	long clk_round_rate(struct clk *clk, unsigned long rate)
	484	{
	485	WARN_ON(clk);
	486	return 0;
	487	}
	488	EXPORT_SYMBOL(clk_round_rate);
	489
	490	int clk_set_parent(struct clk clk, struct clk parent)
	491	{
	492	WARN_ON(clk);
	493	return 0;
	494	}
	495	EXPORT_SYMBOL(clk_set_parent);
	496
	497	struct clk clk_get_parent(struct clk clk)
	498	{
	499	return clk->parent;
	500	}
	501	EXPORT_SYMBOL(clk_get_parent);
	502
1d81eedb LB	503
	504	static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
	505	static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
	506	static char pclk_divisors[] = { 1, 2, 4, 8 };
	507
	508	/*
	509	* PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS
	510	*/
	511	static unsigned long calc_pll_rate(u32 config_word)
	512	{
	513	unsigned long long rate;
	514	int i;
	515
ebd00c08	516	rate = clk_xtali.rate;
1d81eedb LB	517	rate = ((config_word >> 11) & 0x1f) + 1; / X1FBD */
	518	rate = ((config_word >> 5) & 0x3f) + 1; / X2FBD */
	519	do_div(rate, (config_word & 0x1f) + 1); /* X2IPD */
	520	for (i = 0; i < ((config_word >> 16) & 3); i++) /* PS */
	521	rate >>= 1;
	522
	523	return (unsigned long)rate;
	524	}
	525
1c8daabe RM	526	static void __init ep93xx_dma_clock_init(void)
	527	{
	528	clk_m2p0.rate = clk_h.rate;
	529	clk_m2p1.rate = clk_h.rate;
	530	clk_m2p2.rate = clk_h.rate;
	531	clk_m2p3.rate = clk_h.rate;
	532	clk_m2p4.rate = clk_h.rate;
	533	clk_m2p5.rate = clk_h.rate;
	534	clk_m2p6.rate = clk_h.rate;
	535	clk_m2p7.rate = clk_h.rate;
	536	clk_m2p8.rate = clk_h.rate;
	537	clk_m2p9.rate = clk_h.rate;
	538	clk_m2m0.rate = clk_h.rate;
	539	clk_m2m1.rate = clk_h.rate;
	540	}
	541
51dd249e	542	static int __init ep93xx_clock_init(void)
1d81eedb LB	543	{
	544	u32 value;
	545
346e34ab HS	546	/* Determine the bootloader configured pll1 rate */
	547	value = __raw_readl(EP93XX_SYSCON_CLKSET1);
	548	if (!(value & EP93XX_SYSCON_CLKSET1_NBYP1))
ebd00c08	549	clk_pll1.rate = clk_xtali.rate;
346e34ab	550	else
1d81eedb	551	clk_pll1.rate = calc_pll_rate(value);
346e34ab HS	552
346e34ab HS	553	/* Initialize the pll1 derived clocks */
1d81eedb LB	554	clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7];
	555	clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7];
	556	clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3];
1c8daabe	557	ep93xx_dma_clock_init();
1d81eedb	558
346e34ab	559	/* Determine the bootloader configured pll2 rate */
ba7c6a3b	560	value = __raw_readl(EP93XX_SYSCON_CLKSET2);
346e34ab	561	if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2))
ebd00c08	562	clk_pll2.rate = clk_xtali.rate;
346e34ab	563	else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN)
1d81eedb	564	clk_pll2.rate = calc_pll_rate(value);
346e34ab	565	else
1d81eedb	566	clk_pll2.rate = 0;
346e34ab HS	567
346e34ab HS	568	/* Initialize the pll2 derived clocks */
1d81eedb LB	569	clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1);
1d81eedb LB	570
4fec9978 MW	571	/*
	572	* EP93xx SSP clock rate was doubled in version E2. For more information
	573	* see:
	574	* http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
	575	*/
	576	if (ep93xx_chip_revision() < EP93XX_CHIP_REV_E2)
	577	clk_spi.rate /= 2;
	578
99acbb90	579	pr_info("PLL1 running at %ld MHz, PLL2 at %ld MHz\n",
1d81eedb	580	clk_pll1.rate / 1000000, clk_pll2.rate / 1000000);
99acbb90	581	pr_info("FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n",
1d81eedb LB	582	clk_f.rate / 1000000, clk_h.rate / 1000000,
1d81eedb LB	583	clk_p.rate / 1000000);
51dd249e	584
0a0300dc	585	clkdev_add_table(clocks, ARRAY_SIZE(clocks));
51dd249e	586	return 0;
1d81eedb	587	}
a387f0f5	588	postcore_initcall(ep93xx_clock_init);