[mirror_ubuntu-kernels.git] / arch / arm / mach-ep93xx / clock.c

/*
 * arch/arm/mach-ep93xx/clock.c
 * Clock control for Cirrus EP93xx chips.
 *
 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or (at
 * your option) any later version.
 */

#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/io.h>

#include <asm/clkdev.h>
#include <asm/div64.h>
#include <mach/hardware.h>

struct clk {
	unsigned long	rate;
	int		users;
	u32		enable_reg;
	u32		enable_mask;
};

static struct clk clk_uart = {
	.rate		= 14745600,
};
static struct clk clk_pll1;
static struct clk clk_f;
static struct clk clk_h;
static struct clk clk_p;
static struct clk clk_pll2;
static struct clk clk_usb_host = {
	.enable_reg	= EP93XX_SYSCON_CLOCK_CONTROL,
	.enable_mask	= EP93XX_SYSCON_CLOCK_USH_EN,
};

#define INIT_CK(dev,con,ck)					\
	{ .dev_id = dev, .con_id = con, .clk = ck }

static struct clk_lookup clocks[] = {
	INIT_CK("apb:uart1", NULL, &clk_uart),
	INIT_CK("apb:uart2", NULL, &clk_uart),
	INIT_CK("apb:uart3", NULL, &clk_uart),
	INIT_CK(NULL, "pll1", &clk_pll1),
	INIT_CK(NULL, "fclk", &clk_f),
	INIT_CK(NULL, "hclk", &clk_h),
	INIT_CK(NULL, "pclk", &clk_p),
	INIT_CK(NULL, "pll2", &clk_pll2),
	INIT_CK(NULL, "usb_host", &clk_usb_host),
};


int clk_enable(struct clk *clk)
{
	if (!clk->users++ && clk->enable_reg) {
		u32 value;

		value = __raw_readl(clk->enable_reg);
		__raw_writel(value | clk->enable_mask, clk->enable_reg);
	}

	return 0;
}
EXPORT_SYMBOL(clk_enable);

void clk_disable(struct clk *clk)
{
	if (!--clk->users && clk->enable_reg) {
		u32 value;

		value = __raw_readl(clk->enable_reg);
		__raw_writel(value & ~clk->enable_mask, clk->enable_reg);
	}
}
EXPORT_SYMBOL(clk_disable);

unsigned long clk_get_rate(struct clk *clk)
{
	return clk->rate;
}
EXPORT_SYMBOL(clk_get_rate);


static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
static char pclk_divisors[] = { 1, 2, 4, 8 };

/*
 * PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS
 */
static unsigned long calc_pll_rate(u32 config_word)
{
	unsigned long long rate;
	int i;

	rate = 14745600;
	rate *= ((config_word >> 11) & 0x1f) + 1;		/* X1FBD */
	rate *= ((config_word >> 5) & 0x3f) + 1;		/* X2FBD */
	do_div(rate, (config_word & 0x1f) + 1);			/* X2IPD */
	for (i = 0; i < ((config_word >> 16) & 3); i++)		/* PS */
		rate >>= 1;

	return (unsigned long)rate;
}

static int __init ep93xx_clock_init(void)
{
	u32 value;
	int i;

	value = __raw_readl(EP93XX_SYSCON_CLOCK_SET1);
	if (!(value & 0x00800000)) {			/* PLL1 bypassed?  */
		clk_pll1.rate = 14745600;
	} else {
		clk_pll1.rate = calc_pll_rate(value);
	}
	clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7];
	clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7];
	clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3];

	value = __raw_readl(EP93XX_SYSCON_CLOCK_SET2);
	if (!(value & 0x00080000)) {			/* PLL2 bypassed?  */
		clk_pll2.rate = 14745600;
	} else if (value & 0x00040000) {		/* PLL2 enabled?  */
		clk_pll2.rate = calc_pll_rate(value);
	} else {
		clk_pll2.rate = 0;
	}
	clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1);

	printk(KERN_INFO "ep93xx: PLL1 running at %ld MHz, PLL2 at %ld MHz\n",
		clk_pll1.rate / 1000000, clk_pll2.rate / 1000000);
	printk(KERN_INFO "ep93xx: FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n",
		clk_f.rate / 1000000, clk_h.rate / 1000000,
		clk_p.rate / 1000000);

	for (i = 0; i < ARRAY_SIZE(clocks); i++)
		clkdev_add(&clocks[i]);
	return 0;
}
arch_initcall(ep93xx_clock_init);
Commit	Line	Data
1d81eedb LB	1	/*
	2	* arch/arm/mach-ep93xx/clock.c
	3	* Clock control for Cirrus EP93xx chips.
	4	*
	5	* Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or (at
	10	* your option) any later version.
	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/clk.h>
	15	#include <linux/err.h>
51dd249e	16	#include <linux/module.h>
1d81eedb	17	#include <linux/string.h>
fced80c7	18	#include <linux/io.h>
ae696fd5 RK	19
ae696fd5 RK	20	#include <asm/clkdev.h>
1d81eedb	21	#include <asm/div64.h>
a09e64fb	22	#include <mach/hardware.h>
1d81eedb LB	23
1d81eedb LB	24	struct clk {
1d81eedb LB	25	unsigned long rate;
	26	int users;
	27	u32 enable_reg;
	28	u32 enable_mask;
	29	};
	30
ed519ded	31	static struct clk clk_uart = {
ed519ded RK	32	.rate = 14745600,
ed519ded RK	33	};
ae696fd5 RK	34	static struct clk clk_pll1;
	35	static struct clk clk_f;
	36	static struct clk clk_h;
	37	static struct clk clk_p;
	38	static struct clk clk_pll2;
1d81eedb	39	static struct clk clk_usb_host = {
1d81eedb LB	40	.enable_reg = EP93XX_SYSCON_CLOCK_CONTROL,
	41	.enable_mask = EP93XX_SYSCON_CLOCK_USH_EN,
	42	};
	43
ae696fd5 RK	44	#define INIT_CK(dev,con,ck) \
	45	{ .dev_id = dev, .con_id = con, .clk = ck }
	46
	47	static struct clk_lookup clocks[] = {
	48	INIT_CK("apb:uart1", NULL, &clk_uart),
	49	INIT_CK("apb:uart2", NULL, &clk_uart),
	50	INIT_CK("apb:uart3", NULL, &clk_uart),
	51	INIT_CK(NULL, "pll1", &clk_pll1),
	52	INIT_CK(NULL, "fclk", &clk_f),
	53	INIT_CK(NULL, "hclk", &clk_h),
	54	INIT_CK(NULL, "pclk", &clk_p),
	55	INIT_CK(NULL, "pll2", &clk_pll2),
	56	INIT_CK(NULL, "usb_host", &clk_usb_host),
1d81eedb LB	57	};
1d81eedb LB	58
1d81eedb LB	59
	60	int clk_enable(struct clk *clk)
	61	{
	62	if (!clk->users++ && clk->enable_reg) {
	63	u32 value;
	64
	65	value = __raw_readl(clk->enable_reg);
	66	__raw_writel(value \| clk->enable_mask, clk->enable_reg);
	67	}
	68
	69	return 0;
	70	}
0c5d5b70	71	EXPORT_SYMBOL(clk_enable);
1d81eedb LB	72
	73	void clk_disable(struct clk *clk)
	74	{
	75	if (!--clk->users && clk->enable_reg) {
	76	u32 value;
	77
	78	value = __raw_readl(clk->enable_reg);
	79	__raw_writel(value & ~clk->enable_mask, clk->enable_reg);
	80	}
	81	}
0c5d5b70	82	EXPORT_SYMBOL(clk_disable);
1d81eedb LB	83
	84	unsigned long clk_get_rate(struct clk *clk)
	85	{
	86	return clk->rate;
	87	}
0c5d5b70	88	EXPORT_SYMBOL(clk_get_rate);
1d81eedb	89
1d81eedb LB	90
	91	static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
	92	static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
	93	static char pclk_divisors[] = { 1, 2, 4, 8 };
	94
	95	/*
	96	* PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS
	97	*/
	98	static unsigned long calc_pll_rate(u32 config_word)
	99	{
	100	unsigned long long rate;
	101	int i;
	102
	103	rate = 14745600;
	104	rate = ((config_word >> 11) & 0x1f) + 1; / X1FBD */
	105	rate = ((config_word >> 5) & 0x3f) + 1; / X2FBD */
	106	do_div(rate, (config_word & 0x1f) + 1); /* X2IPD */
	107	for (i = 0; i < ((config_word >> 16) & 3); i++) /* PS */
	108	rate >>= 1;
	109
	110	return (unsigned long)rate;
	111	}
	112
51dd249e	113	static int __init ep93xx_clock_init(void)
1d81eedb LB	114	{
1d81eedb LB	115	u32 value;
ae696fd5	116	int i;
1d81eedb LB	117
	118	value = __raw_readl(EP93XX_SYSCON_CLOCK_SET1);
	119	if (!(value & 0x00800000)) { /* PLL1 bypassed? */
	120	clk_pll1.rate = 14745600;
	121	} else {
	122	clk_pll1.rate = calc_pll_rate(value);
	123	}
	124	clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7];
	125	clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7];
	126	clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3];
	127
	128	value = __raw_readl(EP93XX_SYSCON_CLOCK_SET2);
	129	if (!(value & 0x00080000)) { /* PLL2 bypassed? */
	130	clk_pll2.rate = 14745600;
	131	} else if (value & 0x00040000) { /* PLL2 enabled? */
	132	clk_pll2.rate = calc_pll_rate(value);
	133	} else {
	134	clk_pll2.rate = 0;
	135	}
	136	clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1);
	137
	138	printk(KERN_INFO "ep93xx: PLL1 running at %ld MHz, PLL2 at %ld MHz\n",
	139	clk_pll1.rate / 1000000, clk_pll2.rate / 1000000);
	140	printk(KERN_INFO "ep93xx: FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n",
	141	clk_f.rate / 1000000, clk_h.rate / 1000000,
	142	clk_p.rate / 1000000);
51dd249e	143
ae696fd5 RK	144	for (i = 0; i < ARRAY_SIZE(clocks); i++)
ae696fd5 RK	145	clkdev_add(&clocks[i]);
51dd249e	146	return 0;
1d81eedb	147	}
51dd249e	148	arch_initcall(ep93xx_clock_init);