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ARM: 6124/1: ep93xx: SPI driver platform support code
[mirror_ubuntu-jammy-kernel.git] / arch / arm / mach-ep93xx / core.c
CommitLineData
e7736d47
LB		 1/*
2 * arch/arm/mach-ep93xx/core.c
3 * Core routines for Cirrus EP93xx chips.
4 *
5 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
3c9a071d 6 * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
e7736d47
LB		 7 *
8 * Thanks go to Michael Burian and Ray Lehtiniemi for their key
9 * role in the ep93xx linux community.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 */
16
64d6882d
HS		 17#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
18
e7736d47
LB		 19#include <linux/kernel.h>
20#include <linux/init.h>
583ddafe 21#include <linux/platform_device.h>
e7736d47 22#include <linux/interrupt.h>
63890a0e 23#include <linux/dma-mapping.h>
e7736d47 24#include <linux/timex.h>
6bd4b382 25#include <linux/irq.h>
583ddafe
HS		 26#include <linux/io.h>
27#include <linux/gpio.h>
3aa7a9a3 28#include <linux/leds.h>
aee85fe8 29#include <linux/termios.h>
e7736d47 30#include <linux/amba/bus.h>
aee85fe8 31#include <linux/amba/serial.h>
d52a26a9
HS		 32#include <linux/i2c.h>
33#include <linux/i2c-gpio.h>
4fec9978 34#include <linux/spi/spi.h>
e7736d47 35
a09e64fb 36#include <mach/hardware.h>
c6012189 37#include <mach/fb.h>
12f56c68 38#include <mach/ep93xx_keypad.h>
4fec9978 39#include <mach/ep93xx_spi.h>
e7736d47
LB		 40
41#include <asm/mach/map.h>
42#include <asm/mach/time.h>
e7736d47
LB		 43
44#include <asm/hardware/vic.h>
45
46
47/*************************************************************************
48 * Static I/O mappings that are needed for all EP93xx platforms
49 *************************************************************************/
50static struct map_desc ep93xx_io_desc[] __initdata = {
51 {
52 .virtual = EP93XX_AHB_VIRT_BASE,
53 .pfn = __phys_to_pfn(EP93XX_AHB_PHYS_BASE),
54 .length = EP93XX_AHB_SIZE,
55 .type = MT_DEVICE,
56 }, {
57 .virtual = EP93XX_APB_VIRT_BASE,
58 .pfn = __phys_to_pfn(EP93XX_APB_PHYS_BASE),
59 .length = EP93XX_APB_SIZE,
60 .type = MT_DEVICE,
61 },
62};
63
64void __init ep93xx_map_io(void)
65{
66 iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc));
67}
68
69
70/*************************************************************************
71 * Timer handling for EP93xx
72 *************************************************************************
73 * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and
74 * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
75 * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz,
76 * is free-running, and can't generate interrupts.
77 *
78 * The 508 kHz timers are ideal for use for the timer interrupt, as the
79 * most common values of HZ divide 508 kHz nicely. We pick one of the 16
80 * bit timers (timer 1) since we don't need more than 16 bits of reload
81 * value as long as HZ >= 8.
82 *
83 * The higher clock rate of timer 4 makes it a better choice than the
84 * other timers for use in gettimeoffset(), while the fact that it can't
85 * generate interrupts means we don't have to worry about not being able
86 * to use this timer for something else. We also use timer 4 for keeping
87 * track of lost jiffies.
88 */
1587a373
HS		 89#define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x))
90#define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00)
91#define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04)
92#define EP93XX_TIMER1_CONTROL EP93XX_TIMER_REG(0x08)
93#define EP93XX_TIMER123_CONTROL_ENABLE (1 << 7)
94#define EP93XX_TIMER123_CONTROL_MODE (1 << 6)
95#define EP93XX_TIMER123_CONTROL_CLKSEL (1 << 3)
96#define EP93XX_TIMER1_CLEAR EP93XX_TIMER_REG(0x0c)
97#define EP93XX_TIMER2_LOAD EP93XX_TIMER_REG(0x20)
98#define EP93XX_TIMER2_VALUE EP93XX_TIMER_REG(0x24)
99#define EP93XX_TIMER2_CONTROL EP93XX_TIMER_REG(0x28)
100#define EP93XX_TIMER2_CLEAR EP93XX_TIMER_REG(0x2c)
101#define EP93XX_TIMER4_VALUE_LOW EP93XX_TIMER_REG(0x60)
102#define EP93XX_TIMER4_VALUE_HIGH EP93XX_TIMER_REG(0x64)
103#define EP93XX_TIMER4_VALUE_HIGH_ENABLE (1 << 8)
104#define EP93XX_TIMER3_LOAD EP93XX_TIMER_REG(0x80)
105#define EP93XX_TIMER3_VALUE EP93XX_TIMER_REG(0x84)
106#define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88)
107#define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c)
108
109#define EP93XX_TIMER123_CLOCK 508469
110#define EP93XX_TIMER4_CLOCK 983040
111
112#define TIMER1_RELOAD ((EP93XX_TIMER123_CLOCK / HZ) - 1)
af1057ab 113#define TIMER4_TICKS_PER_JIFFY DIV_ROUND_CLOSEST(CLOCK_TICK_RATE, HZ)
e7736d47 114
1587a373
HS		 115static unsigned int last_jiffy_time;
116
d5565f76 117static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
e7736d47 118{
1587a373 119 /* Writing any value clears the timer interrupt */
e7736d47 120 __raw_writel(1, EP93XX_TIMER1_CLEAR);
1587a373
HS		 121
122 /* Recover lost jiffies */
f869afab
LB		 123 while ((signed long)
124 (__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)
e7736d47
LB		 125 >= TIMER4_TICKS_PER_JIFFY) {
126 last_jiffy_time += TIMER4_TICKS_PER_JIFFY;
0cd61b68 127 timer_tick();
e7736d47
LB		 128 }
129
e7736d47
LB		 130 return IRQ_HANDLED;
131}
132
133static struct irqaction ep93xx_timer_irq = {
134 .name = "ep93xx timer",
b30fabad 135 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
e7736d47
LB		 136 .handler = ep93xx_timer_interrupt,
137};
138
139static void __init ep93xx_timer_init(void)
140{
1587a373
HS		 141 u32 tmode = EP93XX_TIMER123_CONTROL_MODE |
142 EP93XX_TIMER123_CONTROL_CLKSEL;
143
e7736d47 144 /* Enable periodic HZ timer. */
1587a373
HS		 145 __raw_writel(tmode, EP93XX_TIMER1_CONTROL);
146 __raw_writel(TIMER1_RELOAD, EP93XX_TIMER1_LOAD);
147 __raw_writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE,
148 EP93XX_TIMER1_CONTROL);
e7736d47
LB		 149
150 /* Enable lost jiffy timer. */
1587a373
HS		 151 __raw_writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE,
152 EP93XX_TIMER4_VALUE_HIGH);
e7736d47
LB		 153
154 setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
155}
156
157static unsigned long ep93xx_gettimeoffset(void)
158{
159 int offset;
160
161 offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time;
162
163 /* Calculate (1000000 / 983040) * offset. */
164 return offset + (53 * offset / 3072);
165}
166
167struct sys_timer ep93xx_timer = {
168 .init = ep93xx_timer_init,
169 .offset = ep93xx_gettimeoffset,
170};
171
172
173/*************************************************************************
174 * EP93xx IRQ handling
175 *************************************************************************/
d056ab78 176extern void ep93xx_gpio_init_irq(void);
bd20ff57 177
e7736d47
LB		 178void __init ep93xx_init_irq(void)
179{
5396730b
HS		 180 vic_init(EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
181 vic_init(EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0);
bd20ff57 182
d056ab78 183 ep93xx_gpio_init_irq();
e7736d47
LB		 184}
185
186
02239f0a
HS		 187/*************************************************************************
188 * EP93xx System Controller Software Locked register handling
189 *************************************************************************/
190
191/*
192 * syscon_swlock prevents anything else from writing to the syscon
193 * block while a software locked register is being written.
194 */
195static DEFINE_SPINLOCK(syscon_swlock);
196
fbeeea53 197void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg)
02239f0a
HS		 198{
199 unsigned long flags;
200
201 spin_lock_irqsave(&syscon_swlock, flags);
202
203 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
204 __raw_writel(val, reg);
205
206 spin_unlock_irqrestore(&syscon_swlock, flags);
207}
208EXPORT_SYMBOL(ep93xx_syscon_swlocked_write);
209
210void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
211{
212 unsigned long flags;
213 unsigned int val;
214
215 spin_lock_irqsave(&syscon_swlock, flags);
216
217 val = __raw_readl(EP93XX_SYSCON_DEVCFG);
218 val |= set_bits;
219 val &= ~clear_bits;
220 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
221 __raw_writel(val, EP93XX_SYSCON_DEVCFG);
222
223 spin_unlock_irqrestore(&syscon_swlock, flags);
224}
225EXPORT_SYMBOL(ep93xx_devcfg_set_clear);
226
99e6a23a
MW		 227/**
228 * ep93xx_chip_revision() - returns the EP93xx chip revision
229 *
230 * See <mach/platform.h> for more information.
231 */
232unsigned int ep93xx_chip_revision(void)
233{
234 unsigned int v;
235
236 v = __raw_readl(EP93XX_SYSCON_SYSCFG);
237 v &= EP93XX_SYSCON_SYSCFG_REV_MASK;
238 v >>= EP93XX_SYSCON_SYSCFG_REV_SHIFT;
239 return v;
240}
02239f0a 241
e7736d47
LB		 242/*************************************************************************
243 * EP93xx peripheral handling
244 *************************************************************************/
aee85fe8
LB		 245#define EP93XX_UART_MCR_OFFSET (0x0100)
246
247static void ep93xx_uart_set_mctrl(struct amba_device *dev,
248 void __iomem *base, unsigned int mctrl)
249{
250 unsigned int mcr;
251
252 mcr = 0;
253 if (!(mctrl & TIOCM_RTS))
254 mcr |= 2;
255 if (!(mctrl & TIOCM_DTR))
256 mcr |= 1;
257
258 __raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET);
259}
260
261static struct amba_pl010_data ep93xx_uart_data = {
262 .set_mctrl = ep93xx_uart_set_mctrl,
263};
264
265static struct amba_device uart1_device = {
266 .dev = {
1d559e29 267 .init_name = "apb:uart1",
aee85fe8
LB		 268 .platform_data = &ep93xx_uart_data,
269 },
270 .res = {
271 .start = EP93XX_UART1_PHYS_BASE,
272 .end = EP93XX_UART1_PHYS_BASE + 0x0fff,
273 .flags = IORESOURCE_MEM,
274 },
275 .irq = { IRQ_EP93XX_UART1, NO_IRQ },
276 .periphid = 0x00041010,
277};
278
279static struct amba_device uart2_device = {
280 .dev = {
1d559e29 281 .init_name = "apb:uart2",
aee85fe8
LB		 282 .platform_data = &ep93xx_uart_data,
283 },
284 .res = {
285 .start = EP93XX_UART2_PHYS_BASE,
286 .end = EP93XX_UART2_PHYS_BASE + 0x0fff,
287 .flags = IORESOURCE_MEM,
288 },
289 .irq = { IRQ_EP93XX_UART2, NO_IRQ },
290 .periphid = 0x00041010,
291};
292
293static struct amba_device uart3_device = {
294 .dev = {
1d559e29 295 .init_name = "apb:uart3",
aee85fe8
LB		 296 .platform_data = &ep93xx_uart_data,
297 },
298 .res = {
299 .start = EP93XX_UART3_PHYS_BASE,
300 .end = EP93XX_UART3_PHYS_BASE + 0x0fff,
301 .flags = IORESOURCE_MEM,
302 },
303 .irq = { IRQ_EP93XX_UART3, NO_IRQ },
304 .periphid = 0x00041010,
305};
306
41658132 307
38f7b009
HS		 308static struct resource ep93xx_rtc_resource[] = {
309 {
310 .start = EP93XX_RTC_PHYS_BASE,
311 .end = EP93XX_RTC_PHYS_BASE + 0x10c - 1,
312 .flags = IORESOURCE_MEM,
313 },
314};
315
41658132 316static struct platform_device ep93xx_rtc_device = {
38f7b009
HS		 317 .name = "ep93xx-rtc",
318 .id = -1,
319 .num_resources = ARRAY_SIZE(ep93xx_rtc_resource),
320 .resource = ep93xx_rtc_resource,
41658132
LB		 321};
322
323
1f64eb37
LB		 324static struct resource ep93xx_ohci_resources[] = {
325 [0] = {
326 .start = EP93XX_USB_PHYS_BASE,
327 .end = EP93XX_USB_PHYS_BASE + 0x0fff,
328 .flags = IORESOURCE_MEM,
329 },
330 [1] = {
331 .start = IRQ_EP93XX_USB,
332 .end = IRQ_EP93XX_USB,
333 .flags = IORESOURCE_IRQ,
334 },
335};
336
63890a0e 337
1f64eb37
LB		 338static struct platform_device ep93xx_ohci_device = {
339 .name = "ep93xx-ohci",
340 .id = -1,
341 .dev = {
63890a0e
MK		 342 .dma_mask = &ep93xx_ohci_device.dev.coherent_dma_mask,
343 .coherent_dma_mask = DMA_BIT_MASK(32),
1f64eb37
LB		 344 },
345 .num_resources = ARRAY_SIZE(ep93xx_ohci_resources),
346 .resource = ep93xx_ohci_resources,
347};
348
b370e082
HS		 349
350/*************************************************************************
351 * EP93xx ethernet peripheral handling
352 *************************************************************************/
a0a08fdc
HS		 353static struct ep93xx_eth_data ep93xx_eth_data;
354
355static struct resource ep93xx_eth_resource[] = {
356 {
357 .start = EP93XX_ETHERNET_PHYS_BASE,
358 .end = EP93XX_ETHERNET_PHYS_BASE + 0xffff,
359 .flags = IORESOURCE_MEM,
360 }, {
361 .start = IRQ_EP93XX_ETHERNET,
362 .end = IRQ_EP93XX_ETHERNET,
363 .flags = IORESOURCE_IRQ,
364 }
365};
366
367static struct platform_device ep93xx_eth_device = {
368 .name = "ep93xx-eth",
369 .id = -1,
370 .dev = {
371 .platform_data = &ep93xx_eth_data,
372 },
373 .num_resources = ARRAY_SIZE(ep93xx_eth_resource),
374 .resource = ep93xx_eth_resource,
375};
376
b370e082
HS		 377/**
378 * ep93xx_register_eth - Register the built-in ethernet platform device.
379 * @data: platform specific ethernet configuration (__initdata)
380 * @copy_addr: flag indicating that the MAC address should be copied
381 * from the IndAd registers (as programmed by the bootloader)
382 */
a0a08fdc
HS		 383void __init ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr)
384{
5b1c3c85
HS		 385 if (copy_addr)
386 memcpy_fromio(data->dev_addr, EP93XX_ETHERNET_BASE + 0x50, 6);
a0a08fdc
HS		 387
388 ep93xx_eth_data = *data;
389 platform_device_register(&ep93xx_eth_device);
390}
391
6531a991
HS		 392
393/*************************************************************************
394 * EP93xx i2c peripheral handling
395 *************************************************************************/
396static struct i2c_gpio_platform_data ep93xx_i2c_data;
d52a26a9
HS		 397
398static struct platform_device ep93xx_i2c_device = {
b370e082
HS		 399 .name = "i2c-gpio",
400 .id = 0,
401 .dev = {
402 .platform_data = &ep93xx_i2c_data,
403 },
d52a26a9
HS		 404};
405
b370e082
HS		 406/**
407 * ep93xx_register_i2c - Register the i2c platform device.
408 * @data: platform specific i2c-gpio configuration (__initdata)
409 * @devices: platform specific i2c bus device information (__initdata)
410 * @num: the number of devices on the i2c bus
411 */
6531a991
HS		 412void __init ep93xx_register_i2c(struct i2c_gpio_platform_data *data,
413 struct i2c_board_info *devices, int num)
d52a26a9 414{
6531a991
HS		 415 /*
416 * Set the EEPROM interface pin drive type control.
417 * Defines the driver type for the EECLK and EEDAT pins as either
418 * open drain, which will require an external pull-up, or a normal
419 * CMOS driver.
420 */
421 if (data->sda_is_open_drain && data->sda_pin != EP93XX_GPIO_LINE_EEDAT)
64d6882d 422 pr_warning("sda != EEDAT, open drain has no effect\n");
6531a991 423 if (data->scl_is_open_drain && data->scl_pin != EP93XX_GPIO_LINE_EECLK)
64d6882d 424 pr_warning("scl != EECLK, open drain has no effect\n");
6531a991
HS		 425
426 __raw_writel((data->sda_is_open_drain << 1) |
427 (data->scl_is_open_drain << 0),
428 EP93XX_GPIO_EEDRIVE);
429
430 ep93xx_i2c_data = *data;
d52a26a9
HS		 431 i2c_register_board_info(0, devices, num);
432 platform_device_register(&ep93xx_i2c_device);
433}
434
4fec9978
MW		 435/*************************************************************************
436 * EP93xx SPI peripheral handling
437 *************************************************************************/
438static struct ep93xx_spi_info ep93xx_spi_master_data;
439
440static struct resource ep93xx_spi_resources[] = {
441 {
442 .start = EP93XX_SPI_PHYS_BASE,
443 .end = EP93XX_SPI_PHYS_BASE + 0x18 - 1,
444 .flags = IORESOURCE_MEM,
445 },
446 {
447 .start = IRQ_EP93XX_SSP,
448 .end = IRQ_EP93XX_SSP,
449 .flags = IORESOURCE_IRQ,
450 },
451};
452
453static struct platform_device ep93xx_spi_device = {
454 .name = "ep93xx-spi",
455 .id = 0,
456 .dev = {
457 .platform_data = &ep93xx_spi_master_data,
458 },
459 .num_resources = ARRAY_SIZE(ep93xx_spi_resources),
460 .resource = ep93xx_spi_resources,
461};
462
463/**
464 * ep93xx_register_spi() - registers spi platform device
465 * @info: ep93xx board specific spi master info (__initdata)
466 * @devices: SPI devices to register (__initdata)
467 * @num: number of SPI devices to register
468 *
469 * This function registers platform device for the EP93xx SPI controller and
470 * also makes sure that SPI pins are muxed so that I2S is not using those pins.
471 */
472void __init ep93xx_register_spi(struct ep93xx_spi_info *info,
473 struct spi_board_info *devices, int num)
474{
475 /*
476 * When SPI is used, we need to make sure that I2S is muxed off from
477 * SPI pins.
478 */
479 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2SONSSP);
480
481 ep93xx_spi_master_data = *info;
482 spi_register_board_info(devices, num);
483 platform_device_register(&ep93xx_spi_device);
484}
3aa7a9a3
HS		 485
486/*************************************************************************
487 * EP93xx LEDs
488 *************************************************************************/
489static struct gpio_led ep93xx_led_pins[] = {
490 {
b370e082
HS		 491 .name = "platform:grled",
492 .gpio = EP93XX_GPIO_LINE_GRLED,
3aa7a9a3 493 }, {
b370e082
HS		 494 .name = "platform:rdled",
495 .gpio = EP93XX_GPIO_LINE_RDLED,
3aa7a9a3
HS		 496 },
497};
498
499static struct gpio_led_platform_data ep93xx_led_data = {
500 .num_leds = ARRAY_SIZE(ep93xx_led_pins),
501 .leds = ep93xx_led_pins,
502};
503
504static struct platform_device ep93xx_leds = {
505 .name = "leds-gpio",
506 .id = -1,
507 .dev = {
508 .platform_data = &ep93xx_led_data,
509 },
510};
511
512
ef12379f
HS		 513/*************************************************************************
514 * EP93xx pwm peripheral handling
515 *************************************************************************/
516static struct resource ep93xx_pwm0_resource[] = {
517 {
518 .start = EP93XX_PWM_PHYS_BASE,
519 .end = EP93XX_PWM_PHYS_BASE + 0x10 - 1,
520 .flags = IORESOURCE_MEM,
521 },
522};
523
524static struct platform_device ep93xx_pwm0_device = {
525 .name = "ep93xx-pwm",
526 .id = 0,
527 .num_resources = ARRAY_SIZE(ep93xx_pwm0_resource),
528 .resource = ep93xx_pwm0_resource,
529};
530
531static struct resource ep93xx_pwm1_resource[] = {
532 {
533 .start = EP93XX_PWM_PHYS_BASE + 0x20,
534 .end = EP93XX_PWM_PHYS_BASE + 0x30 - 1,
535 .flags = IORESOURCE_MEM,
536 },
537};
538
539static struct platform_device ep93xx_pwm1_device = {
540 .name = "ep93xx-pwm",
541 .id = 1,
542 .num_resources = ARRAY_SIZE(ep93xx_pwm1_resource),
543 .resource = ep93xx_pwm1_resource,
544};
545
546void __init ep93xx_register_pwm(int pwm0, int pwm1)
547{
548 if (pwm0)
549 platform_device_register(&ep93xx_pwm0_device);
550
551 /* NOTE: EP9307 does not have PWMOUT1 (pin EGPIO14) */
552 if (pwm1)
553 platform_device_register(&ep93xx_pwm1_device);
554}
555
556int ep93xx_pwm_acquire_gpio(struct platform_device *pdev)
557{
558 int err;
559
560 if (pdev->id == 0) {
561 err = 0;
562 } else if (pdev->id == 1) {
563 err = gpio_request(EP93XX_GPIO_LINE_EGPIO14,
564 dev_name(&pdev->dev));
565 if (err)
566 return err;
567 err = gpio_direction_output(EP93XX_GPIO_LINE_EGPIO14, 0);
568 if (err)
569 goto fail;
570
571 /* PWM 1 output on EGPIO[14] */
572 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_PONG);
573 } else {
574 err = -ENODEV;
575 }
576
577 return err;
578
579fail:
580 gpio_free(EP93XX_GPIO_LINE_EGPIO14);
581 return err;
582}
583EXPORT_SYMBOL(ep93xx_pwm_acquire_gpio);
584
585void ep93xx_pwm_release_gpio(struct platform_device *pdev)
586{
587 if (pdev->id == 1) {
588 gpio_direction_input(EP93XX_GPIO_LINE_EGPIO14);
589 gpio_free(EP93XX_GPIO_LINE_EGPIO14);
590
591 /* EGPIO[14] used for GPIO */
592 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_PONG);
593 }
594}
595EXPORT_SYMBOL(ep93xx_pwm_release_gpio);
596
597
c6012189
RM		 598/*************************************************************************
599 * EP93xx video peripheral handling
600 *************************************************************************/
601static struct ep93xxfb_mach_info ep93xxfb_data;
602
603static struct resource ep93xx_fb_resource[] = {
604 {
605 .start = EP93XX_RASTER_PHYS_BASE,
606 .end = EP93XX_RASTER_PHYS_BASE + 0x800 - 1,
607 .flags = IORESOURCE_MEM,
608 },
609};
610
611static struct platform_device ep93xx_fb_device = {
612 .name = "ep93xx-fb",
613 .id = -1,
614 .dev = {
b370e082 615 .platform_data = &ep93xxfb_data,
c6012189
RM		 616 .coherent_dma_mask = DMA_BIT_MASK(32),
617 .dma_mask = &ep93xx_fb_device.dev.coherent_dma_mask,
618 },
619 .num_resources = ARRAY_SIZE(ep93xx_fb_resource),
620 .resource = ep93xx_fb_resource,
621};
622
b370e082
HS		 623/**
624 * ep93xx_register_fb - Register the framebuffer platform device.
625 * @data: platform specific framebuffer configuration (__initdata)
626 */
c6012189
RM		 627void __init ep93xx_register_fb(struct ep93xxfb_mach_info *data)
628{
629 ep93xxfb_data = *data;
630 platform_device_register(&ep93xx_fb_device);
631}
632
12f56c68
HS		 633
634/*************************************************************************
635 * EP93xx matrix keypad peripheral handling
636 *************************************************************************/
b370e082
HS		 637static struct ep93xx_keypad_platform_data ep93xx_keypad_data;
638
12f56c68
HS		 639static struct resource ep93xx_keypad_resource[] = {
640 {
641 .start = EP93XX_KEY_MATRIX_PHYS_BASE,
642 .end = EP93XX_KEY_MATRIX_PHYS_BASE + 0x0c - 1,
643 .flags = IORESOURCE_MEM,
644 }, {
645 .start = IRQ_EP93XX_KEY,
646 .end = IRQ_EP93XX_KEY,
647 .flags = IORESOURCE_IRQ,
648 },
649};
650
651static struct platform_device ep93xx_keypad_device = {
b370e082
HS		 652 .name = "ep93xx-keypad",
653 .id = -1,
654 .dev = {
655 .platform_data = &ep93xx_keypad_data,
656 },
657 .num_resources = ARRAY_SIZE(ep93xx_keypad_resource),
658 .resource = ep93xx_keypad_resource,
12f56c68
HS		 659};
660
b370e082
HS		 661/**
662 * ep93xx_register_keypad - Register the keypad platform device.
663 * @data: platform specific keypad configuration (__initdata)
664 */
12f56c68
HS		 665void __init ep93xx_register_keypad(struct ep93xx_keypad_platform_data *data)
666{
b370e082 667 ep93xx_keypad_data = *data;
12f56c68
HS		 668 platform_device_register(&ep93xx_keypad_device);
669}
670
671int ep93xx_keypad_acquire_gpio(struct platform_device *pdev)
672{
673 int err;
674 int i;
675
676 for (i = 0; i < 8; i++) {
677 err = gpio_request(EP93XX_GPIO_LINE_C(i), dev_name(&pdev->dev));
678 if (err)
679 goto fail_gpio_c;
680 err = gpio_request(EP93XX_GPIO_LINE_D(i), dev_name(&pdev->dev));
681 if (err)
682 goto fail_gpio_d;
683 }
684
685 /* Enable the keypad controller; GPIO ports C and D used for keypad */
686 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_KEYS |
687 EP93XX_SYSCON_DEVCFG_GONK);
688
689 return 0;
690
691fail_gpio_d:
692 gpio_free(EP93XX_GPIO_LINE_C(i));
693fail_gpio_c:
694 for ( ; i >= 0; --i) {
695 gpio_free(EP93XX_GPIO_LINE_C(i));
696 gpio_free(EP93XX_GPIO_LINE_D(i));
697 }
698 return err;
699}
700EXPORT_SYMBOL(ep93xx_keypad_acquire_gpio);
701
702void ep93xx_keypad_release_gpio(struct platform_device *pdev)
703{
704 int i;
705
706 for (i = 0; i < 8; i++) {
707 gpio_free(EP93XX_GPIO_LINE_C(i));
708 gpio_free(EP93XX_GPIO_LINE_D(i));
709 }
710
711 /* Disable the keypad controller; GPIO ports C and D used for GPIO */
712 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS |
713 EP93XX_SYSCON_DEVCFG_GONK);
714}
715EXPORT_SYMBOL(ep93xx_keypad_release_gpio);
716
717
b685004f 718extern void ep93xx_gpio_init(void);
1f64eb37 719
e7736d47
LB		 720void __init ep93xx_init_devices(void)
721{
02239f0a
HS		 722 /* Disallow access to MaverickCrunch initially */
723 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA);
aee85fe8 724
b685004f
RM		 725 ep93xx_gpio_init();
726
aee85fe8
LB		 727 amba_device_register(&uart1_device, &iomem_resource);
728 amba_device_register(&uart2_device, &iomem_resource);
729 amba_device_register(&uart3_device, &iomem_resource);
41658132
LB		 730
731 platform_device_register(&ep93xx_rtc_device);
1f64eb37 732 platform_device_register(&ep93xx_ohci_device);
3aa7a9a3 733 platform_device_register(&ep93xx_leds);
e7736d47 734}
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