projects / mirror_ubuntu-jammy-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| e7736d47 | 1 | /* |
| a09e64fb | 2 | * arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h |
| e7736d47 LB |
3 | */ |
| 4 | ||
| 5 | #ifndef __ASM_ARCH_EP93XX_REGS_H | |
| 6 | #define __ASM_ARCH_EP93XX_REGS_H | |
| 7 | ||
| 446b097a HS |
8 | /* |
| 9 | * EP93xx Physical Memory Map: | |
| 10 | * | |
| 11 | * The ASDO pin is sampled at system reset to select a synchronous or | |
| 12 | * asynchronous boot configuration. When ASDO is "1" (i.e. pulled-up) | |
| 13 | * the synchronous boot mode is selected. When ASDO is "0" (i.e | |
| 14 | * pulled-down) the asynchronous boot mode is selected. | |
| 15 | * | |
| 16 | * In synchronous boot mode nSDCE3 is decoded starting at physical address | |
| 17 | * 0x00000000 and nCS0 is decoded starting at 0xf0000000. For asynchronous | |
| 18 | * boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3 | |
| 19 | * decoded at 0xf0000000. | |
| 20 | * | |
| 21 | * There is known errata for the EP93xx dealing with External Memory | |
| 22 | * Configurations. Please refer to "AN273: EP93xx Silicon Rev E Design | |
| 23 | * Guidelines" for more information. This document can be found at: | |
| 24 | * | |
| 25 | * http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf | |
| 26 | */ | |
| 27 | ||
| 28 | #define EP93XX_CS0_PHYS_BASE_ASYNC 0x00000000 /* ASDO Pin = 0 */ | |
| 29 | #define EP93XX_SDCE3_PHYS_BASE_SYNC 0x00000000 /* ASDO Pin = 1 */ | |
| 30 | #define EP93XX_CS1_PHYS_BASE 0x10000000 | |
| 31 | #define EP93XX_CS2_PHYS_BASE 0x20000000 | |
| 32 | #define EP93XX_CS3_PHYS_BASE 0x30000000 | |
| 33 | #define EP93XX_PCMCIA_PHYS_BASE 0x40000000 | |
| 34 | #define EP93XX_CS6_PHYS_BASE 0x60000000 | |
| 35 | #define EP93XX_CS7_PHYS_BASE 0x70000000 | |
| 36 | #define EP93XX_SDCE0_PHYS_BASE 0xc0000000 | |
| 37 | #define EP93XX_SDCE1_PHYS_BASE 0xd0000000 | |
| 38 | #define EP93XX_SDCE2_PHYS_BASE 0xe0000000 | |
| 39 | #define EP93XX_SDCE3_PHYS_BASE_ASYNC 0xf0000000 /* ASDO Pin = 0 */ | |
| 40 | #define EP93XX_CS0_PHYS_BASE_SYNC 0xf0000000 /* ASDO Pin = 1 */ | |
| 41 | ||
| e7736d47 LB |
42 | /* |
| 43 | * EP93xx linux memory map: | |
| 44 | * | |
| 45 | * virt phys size | |
| 46 | * fe800000 5M per-platform mappings | |
| 47 | * fed00000 80800000 2M APB | |
| 48 | * fef00000 80000000 1M AHB | |
| 49 | */ | |
| 50 | ||
| 51 | #define EP93XX_AHB_PHYS_BASE 0x80000000 | |
| 52 | #define EP93XX_AHB_VIRT_BASE 0xfef00000 | |
| 53 | #define EP93XX_AHB_SIZE 0x00100000 | |
| 54 | ||
| 591006f8 | 55 | #define EP93XX_AHB_PHYS(x) (EP93XX_AHB_PHYS_BASE + (x)) |
| 702b59e6 HS |
56 | #define EP93XX_AHB_IOMEM(x) IOMEM(EP93XX_AHB_VIRT_BASE + (x)) |
| 57 | ||
| e7736d47 LB |
58 | #define EP93XX_APB_PHYS_BASE 0x80800000 |
| 59 | #define EP93XX_APB_VIRT_BASE 0xfed00000 | |
| 60 | #define EP93XX_APB_SIZE 0x00200000 | |
| 61 | ||
| 591006f8 | 62 | #define EP93XX_APB_PHYS(x) (EP93XX_APB_PHYS_BASE + (x)) |
| 702b59e6 HS |
63 | #define EP93XX_APB_IOMEM(x) IOMEM(EP93XX_APB_VIRT_BASE + (x)) |
| 64 | ||
| e7736d47 LB |
65 | |
| 66 | /* AHB peripherals */ | |
| 702b59e6 | 67 | #define EP93XX_DMA_BASE EP93XX_AHB_IOMEM(0x00000000) |
| e7736d47 | 68 | |
| 591006f8 | 69 | #define EP93XX_ETHERNET_PHYS_BASE EP93XX_AHB_PHYS(0x00010000) |
| 702b59e6 | 70 | #define EP93XX_ETHERNET_BASE EP93XX_AHB_IOMEM(0x00010000) |
| e7736d47 | 71 | |
| 591006f8 | 72 | #define EP93XX_USB_PHYS_BASE EP93XX_AHB_PHYS(0x00020000) |
| 702b59e6 | 73 | #define EP93XX_USB_BASE EP93XX_AHB_IOMEM(0x00020000) |
| e7736d47 | 74 | |
| 591006f8 | 75 | #define EP93XX_RASTER_PHYS_BASE EP93XX_AHB_PHYS(0x00030000) |
| 702b59e6 | 76 | #define EP93XX_RASTER_BASE EP93XX_AHB_IOMEM(0x00030000) |
| e7736d47 | 77 | |
| 702b59e6 | 78 | #define EP93XX_GRAPHICS_ACCEL_BASE EP93XX_AHB_IOMEM(0x00040000) |
| e7736d47 | 79 | |
| 702b59e6 | 80 | #define EP93XX_SDRAM_CONTROLLER_BASE EP93XX_AHB_IOMEM(0x00060000) |
| e7736d47 | 81 | |
| 702b59e6 | 82 | #define EP93XX_PCMCIA_CONTROLLER_BASE EP93XX_AHB_IOMEM(0x00080000) |
| e7736d47 | 83 | |
| 702b59e6 | 84 | #define EP93XX_BOOT_ROM_BASE EP93XX_AHB_IOMEM(0x00090000) |
| e7736d47 | 85 | |
| 702b59e6 | 86 | #define EP93XX_IDE_BASE EP93XX_AHB_IOMEM(0x000a0000) |
| e7736d47 | 87 | |
| 702b59e6 | 88 | #define EP93XX_VIC1_BASE EP93XX_AHB_IOMEM(0x000b0000) |
| e7736d47 | 89 | |
| 702b59e6 | 90 | #define EP93XX_VIC2_BASE EP93XX_AHB_IOMEM(0x000c0000) |
| e7736d47 LB |
91 | |
| 92 | ||
| 93 | /* APB peripherals */ | |
| 702b59e6 | 94 | #define EP93XX_TIMER_BASE EP93XX_APB_IOMEM(0x00010000) |
| e7736d47 | 95 | |
| 702b59e6 | 96 | #define EP93XX_I2S_BASE EP93XX_APB_IOMEM(0x00020000) |
| e7736d47 | 97 | |
| 702b59e6 | 98 | #define EP93XX_SECURITY_BASE EP93XX_APB_IOMEM(0x00030000) |
| e7736d47 | 99 | |
| 702b59e6 | 100 | #define EP93XX_GPIO_BASE EP93XX_APB_IOMEM(0x00040000) |
| a8e19667 | 101 | #define EP93XX_GPIO_REG(x) (EP93XX_GPIO_BASE + (x)) |
| 4932e397 | 102 | #define EP93XX_GPIO_F_INT_STATUS EP93XX_GPIO_REG(0x5c) |
| bd20ff57 | 103 | #define EP93XX_GPIO_A_INT_STATUS EP93XX_GPIO_REG(0xa0) |
| bd20ff57 | 104 | #define EP93XX_GPIO_B_INT_STATUS EP93XX_GPIO_REG(0xbc) |
| 6531a991 | 105 | #define EP93XX_GPIO_EEDRIVE EP93XX_GPIO_REG(0xc8) |
| e7736d47 | 106 | |
| 702b59e6 | 107 | #define EP93XX_AAC_BASE EP93XX_APB_IOMEM(0x00080000) |
| e7736d47 | 108 | |
| 4fec9978 | 109 | #define EP93XX_SPI_PHYS_BASE EP93XX_APB_PHYS(0x000a0000) |
| 702b59e6 | 110 | #define EP93XX_SPI_BASE EP93XX_APB_IOMEM(0x000a0000) |
| e7736d47 | 111 | |
| 702b59e6 | 112 | #define EP93XX_IRDA_BASE EP93XX_APB_IOMEM(0x000b0000) |
| e7736d47 | 113 | |
| 591006f8 | 114 | #define EP93XX_UART1_PHYS_BASE EP93XX_APB_PHYS(0x000c0000) |
| 702b59e6 | 115 | #define EP93XX_UART1_BASE EP93XX_APB_IOMEM(0x000c0000) |
| e7736d47 | 116 | |
| 591006f8 | 117 | #define EP93XX_UART2_PHYS_BASE EP93XX_APB_PHYS(0x000d0000) |
| 702b59e6 | 118 | #define EP93XX_UART2_BASE EP93XX_APB_IOMEM(0x000d0000) |
| e7736d47 | 119 | |
| 591006f8 | 120 | #define EP93XX_UART3_PHYS_BASE EP93XX_APB_PHYS(0x000e0000) |
| 702b59e6 | 121 | #define EP93XX_UART3_BASE EP93XX_APB_IOMEM(0x000e0000) |
| e7736d47 | 122 | |
| 12f56c68 | 123 | #define EP93XX_KEY_MATRIX_PHYS_BASE EP93XX_APB_PHYS(0x000f0000) |
| 702b59e6 | 124 | #define EP93XX_KEY_MATRIX_BASE EP93XX_APB_IOMEM(0x000f0000) |
| e7736d47 | 125 | |
| 702b59e6 HS |
126 | #define EP93XX_ADC_BASE EP93XX_APB_IOMEM(0x00100000) |
| 127 | #define EP93XX_TOUCHSCREEN_BASE EP93XX_APB_IOMEM(0x00100000) | |
| e7736d47 | 128 | |
| 591006f8 | 129 | #define EP93XX_PWM_PHYS_BASE EP93XX_APB_PHYS(0x00110000) |
| 702b59e6 | 130 | #define EP93XX_PWM_BASE EP93XX_APB_IOMEM(0x00110000) |
| e7736d47 | 131 | |
| 591006f8 | 132 | #define EP93XX_RTC_PHYS_BASE EP93XX_APB_PHYS(0x00120000) |
| 702b59e6 | 133 | #define EP93XX_RTC_BASE EP93XX_APB_IOMEM(0x00120000) |
| e7736d47 | 134 | |
| 702b59e6 | 135 | #define EP93XX_SYSCON_BASE EP93XX_APB_IOMEM(0x00130000) |
| e7736d47 LB |
136 | #define EP93XX_SYSCON_REG(x) (EP93XX_SYSCON_BASE + (x)) |
| 137 | #define EP93XX_SYSCON_POWER_STATE EP93XX_SYSCON_REG(0x00) | |
| 40702432 HS |
138 | #define EP93XX_SYSCON_PWRCNT EP93XX_SYSCON_REG(0x04) |
| 139 | #define EP93XX_SYSCON_PWRCNT_FIR_EN (1<<31) | |
| 140 | #define EP93XX_SYSCON_PWRCNT_UARTBAUD (1<<29) | |
| 141 | #define EP93XX_SYSCON_PWRCNT_USH_EN (1<<28) | |
| 142 | #define EP93XX_SYSCON_PWRCNT_DMA_M2M1 (1<<27) | |
| 143 | #define EP93XX_SYSCON_PWRCNT_DMA_M2M0 (1<<26) | |
| 144 | #define EP93XX_SYSCON_PWRCNT_DMA_M2P8 (1<<25) | |
| 145 | #define EP93XX_SYSCON_PWRCNT_DMA_M2P9 (1<<24) | |
| 146 | #define EP93XX_SYSCON_PWRCNT_DMA_M2P6 (1<<23) | |
| 147 | #define EP93XX_SYSCON_PWRCNT_DMA_M2P7 (1<<22) | |
| 148 | #define EP93XX_SYSCON_PWRCNT_DMA_M2P4 (1<<21) | |
| 149 | #define EP93XX_SYSCON_PWRCNT_DMA_M2P5 (1<<20) | |
| 150 | #define EP93XX_SYSCON_PWRCNT_DMA_M2P2 (1<<19) | |
| 151 | #define EP93XX_SYSCON_PWRCNT_DMA_M2P3 (1<<18) | |
| 152 | #define EP93XX_SYSCON_PWRCNT_DMA_M2P0 (1<<17) | |
| 153 | #define EP93XX_SYSCON_PWRCNT_DMA_M2P1 (1<<16) | |
| e7736d47 LB |
154 | #define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08) |
| 155 | #define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c) | |
| 346e34ab HS |
156 | #define EP93XX_SYSCON_CLKSET1 EP93XX_SYSCON_REG(0x20) |
| 157 | #define EP93XX_SYSCON_CLKSET1_NBYP1 (1<<23) | |
| 158 | #define EP93XX_SYSCON_CLKSET2 EP93XX_SYSCON_REG(0x24) | |
| 159 | #define EP93XX_SYSCON_CLKSET2_NBYP2 (1<<19) | |
| 160 | #define EP93XX_SYSCON_CLKSET2_PLL2_EN (1<<18) | |
| 02239f0a HS |
161 | #define EP93XX_SYSCON_DEVCFG EP93XX_SYSCON_REG(0x80) |
| 162 | #define EP93XX_SYSCON_DEVCFG_SWRST (1<<31) | |
| 163 | #define EP93XX_SYSCON_DEVCFG_D1ONG (1<<30) | |
| 164 | #define EP93XX_SYSCON_DEVCFG_D0ONG (1<<29) | |
| 165 | #define EP93XX_SYSCON_DEVCFG_IONU2 (1<<28) | |
| 166 | #define EP93XX_SYSCON_DEVCFG_GONK (1<<27) | |
| 167 | #define EP93XX_SYSCON_DEVCFG_TONG (1<<26) | |
| 168 | #define EP93XX_SYSCON_DEVCFG_MONG (1<<25) | |
| 169 | #define EP93XX_SYSCON_DEVCFG_U3EN (1<<24) | |
| 170 | #define EP93XX_SYSCON_DEVCFG_CPENA (1<<23) | |
| 171 | #define EP93XX_SYSCON_DEVCFG_A2ONG (1<<22) | |
| 172 | #define EP93XX_SYSCON_DEVCFG_A1ONG (1<<21) | |
| 173 | #define EP93XX_SYSCON_DEVCFG_U2EN (1<<20) | |
| 174 | #define EP93XX_SYSCON_DEVCFG_EXVC (1<<19) | |
| 175 | #define EP93XX_SYSCON_DEVCFG_U1EN (1<<18) | |
| 176 | #define EP93XX_SYSCON_DEVCFG_TIN (1<<17) | |
| 177 | #define EP93XX_SYSCON_DEVCFG_HC3IN (1<<15) | |
| 178 | #define EP93XX_SYSCON_DEVCFG_HC3EN (1<<14) | |
| 179 | #define EP93XX_SYSCON_DEVCFG_HC1IN (1<<13) | |
| 180 | #define EP93XX_SYSCON_DEVCFG_HC1EN (1<<12) | |
| 181 | #define EP93XX_SYSCON_DEVCFG_HONIDE (1<<11) | |
| 182 | #define EP93XX_SYSCON_DEVCFG_GONIDE (1<<10) | |
| 183 | #define EP93XX_SYSCON_DEVCFG_PONG (1<<9) | |
| 184 | #define EP93XX_SYSCON_DEVCFG_EONIDE (1<<8) | |
| 185 | #define EP93XX_SYSCON_DEVCFG_I2SONSSP (1<<7) | |
| 186 | #define EP93XX_SYSCON_DEVCFG_I2SONAC97 (1<<6) | |
| 187 | #define EP93XX_SYSCON_DEVCFG_RASONP3 (1<<4) | |
| 188 | #define EP93XX_SYSCON_DEVCFG_RAS (1<<3) | |
| 189 | #define EP93XX_SYSCON_DEVCFG_ADCPD (1<<2) | |
| 190 | #define EP93XX_SYSCON_DEVCFG_KEYS (1<<1) | |
| 191 | #define EP93XX_SYSCON_DEVCFG_SHENA (1<<0) | |
| c6012189 RM |
192 | #define EP93XX_SYSCON_VIDCLKDIV EP93XX_SYSCON_REG(0x84) |
| 193 | #define EP93XX_SYSCON_CLKDIV_ENABLE (1<<15) | |
| 194 | #define EP93XX_SYSCON_CLKDIV_ESEL (1<<14) | |
| 195 | #define EP93XX_SYSCON_CLKDIV_PSEL (1<<13) | |
| 196 | #define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT 8 | |
| 5d43f11b HS |
197 | #define EP93XX_SYSCON_KEYTCHCLKDIV EP93XX_SYSCON_REG(0x90) |
| 198 | #define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN (1<<31) | |
| 199 | #define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV (1<<16) | |
| 200 | #define EP93XX_SYSCON_KEYTCHCLKDIV_KEN (1<<15) | |
| 201 | #define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV (1<<0) | |
| 14636005 HF |
202 | #define EP93XX_SYSCON_SYSCFG EP93XX_SYSCON_REG(0x9c) |
| 203 | #define EP93XX_SYSCON_SYSCFG_REV_MASK (0xf0000000) | |
| 204 | #define EP93XX_SYSCON_SYSCFG_REV_SHIFT (28) | |
| 205 | #define EP93XX_SYSCON_SYSCFG_SBOOT (1<<8) | |
| 206 | #define EP93XX_SYSCON_SYSCFG_LCSN7 (1<<7) | |
| 207 | #define EP93XX_SYSCON_SYSCFG_LCSN6 (1<<6) | |
| 208 | #define EP93XX_SYSCON_SYSCFG_LASDO (1<<5) | |
| 209 | #define EP93XX_SYSCON_SYSCFG_LEEDA (1<<4) | |
| 210 | #define EP93XX_SYSCON_SYSCFG_LEECLK (1<<3) | |
| 211 | #define EP93XX_SYSCON_SYSCFG_LCSN2 (1<<1) | |
| 212 | #define EP93XX_SYSCON_SYSCFG_LCSN1 (1<<0) | |
| e7736d47 LB |
213 | #define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0) |
| 214 | ||
| 702b59e6 | 215 | #define EP93XX_WATCHDOG_BASE EP93XX_APB_IOMEM(0x00140000) |
| e7736d47 LB |
216 | |
| 217 | ||
| 218 | #endif |