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[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-ep93xx / vision_ep9307.c
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1/*
2 * arch/arm/mach-ep93xx/vision_ep9307.c
3 * Vision Engraving Systems EP9307 SoM support.
4 *
5 * Copyright (C) 2008-2011 Vision Engraving Systems
6 * H Hartley Sweeten <hsweeten@visionengravers.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or (at
11 * your option) any later version.
12 */
13
14#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/irq.h>
20#include <linux/gpio.h>
21#include <linux/fb.h>
22#include <linux/io.h>
23#include <linux/mtd/partitions.h>
24#include <linux/i2c.h>
25#include <linux/i2c-gpio.h>
5877457a 26#include <linux/platform_data/pca953x.h>
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27#include <linux/spi/spi.h>
28#include <linux/spi/flash.h>
29#include <linux/spi/mmc_spi.h>
30#include <linux/mmc/host.h>
31
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32#include <sound/cs4271.h>
33
1cb17e2d 34#include <mach/hardware.h>
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35#include <linux/platform_data/video-ep93xx.h>
36#include <linux/platform_data/spi-ep93xx.h>
e9c6c5df 37#include <mach/gpio-ep93xx.h>
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38
39#include <asm/mach-types.h>
40#include <asm/mach/map.h>
41#include <asm/mach/arch.h>
42
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43#include "soc.h"
44
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45/*************************************************************************
46 * Static I/O mappings for the FPGA
47 *************************************************************************/
48#define VISION_PHYS_BASE EP93XX_CS7_PHYS_BASE
49#define VISION_VIRT_BASE 0xfebff000
50
51static struct map_desc vision_io_desc[] __initdata = {
52 {
53 .virtual = VISION_VIRT_BASE,
54 .pfn = __phys_to_pfn(VISION_PHYS_BASE),
55 .length = SZ_4K,
56 .type = MT_DEVICE,
57 },
58};
59
60static void __init vision_map_io(void)
61{
62 ep93xx_map_io();
63
64 iotable_init(vision_io_desc, ARRAY_SIZE(vision_io_desc));
65}
66
67/*************************************************************************
68 * Ethernet
69 *************************************************************************/
70static struct ep93xx_eth_data vision_eth_data __initdata = {
71 .phy_id = 1,
72};
73
74/*************************************************************************
75 * Framebuffer
76 *************************************************************************/
77#define VISION_LCD_ENABLE EP93XX_GPIO_LINE_EGPIO1
78
79static int vision_lcd_setup(struct platform_device *pdev)
80{
81 int err;
82
83 err = gpio_request_one(VISION_LCD_ENABLE, GPIOF_INIT_HIGH,
84 dev_name(&pdev->dev));
85 if (err)
86 return err;
87
88 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_RAS |
89 EP93XX_SYSCON_DEVCFG_RASONP3 |
90 EP93XX_SYSCON_DEVCFG_EXVC);
91
92 return 0;
93}
94
95static void vision_lcd_teardown(struct platform_device *pdev)
96{
97 gpio_free(VISION_LCD_ENABLE);
98}
99
100static void vision_lcd_blank(int blank_mode, struct fb_info *info)
101{
102 if (blank_mode)
103 gpio_set_value(VISION_LCD_ENABLE, 0);
104 else
105 gpio_set_value(VISION_LCD_ENABLE, 1);
106}
107
108static struct ep93xxfb_mach_info ep93xxfb_info __initdata = {
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109 .flags = EP93XXFB_USE_SDCSN0 | EP93XXFB_PCLK_FALLING,
110 .setup = vision_lcd_setup,
111 .teardown = vision_lcd_teardown,
112 .blank = vision_lcd_blank,
113};
114
115
116/*************************************************************************
117 * GPIO Expanders
118 *************************************************************************/
119#define PCA9539_74_GPIO_BASE (EP93XX_GPIO_LINE_MAX + 1)
120#define PCA9539_75_GPIO_BASE (PCA9539_74_GPIO_BASE + 16)
121#define PCA9539_76_GPIO_BASE (PCA9539_75_GPIO_BASE + 16)
122#define PCA9539_77_GPIO_BASE (PCA9539_76_GPIO_BASE + 16)
123
124static struct pca953x_platform_data pca953x_74_gpio_data = {
125 .gpio_base = PCA9539_74_GPIO_BASE,
126 .irq_base = EP93XX_BOARD_IRQ(0),
127};
128
129static struct pca953x_platform_data pca953x_75_gpio_data = {
130 .gpio_base = PCA9539_75_GPIO_BASE,
131 .irq_base = -1,
132};
133
134static struct pca953x_platform_data pca953x_76_gpio_data = {
135 .gpio_base = PCA9539_76_GPIO_BASE,
136 .irq_base = -1,
137};
138
139static struct pca953x_platform_data pca953x_77_gpio_data = {
140 .gpio_base = PCA9539_77_GPIO_BASE,
141 .irq_base = -1,
142};
143
144/*************************************************************************
145 * I2C Bus
146 *************************************************************************/
147static struct i2c_gpio_platform_data vision_i2c_gpio_data __initdata = {
148 .sda_pin = EP93XX_GPIO_LINE_EEDAT,
149 .scl_pin = EP93XX_GPIO_LINE_EECLK,
150};
151
152static struct i2c_board_info vision_i2c_info[] __initdata = {
153 {
154 I2C_BOARD_INFO("isl1208", 0x6f),
155 .irq = IRQ_EP93XX_EXT1,
156 }, {
157 I2C_BOARD_INFO("pca9539", 0x74),
158 .platform_data = &pca953x_74_gpio_data,
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159 }, {
160 I2C_BOARD_INFO("pca9539", 0x75),
161 .platform_data = &pca953x_75_gpio_data,
162 }, {
163 I2C_BOARD_INFO("pca9539", 0x76),
164 .platform_data = &pca953x_76_gpio_data,
165 }, {
166 I2C_BOARD_INFO("pca9539", 0x77),
167 .platform_data = &pca953x_77_gpio_data,
168 },
169};
170
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171/*************************************************************************
172 * SPI CS4271 Audio Codec
173 *************************************************************************/
174static struct cs4271_platform_data vision_cs4271_data = {
175 .gpio_nreset = EP93XX_GPIO_LINE_H(2),
176};
177
178static int vision_cs4271_hw_setup(struct spi_device *spi)
179{
180 return gpio_request_one(EP93XX_GPIO_LINE_EGPIO6,
181 GPIOF_OUT_INIT_HIGH, spi->modalias);
182}
183
184static void vision_cs4271_hw_cleanup(struct spi_device *spi)
185{
186 gpio_free(EP93XX_GPIO_LINE_EGPIO6);
187}
188
189static void vision_cs4271_hw_cs_control(struct spi_device *spi, int value)
190{
191 gpio_set_value(EP93XX_GPIO_LINE_EGPIO6, value);
192}
193
194static struct ep93xx_spi_chip_ops vision_cs4271_hw = {
195 .setup = vision_cs4271_hw_setup,
196 .cleanup = vision_cs4271_hw_cleanup,
197 .cs_control = vision_cs4271_hw_cs_control,
198};
199
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200/*************************************************************************
201 * SPI Flash
202 *************************************************************************/
203#define VISION_SPI_FLASH_CS EP93XX_GPIO_LINE_EGPIO7
204
205static struct mtd_partition vision_spi_flash_partitions[] = {
206 {
207 .name = "SPI bootstrap",
208 .offset = 0,
209 .size = SZ_4K,
210 }, {
211 .name = "Bootstrap config",
212 .offset = MTDPART_OFS_APPEND,
213 .size = SZ_4K,
214 }, {
215 .name = "System config",
216 .offset = MTDPART_OFS_APPEND,
217 .size = MTDPART_SIZ_FULL,
218 },
219};
220
221static struct flash_platform_data vision_spi_flash_data = {
222 .name = "SPI Flash",
223 .parts = vision_spi_flash_partitions,
224 .nr_parts = ARRAY_SIZE(vision_spi_flash_partitions),
225};
226
227static int vision_spi_flash_hw_setup(struct spi_device *spi)
228{
229 return gpio_request_one(VISION_SPI_FLASH_CS, GPIOF_INIT_HIGH,
230 spi->modalias);
231}
232
233static void vision_spi_flash_hw_cleanup(struct spi_device *spi)
234{
235 gpio_free(VISION_SPI_FLASH_CS);
236}
237
238static void vision_spi_flash_hw_cs_control(struct spi_device *spi, int value)
239{
240 gpio_set_value(VISION_SPI_FLASH_CS, value);
241}
242
243static struct ep93xx_spi_chip_ops vision_spi_flash_hw = {
244 .setup = vision_spi_flash_hw_setup,
245 .cleanup = vision_spi_flash_hw_cleanup,
246 .cs_control = vision_spi_flash_hw_cs_control,
247};
248
249/*************************************************************************
250 * SPI SD/MMC host
251 *************************************************************************/
252#define VISION_SPI_MMC_CS EP93XX_GPIO_LINE_G(2)
253#define VISION_SPI_MMC_WP EP93XX_GPIO_LINE_F(0)
254#define VISION_SPI_MMC_CD EP93XX_GPIO_LINE_EGPIO15
255
1cb17e2d 256static struct mmc_spi_platform_data vision_spi_mmc_data = {
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257 .detect_delay = 100,
258 .powerup_msecs = 100,
259 .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
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260 .flags = MMC_SPI_USE_CD_GPIO | MMC_SPI_USE_RO_GPIO,
261 .cd_gpio = VISION_SPI_MMC_CD,
262 .cd_debounce = 1,
263 .ro_gpio = VISION_SPI_MMC_WP,
264 .caps2 = MMC_CAP2_RO_ACTIVE_HIGH,
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265};
266
267static int vision_spi_mmc_hw_setup(struct spi_device *spi)
268{
269 return gpio_request_one(VISION_SPI_MMC_CS, GPIOF_INIT_HIGH,
270 spi->modalias);
271}
272
273static void vision_spi_mmc_hw_cleanup(struct spi_device *spi)
274{
275 gpio_free(VISION_SPI_MMC_CS);
276}
277
278static void vision_spi_mmc_hw_cs_control(struct spi_device *spi, int value)
279{
280 gpio_set_value(VISION_SPI_MMC_CS, value);
281}
282
283static struct ep93xx_spi_chip_ops vision_spi_mmc_hw = {
284 .setup = vision_spi_mmc_hw_setup,
285 .cleanup = vision_spi_mmc_hw_cleanup,
286 .cs_control = vision_spi_mmc_hw_cs_control,
287};
288
289/*************************************************************************
290 * SPI Bus
291 *************************************************************************/
292static struct spi_board_info vision_spi_board_info[] __initdata = {
293 {
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294 .modalias = "cs4271",
295 .platform_data = &vision_cs4271_data,
296 .controller_data = &vision_cs4271_hw,
297 .max_speed_hz = 6000000,
298 .bus_num = 0,
299 .chip_select = 0,
300 .mode = SPI_MODE_3,
301 }, {
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302 .modalias = "sst25l",
303 .platform_data = &vision_spi_flash_data,
304 .controller_data = &vision_spi_flash_hw,
305 .max_speed_hz = 20000000,
306 .bus_num = 0,
b07b4e29 307 .chip_select = 1,
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308 .mode = SPI_MODE_3,
309 }, {
310 .modalias = "mmc_spi",
311 .platform_data = &vision_spi_mmc_data,
312 .controller_data = &vision_spi_mmc_hw,
313 .max_speed_hz = 20000000,
314 .bus_num = 0,
b07b4e29 315 .chip_select = 2,
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316 .mode = SPI_MODE_3,
317 },
318};
319
320static struct ep93xx_spi_info vision_spi_master __initdata = {
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321 .num_chipselect = ARRAY_SIZE(vision_spi_board_info),
322 .use_dma = 1,
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323};
324
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325/*************************************************************************
326 * I2S Audio
327 *************************************************************************/
328static struct platform_device vision_audio_device = {
329 .name = "edb93xx-audio",
330 .id = -1,
331};
332
333static void __init vision_register_i2s(void)
334{
335 ep93xx_register_i2s();
336 platform_device_register(&vision_audio_device);
337}
338
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339/*************************************************************************
340 * Machine Initialization
341 *************************************************************************/
342static void __init vision_init_machine(void)
343{
344 ep93xx_init_devices();
345 ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_64M);
346 ep93xx_register_eth(&vision_eth_data, 1);
347 ep93xx_register_fb(&ep93xxfb_info);
348 ep93xx_register_pwm(1, 0);
349
350 /*
351 * Request the gpio expander's interrupt gpio line now to prevent
352 * the kernel from doing a WARN in gpiolib:gpio_ensure_requested().
353 */
354 if (gpio_request_one(EP93XX_GPIO_LINE_F(7), GPIOF_DIR_IN,
355 "pca9539:74"))
356 pr_warn("cannot request interrupt gpio for pca9539:74\n");
357
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358 vision_i2c_info[1].irq = gpio_to_irq(EP93XX_GPIO_LINE_F(7));
359
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360 ep93xx_register_i2c(&vision_i2c_gpio_data, vision_i2c_info,
361 ARRAY_SIZE(vision_i2c_info));
362 ep93xx_register_spi(&vision_spi_master, vision_spi_board_info,
363 ARRAY_SIZE(vision_spi_board_info));
b07b4e29 364 vision_register_i2s();
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365}
366
367MACHINE_START(VISION_EP9307, "Vision Engraving Systems EP9307")
368 /* Maintainer: H Hartley Sweeten <hsweeten@visionengravers.com> */
a7fadac1 369 .atag_offset = 0x100,
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370 .map_io = vision_map_io,
371 .init_irq = ep93xx_init_irq,
6bb27d73 372 .init_time = ep93xx_timer_init,
1cb17e2d 373 .init_machine = vision_init_machine,
c914283f 374 .init_late = ep93xx_init_late,
3275166e 375 .restart = ep93xx_restart,
1cb17e2d 376MACHINE_END