]>
Commit | Line | Data |
---|---|---|
ce9c00ee | 1 | /* |
a855039e | 2 | * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd. |
b3ed3a17 | 3 | * http://www.samsung.com |
c8bef140 | 4 | * |
b3ed3a17 | 5 | * EXYNOS4 - Clock support |
c8bef140 CY |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/err.h> | |
14 | #include <linux/io.h> | |
acd35616 | 15 | #include <linux/syscore_ops.h> |
c8bef140 CY |
16 | |
17 | #include <plat/cpu-freq.h> | |
18 | #include <plat/clock.h> | |
19 | #include <plat/cpu.h> | |
20 | #include <plat/pll.h> | |
21 | #include <plat/s5p-clock.h> | |
22 | #include <plat/clock-clksrc.h> | |
acd35616 | 23 | #include <plat/pm.h> |
c8bef140 CY |
24 | |
25 | #include <mach/map.h> | |
26 | #include <mach/regs-clock.h> | |
27 | ||
cc511b8d | 28 | #include "common.h" |
ce9c00ee | 29 | #include "clock-exynos4.h" |
cc511b8d | 30 | |
7cdf04d7 | 31 | #ifdef CONFIG_PM_SLEEP |
acd35616 | 32 | static struct sleep_save exynos4_clock_save[] = { |
a855039e KK |
33 | SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS), |
34 | SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS), | |
35 | SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS), | |
36 | SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS), | |
37 | SAVE_ITEM(EXYNOS4_CLKSRC_TOP0), | |
38 | SAVE_ITEM(EXYNOS4_CLKSRC_TOP1), | |
39 | SAVE_ITEM(EXYNOS4_CLKSRC_CAM), | |
40 | SAVE_ITEM(EXYNOS4_CLKSRC_TV), | |
41 | SAVE_ITEM(EXYNOS4_CLKSRC_MFC), | |
42 | SAVE_ITEM(EXYNOS4_CLKSRC_G3D), | |
43 | SAVE_ITEM(EXYNOS4_CLKSRC_LCD0), | |
44 | SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO), | |
45 | SAVE_ITEM(EXYNOS4_CLKSRC_FSYS), | |
46 | SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0), | |
47 | SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1), | |
48 | SAVE_ITEM(EXYNOS4_CLKDIV_CAM), | |
49 | SAVE_ITEM(EXYNOS4_CLKDIV_TV), | |
50 | SAVE_ITEM(EXYNOS4_CLKDIV_MFC), | |
51 | SAVE_ITEM(EXYNOS4_CLKDIV_G3D), | |
52 | SAVE_ITEM(EXYNOS4_CLKDIV_LCD0), | |
53 | SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO), | |
54 | SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0), | |
55 | SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1), | |
56 | SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2), | |
57 | SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3), | |
58 | SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0), | |
59 | SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1), | |
60 | SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2), | |
61 | SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3), | |
62 | SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4), | |
63 | SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5), | |
64 | SAVE_ITEM(EXYNOS4_CLKDIV_TOP), | |
65 | SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP), | |
66 | SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM), | |
67 | SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV), | |
68 | SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0), | |
69 | SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO), | |
70 | SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS), | |
71 | SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0), | |
72 | SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1), | |
73 | SAVE_ITEM(EXYNOS4_CLKDIV2_RATIO), | |
74 | SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM), | |
75 | SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM), | |
76 | SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV), | |
77 | SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC), | |
78 | SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D), | |
79 | SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0), | |
80 | SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS), | |
81 | SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS), | |
82 | SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL), | |
83 | SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK), | |
84 | SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC), | |
85 | SAVE_ITEM(EXYNOS4_CLKSRC_DMC), | |
86 | SAVE_ITEM(EXYNOS4_CLKDIV_DMC0), | |
87 | SAVE_ITEM(EXYNOS4_CLKDIV_DMC1), | |
88 | SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC), | |
89 | SAVE_ITEM(EXYNOS4_CLKSRC_CPU), | |
90 | SAVE_ITEM(EXYNOS4_CLKDIV_CPU), | |
91 | SAVE_ITEM(EXYNOS4_CLKDIV_CPU + 0x4), | |
92 | SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU), | |
93 | SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU), | |
acd35616 | 94 | }; |
7cdf04d7 | 95 | #endif |
acd35616 | 96 | |
a855039e | 97 | static struct clk exynos4_clk_sclk_hdmi27m = { |
c8bef140 | 98 | .name = "sclk_hdmi27m", |
c8bef140 CY |
99 | .rate = 27000000, |
100 | }; | |
101 | ||
a855039e | 102 | static struct clk exynos4_clk_sclk_hdmiphy = { |
b99380e1 | 103 | .name = "sclk_hdmiphy", |
b99380e1 JL |
104 | }; |
105 | ||
a855039e | 106 | static struct clk exynos4_clk_sclk_usbphy0 = { |
b99380e1 | 107 | .name = "sclk_usbphy0", |
b99380e1 JL |
108 | .rate = 27000000, |
109 | }; | |
110 | ||
a855039e | 111 | static struct clk exynos4_clk_sclk_usbphy1 = { |
b99380e1 | 112 | .name = "sclk_usbphy1", |
b99380e1 JL |
113 | }; |
114 | ||
bf856fbb BK |
115 | static struct clk dummy_apb_pclk = { |
116 | .name = "apb_pclk", | |
117 | .id = -1, | |
118 | }; | |
119 | ||
b3ed3a17 | 120 | static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable) |
37e01729 | 121 | { |
a855039e | 122 | return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable); |
37e01729 JL |
123 | } |
124 | ||
b3ed3a17 | 125 | static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable) |
33f469d2 | 126 | { |
a855039e | 127 | return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM, clk, enable); |
33f469d2 JL |
128 | } |
129 | ||
b3ed3a17 | 130 | static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable) |
33f469d2 | 131 | { |
a855039e | 132 | return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0, clk, enable); |
33f469d2 JL |
133 | } |
134 | ||
2bc02c0d | 135 | int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable) |
340ea1ef | 136 | { |
a855039e | 137 | return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS, clk, enable); |
340ea1ef JL |
138 | } |
139 | ||
b3ed3a17 | 140 | static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable) |
3297c2e6 | 141 | { |
a855039e | 142 | return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0, clk, enable); |
3297c2e6 JL |
143 | } |
144 | ||
b3ed3a17 | 145 | static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable) |
33f469d2 | 146 | { |
a855039e | 147 | return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1, clk, enable); |
33f469d2 JL |
148 | } |
149 | ||
b0b6ff0b KC |
150 | static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable) |
151 | { | |
a855039e | 152 | return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC, clk, enable); |
b0b6ff0b KC |
153 | } |
154 | ||
fbf05563 TS |
155 | static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable) |
156 | { | |
a855039e | 157 | return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV, clk, enable); |
fbf05563 TS |
158 | } |
159 | ||
b3ed3a17 | 160 | static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable) |
82260bf3 | 161 | { |
a855039e | 162 | return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM, clk, enable); |
82260bf3 JL |
163 | } |
164 | ||
b0b6ff0b KC |
165 | static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable) |
166 | { | |
a855039e | 167 | return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable); |
b0b6ff0b KC |
168 | } |
169 | ||
bca10b90 | 170 | int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable) |
82260bf3 | 171 | { |
a855039e | 172 | return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable); |
82260bf3 JL |
173 | } |
174 | ||
b3ed3a17 | 175 | static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable) |
82260bf3 | 176 | { |
a855039e | 177 | return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0, clk, enable); |
82260bf3 JL |
178 | } |
179 | ||
2bc02c0d | 180 | int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable) |
82260bf3 | 181 | { |
a855039e | 182 | return s5p_gatectrl(EXYNOS4210_CLKGATE_IP_LCD1, clk, enable); |
82260bf3 JL |
183 | } |
184 | ||
2bc02c0d | 185 | int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable) |
340ea1ef | 186 | { |
a855039e | 187 | return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS, clk, enable); |
340ea1ef JL |
188 | } |
189 | ||
b3ed3a17 | 190 | static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable) |
5a847b4a | 191 | { |
a855039e | 192 | return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL, clk, enable); |
5a847b4a JL |
193 | } |
194 | ||
b3ed3a17 | 195 | static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable) |
82260bf3 | 196 | { |
a855039e | 197 | return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable); |
82260bf3 JL |
198 | } |
199 | ||
bca10b90 KC |
200 | int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable) |
201 | { | |
202 | return s5p_gatectrl(EXYNOS4_CLKGATE_IP_DMC, clk, enable); | |
203 | } | |
204 | ||
fbf05563 TS |
205 | static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable) |
206 | { | |
207 | return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable); | |
208 | } | |
209 | ||
210 | static int exynos4_clk_dac_ctrl(struct clk *clk, int enable) | |
211 | { | |
212 | return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable); | |
213 | } | |
214 | ||
c8bef140 CY |
215 | /* Core list of CMU_CPU side */ |
216 | ||
a855039e | 217 | static struct clksrc_clk exynos4_clk_mout_apll = { |
c8bef140 CY |
218 | .clk = { |
219 | .name = "mout_apll", | |
c8bef140 | 220 | }, |
ce9c00ee | 221 | .sources = &clk_src_apll, |
a855039e | 222 | .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 0, .size = 1 }, |
3ff31020 JL |
223 | }; |
224 | ||
a855039e | 225 | static struct clksrc_clk exynos4_clk_sclk_apll = { |
3ff31020 JL |
226 | .clk = { |
227 | .name = "sclk_apll", | |
a855039e | 228 | .parent = &exynos4_clk_mout_apll.clk, |
3ff31020 | 229 | }, |
a855039e | 230 | .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 24, .size = 3 }, |
c8bef140 CY |
231 | }; |
232 | ||
a855039e | 233 | static struct clksrc_clk exynos4_clk_mout_epll = { |
c8bef140 CY |
234 | .clk = { |
235 | .name = "mout_epll", | |
c8bef140 | 236 | }, |
ce9c00ee | 237 | .sources = &clk_src_epll, |
a855039e | 238 | .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 4, .size = 1 }, |
c8bef140 CY |
239 | }; |
240 | ||
a855039e | 241 | struct clksrc_clk exynos4_clk_mout_mpll = { |
ce9c00ee | 242 | .clk = { |
c8bef140 | 243 | .name = "mout_mpll", |
c8bef140 | 244 | }, |
ce9c00ee | 245 | .sources = &clk_src_mpll, |
2bc02c0d KK |
246 | |
247 | /* reg_src will be added in each SoCs' clock */ | |
c8bef140 CY |
248 | }; |
249 | ||
a855039e KK |
250 | static struct clk *exynos4_clkset_moutcore_list[] = { |
251 | [0] = &exynos4_clk_mout_apll.clk, | |
252 | [1] = &exynos4_clk_mout_mpll.clk, | |
c8bef140 CY |
253 | }; |
254 | ||
a855039e KK |
255 | static struct clksrc_sources exynos4_clkset_moutcore = { |
256 | .sources = exynos4_clkset_moutcore_list, | |
257 | .nr_sources = ARRAY_SIZE(exynos4_clkset_moutcore_list), | |
c8bef140 CY |
258 | }; |
259 | ||
a855039e | 260 | static struct clksrc_clk exynos4_clk_moutcore = { |
c8bef140 CY |
261 | .clk = { |
262 | .name = "moutcore", | |
c8bef140 | 263 | }, |
a855039e KK |
264 | .sources = &exynos4_clkset_moutcore, |
265 | .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 16, .size = 1 }, | |
c8bef140 CY |
266 | }; |
267 | ||
a855039e | 268 | static struct clksrc_clk exynos4_clk_coreclk = { |
c8bef140 CY |
269 | .clk = { |
270 | .name = "core_clk", | |
a855039e | 271 | .parent = &exynos4_clk_moutcore.clk, |
c8bef140 | 272 | }, |
a855039e | 273 | .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 0, .size = 3 }, |
c8bef140 CY |
274 | }; |
275 | ||
a855039e | 276 | static struct clksrc_clk exynos4_clk_armclk = { |
c8bef140 CY |
277 | .clk = { |
278 | .name = "armclk", | |
a855039e | 279 | .parent = &exynos4_clk_coreclk.clk, |
c8bef140 CY |
280 | }, |
281 | }; | |
282 | ||
a855039e | 283 | static struct clksrc_clk exynos4_clk_aclk_corem0 = { |
c8bef140 CY |
284 | .clk = { |
285 | .name = "aclk_corem0", | |
a855039e | 286 | .parent = &exynos4_clk_coreclk.clk, |
c8bef140 | 287 | }, |
a855039e | 288 | .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 }, |
c8bef140 CY |
289 | }; |
290 | ||
a855039e | 291 | static struct clksrc_clk exynos4_clk_aclk_cores = { |
c8bef140 CY |
292 | .clk = { |
293 | .name = "aclk_cores", | |
a855039e | 294 | .parent = &exynos4_clk_coreclk.clk, |
c8bef140 | 295 | }, |
a855039e | 296 | .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 }, |
c8bef140 CY |
297 | }; |
298 | ||
a855039e | 299 | static struct clksrc_clk exynos4_clk_aclk_corem1 = { |
c8bef140 CY |
300 | .clk = { |
301 | .name = "aclk_corem1", | |
a855039e | 302 | .parent = &exynos4_clk_coreclk.clk, |
c8bef140 | 303 | }, |
a855039e | 304 | .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 8, .size = 3 }, |
c8bef140 CY |
305 | }; |
306 | ||
a855039e | 307 | static struct clksrc_clk exynos4_clk_periphclk = { |
c8bef140 CY |
308 | .clk = { |
309 | .name = "periphclk", | |
a855039e | 310 | .parent = &exynos4_clk_coreclk.clk, |
c8bef140 | 311 | }, |
a855039e | 312 | .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 }, |
c8bef140 CY |
313 | }; |
314 | ||
c8bef140 CY |
315 | /* Core list of CMU_CORE side */ |
316 | ||
a855039e KK |
317 | static struct clk *exynos4_clkset_corebus_list[] = { |
318 | [0] = &exynos4_clk_mout_mpll.clk, | |
319 | [1] = &exynos4_clk_sclk_apll.clk, | |
c8bef140 CY |
320 | }; |
321 | ||
a855039e KK |
322 | struct clksrc_sources exynos4_clkset_mout_corebus = { |
323 | .sources = exynos4_clkset_corebus_list, | |
324 | .nr_sources = ARRAY_SIZE(exynos4_clkset_corebus_list), | |
c8bef140 CY |
325 | }; |
326 | ||
a855039e | 327 | static struct clksrc_clk exynos4_clk_mout_corebus = { |
c8bef140 CY |
328 | .clk = { |
329 | .name = "mout_corebus", | |
c8bef140 | 330 | }, |
a855039e KK |
331 | .sources = &exynos4_clkset_mout_corebus, |
332 | .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 4, .size = 1 }, | |
c8bef140 CY |
333 | }; |
334 | ||
a855039e | 335 | static struct clksrc_clk exynos4_clk_sclk_dmc = { |
c8bef140 CY |
336 | .clk = { |
337 | .name = "sclk_dmc", | |
a855039e | 338 | .parent = &exynos4_clk_mout_corebus.clk, |
c8bef140 | 339 | }, |
a855039e | 340 | .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 12, .size = 3 }, |
c8bef140 CY |
341 | }; |
342 | ||
a855039e | 343 | static struct clksrc_clk exynos4_clk_aclk_cored = { |
c8bef140 CY |
344 | .clk = { |
345 | .name = "aclk_cored", | |
a855039e | 346 | .parent = &exynos4_clk_sclk_dmc.clk, |
c8bef140 | 347 | }, |
a855039e | 348 | .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 16, .size = 3 }, |
c8bef140 CY |
349 | }; |
350 | ||
a855039e | 351 | static struct clksrc_clk exynos4_clk_aclk_corep = { |
c8bef140 CY |
352 | .clk = { |
353 | .name = "aclk_corep", | |
a855039e | 354 | .parent = &exynos4_clk_aclk_cored.clk, |
c8bef140 | 355 | }, |
a855039e | 356 | .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 20, .size = 3 }, |
c8bef140 CY |
357 | }; |
358 | ||
a855039e | 359 | static struct clksrc_clk exynos4_clk_aclk_acp = { |
c8bef140 CY |
360 | .clk = { |
361 | .name = "aclk_acp", | |
a855039e | 362 | .parent = &exynos4_clk_mout_corebus.clk, |
c8bef140 | 363 | }, |
a855039e | 364 | .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 0, .size = 3 }, |
c8bef140 CY |
365 | }; |
366 | ||
a855039e | 367 | static struct clksrc_clk exynos4_clk_pclk_acp = { |
c8bef140 CY |
368 | .clk = { |
369 | .name = "pclk_acp", | |
a855039e | 370 | .parent = &exynos4_clk_aclk_acp.clk, |
c8bef140 | 371 | }, |
a855039e | 372 | .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 4, .size = 3 }, |
c8bef140 CY |
373 | }; |
374 | ||
375 | /* Core list of CMU_TOP side */ | |
376 | ||
a855039e KK |
377 | struct clk *exynos4_clkset_aclk_top_list[] = { |
378 | [0] = &exynos4_clk_mout_mpll.clk, | |
379 | [1] = &exynos4_clk_sclk_apll.clk, | |
c8bef140 CY |
380 | }; |
381 | ||
a855039e KK |
382 | static struct clksrc_sources exynos4_clkset_aclk = { |
383 | .sources = exynos4_clkset_aclk_top_list, | |
384 | .nr_sources = ARRAY_SIZE(exynos4_clkset_aclk_top_list), | |
c8bef140 CY |
385 | }; |
386 | ||
a855039e | 387 | static struct clksrc_clk exynos4_clk_aclk_200 = { |
c8bef140 CY |
388 | .clk = { |
389 | .name = "aclk_200", | |
c8bef140 | 390 | }, |
a855039e KK |
391 | .sources = &exynos4_clkset_aclk, |
392 | .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 12, .size = 1 }, | |
393 | .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 0, .size = 3 }, | |
c8bef140 CY |
394 | }; |
395 | ||
a855039e | 396 | static struct clksrc_clk exynos4_clk_aclk_100 = { |
c8bef140 CY |
397 | .clk = { |
398 | .name = "aclk_100", | |
c8bef140 | 399 | }, |
a855039e KK |
400 | .sources = &exynos4_clkset_aclk, |
401 | .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 16, .size = 1 }, | |
402 | .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 4, .size = 4 }, | |
c8bef140 CY |
403 | }; |
404 | ||
a855039e | 405 | static struct clksrc_clk exynos4_clk_aclk_160 = { |
c8bef140 CY |
406 | .clk = { |
407 | .name = "aclk_160", | |
c8bef140 | 408 | }, |
a855039e KK |
409 | .sources = &exynos4_clkset_aclk, |
410 | .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 20, .size = 1 }, | |
411 | .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 8, .size = 3 }, | |
c8bef140 CY |
412 | }; |
413 | ||
a855039e | 414 | struct clksrc_clk exynos4_clk_aclk_133 = { |
c8bef140 CY |
415 | .clk = { |
416 | .name = "aclk_133", | |
c8bef140 | 417 | }, |
a855039e KK |
418 | .sources = &exynos4_clkset_aclk, |
419 | .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 24, .size = 1 }, | |
420 | .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 12, .size = 3 }, | |
c8bef140 CY |
421 | }; |
422 | ||
a855039e | 423 | static struct clk *exynos4_clkset_vpllsrc_list[] = { |
c8bef140 | 424 | [0] = &clk_fin_vpll, |
a855039e | 425 | [1] = &exynos4_clk_sclk_hdmi27m, |
c8bef140 CY |
426 | }; |
427 | ||
a855039e KK |
428 | static struct clksrc_sources exynos4_clkset_vpllsrc = { |
429 | .sources = exynos4_clkset_vpllsrc_list, | |
430 | .nr_sources = ARRAY_SIZE(exynos4_clkset_vpllsrc_list), | |
c8bef140 CY |
431 | }; |
432 | ||
a855039e | 433 | static struct clksrc_clk exynos4_clk_vpllsrc = { |
c8bef140 CY |
434 | .clk = { |
435 | .name = "vpll_src", | |
b3ed3a17 | 436 | .enable = exynos4_clksrc_mask_top_ctrl, |
37e01729 | 437 | .ctrlbit = (1 << 0), |
c8bef140 | 438 | }, |
a855039e KK |
439 | .sources = &exynos4_clkset_vpllsrc, |
440 | .reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 0, .size = 1 }, | |
c8bef140 CY |
441 | }; |
442 | ||
a855039e KK |
443 | static struct clk *exynos4_clkset_sclk_vpll_list[] = { |
444 | [0] = &exynos4_clk_vpllsrc.clk, | |
c8bef140 CY |
445 | [1] = &clk_fout_vpll, |
446 | }; | |
447 | ||
a855039e KK |
448 | static struct clksrc_sources exynos4_clkset_sclk_vpll = { |
449 | .sources = exynos4_clkset_sclk_vpll_list, | |
450 | .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_vpll_list), | |
c8bef140 CY |
451 | }; |
452 | ||
a855039e | 453 | static struct clksrc_clk exynos4_clk_sclk_vpll = { |
c8bef140 CY |
454 | .clk = { |
455 | .name = "sclk_vpll", | |
c8bef140 | 456 | }, |
a855039e KK |
457 | .sources = &exynos4_clkset_sclk_vpll, |
458 | .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 }, | |
c8bef140 CY |
459 | }; |
460 | ||
a855039e | 461 | static struct clk exynos4_init_clocks_off[] = { |
c8bef140 CY |
462 | { |
463 | .name = "timers", | |
a855039e | 464 | .parent = &exynos4_clk_aclk_100.clk, |
b3ed3a17 | 465 | .enable = exynos4_clk_ip_peril_ctrl, |
c8bef140 | 466 | .ctrlbit = (1<<24), |
82260bf3 JL |
467 | }, { |
468 | .name = "csis", | |
badc4f2d | 469 | .devname = "s5p-mipi-csis.0", |
b3ed3a17 | 470 | .enable = exynos4_clk_ip_cam_ctrl, |
82260bf3 JL |
471 | .ctrlbit = (1 << 4), |
472 | }, { | |
473 | .name = "csis", | |
badc4f2d | 474 | .devname = "s5p-mipi-csis.1", |
b3ed3a17 | 475 | .enable = exynos4_clk_ip_cam_ctrl, |
82260bf3 | 476 | .ctrlbit = (1 << 5), |
853a0231 AB |
477 | }, { |
478 | .name = "jpeg", | |
479 | .id = 0, | |
480 | .enable = exynos4_clk_ip_cam_ctrl, | |
481 | .ctrlbit = (1 << 6), | |
82260bf3 JL |
482 | }, { |
483 | .name = "fimc", | |
badc4f2d | 484 | .devname = "exynos4-fimc.0", |
b3ed3a17 | 485 | .enable = exynos4_clk_ip_cam_ctrl, |
82260bf3 JL |
486 | .ctrlbit = (1 << 0), |
487 | }, { | |
488 | .name = "fimc", | |
badc4f2d | 489 | .devname = "exynos4-fimc.1", |
b3ed3a17 | 490 | .enable = exynos4_clk_ip_cam_ctrl, |
82260bf3 JL |
491 | .ctrlbit = (1 << 1), |
492 | }, { | |
493 | .name = "fimc", | |
badc4f2d | 494 | .devname = "exynos4-fimc.2", |
b3ed3a17 | 495 | .enable = exynos4_clk_ip_cam_ctrl, |
82260bf3 JL |
496 | .ctrlbit = (1 << 2), |
497 | }, { | |
498 | .name = "fimc", | |
badc4f2d | 499 | .devname = "exynos4-fimc.3", |
b3ed3a17 | 500 | .enable = exynos4_clk_ip_cam_ctrl, |
82260bf3 | 501 | .ctrlbit = (1 << 3), |
1f926c48 CK |
502 | }, { |
503 | .name = "tsi", | |
504 | .enable = exynos4_clk_ip_fsys_ctrl, | |
505 | .ctrlbit = (1 << 4), | |
340ea1ef JL |
506 | }, { |
507 | .name = "hsmmc", | |
8482c81c | 508 | .devname = "exynos4-sdhci.0", |
a855039e | 509 | .parent = &exynos4_clk_aclk_133.clk, |
b3ed3a17 | 510 | .enable = exynos4_clk_ip_fsys_ctrl, |
340ea1ef JL |
511 | .ctrlbit = (1 << 5), |
512 | }, { | |
513 | .name = "hsmmc", | |
8482c81c | 514 | .devname = "exynos4-sdhci.1", |
a855039e | 515 | .parent = &exynos4_clk_aclk_133.clk, |
b3ed3a17 | 516 | .enable = exynos4_clk_ip_fsys_ctrl, |
340ea1ef JL |
517 | .ctrlbit = (1 << 6), |
518 | }, { | |
519 | .name = "hsmmc", | |
8482c81c | 520 | .devname = "exynos4-sdhci.2", |
a855039e | 521 | .parent = &exynos4_clk_aclk_133.clk, |
b3ed3a17 | 522 | .enable = exynos4_clk_ip_fsys_ctrl, |
340ea1ef JL |
523 | .ctrlbit = (1 << 7), |
524 | }, { | |
525 | .name = "hsmmc", | |
8482c81c | 526 | .devname = "exynos4-sdhci.3", |
a855039e | 527 | .parent = &exynos4_clk_aclk_133.clk, |
b3ed3a17 | 528 | .enable = exynos4_clk_ip_fsys_ctrl, |
340ea1ef JL |
529 | .ctrlbit = (1 << 8), |
530 | }, { | |
454696fd | 531 | .name = "biu", |
a855039e | 532 | .parent = &exynos4_clk_aclk_133.clk, |
b3ed3a17 | 533 | .enable = exynos4_clk_ip_fsys_ctrl, |
340ea1ef | 534 | .ctrlbit = (1 << 9), |
1f926c48 CK |
535 | }, { |
536 | .name = "onenand", | |
537 | .enable = exynos4_clk_ip_fsys_ctrl, | |
538 | .ctrlbit = (1 << 15), | |
539 | }, { | |
540 | .name = "nfcon", | |
541 | .enable = exynos4_clk_ip_fsys_ctrl, | |
542 | .ctrlbit = (1 << 16), | |
3055c6da | 543 | }, { |
fbf05563 TS |
544 | .name = "dac", |
545 | .devname = "s5p-sdo", | |
546 | .enable = exynos4_clk_ip_tv_ctrl, | |
547 | .ctrlbit = (1 << 2), | |
548 | }, { | |
549 | .name = "mixer", | |
550 | .devname = "s5p-mixer", | |
551 | .enable = exynos4_clk_ip_tv_ctrl, | |
552 | .ctrlbit = (1 << 1), | |
553 | }, { | |
554 | .name = "vp", | |
555 | .devname = "s5p-mixer", | |
556 | .enable = exynos4_clk_ip_tv_ctrl, | |
557 | .ctrlbit = (1 << 0), | |
558 | }, { | |
559 | .name = "hdmi", | |
560 | .devname = "exynos4-hdmi", | |
561 | .enable = exynos4_clk_ip_tv_ctrl, | |
562 | .ctrlbit = (1 << 3), | |
563 | }, { | |
564 | .name = "hdmiphy", | |
565 | .devname = "exynos4-hdmi", | |
566 | .enable = exynos4_clk_hdmiphy_ctrl, | |
567 | .ctrlbit = (1 << 0), | |
568 | }, { | |
569 | .name = "dacphy", | |
570 | .devname = "s5p-sdo", | |
571 | .enable = exynos4_clk_dac_ctrl, | |
572 | .ctrlbit = (1 << 0), | |
82260bf3 JL |
573 | }, { |
574 | .name = "adc", | |
b3ed3a17 | 575 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 | 576 | .ctrlbit = (1 << 15), |
8d4155db ADK |
577 | }, { |
578 | .name = "tmu_apbif", | |
579 | .enable = exynos4_clk_ip_perir_ctrl, | |
580 | .ctrlbit = (1 << 17), | |
f9d7bcbc NKC |
581 | }, { |
582 | .name = "keypad", | |
f9d7bcbc NKC |
583 | .enable = exynos4_clk_ip_perir_ctrl, |
584 | .ctrlbit = (1 << 16), | |
cdff6e6f CY |
585 | }, { |
586 | .name = "rtc", | |
b3ed3a17 | 587 | .enable = exynos4_clk_ip_perir_ctrl, |
cdff6e6f | 588 | .ctrlbit = (1 << 15), |
82260bf3 JL |
589 | }, { |
590 | .name = "watchdog", | |
a855039e | 591 | .parent = &exynos4_clk_aclk_100.clk, |
b3ed3a17 | 592 | .enable = exynos4_clk_ip_perir_ctrl, |
82260bf3 JL |
593 | .ctrlbit = (1 << 14), |
594 | }, { | |
595 | .name = "usbhost", | |
b3ed3a17 | 596 | .enable = exynos4_clk_ip_fsys_ctrl , |
82260bf3 JL |
597 | .ctrlbit = (1 << 12), |
598 | }, { | |
599 | .name = "otg", | |
b3ed3a17 | 600 | .enable = exynos4_clk_ip_fsys_ctrl, |
82260bf3 JL |
601 | .ctrlbit = (1 << 13), |
602 | }, { | |
603 | .name = "spi", | |
a5238e36 | 604 | .devname = "exynos4210-spi.0", |
b3ed3a17 | 605 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 JL |
606 | .ctrlbit = (1 << 16), |
607 | }, { | |
608 | .name = "spi", | |
a5238e36 | 609 | .devname = "exynos4210-spi.1", |
b3ed3a17 | 610 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 JL |
611 | .ctrlbit = (1 << 17), |
612 | }, { | |
613 | .name = "spi", | |
a5238e36 | 614 | .devname = "exynos4210-spi.2", |
b3ed3a17 | 615 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 | 616 | .ctrlbit = (1 << 18), |
2d27043f JB |
617 | }, { |
618 | .name = "iis", | |
badc4f2d | 619 | .devname = "samsung-i2s.1", |
b3ed3a17 | 620 | .enable = exynos4_clk_ip_peril_ctrl, |
2d27043f JB |
621 | .ctrlbit = (1 << 20), |
622 | }, { | |
623 | .name = "iis", | |
badc4f2d | 624 | .devname = "samsung-i2s.2", |
b3ed3a17 | 625 | .enable = exynos4_clk_ip_peril_ctrl, |
2d27043f | 626 | .ctrlbit = (1 << 21), |
377acfbb CK |
627 | }, { |
628 | .name = "pcm", | |
629 | .devname = "samsung-pcm.1", | |
630 | .enable = exynos4_clk_ip_peril_ctrl, | |
631 | .ctrlbit = (1 << 22), | |
632 | }, { | |
633 | .name = "pcm", | |
634 | .devname = "samsung-pcm.2", | |
635 | .enable = exynos4_clk_ip_peril_ctrl, | |
636 | .ctrlbit = (1 << 23), | |
637 | }, { | |
638 | .name = "slimbus", | |
639 | .enable = exynos4_clk_ip_peril_ctrl, | |
640 | .ctrlbit = (1 << 25), | |
641 | }, { | |
642 | .name = "spdif", | |
643 | .devname = "samsung-spdif", | |
644 | .enable = exynos4_clk_ip_peril_ctrl, | |
645 | .ctrlbit = (1 << 26), | |
aa227557 JB |
646 | }, { |
647 | .name = "ac97", | |
af8a9f63 | 648 | .devname = "samsung-ac97", |
b3ed3a17 | 649 | .enable = exynos4_clk_ip_peril_ctrl, |
aa227557 | 650 | .ctrlbit = (1 << 27), |
0f75a96b KD |
651 | }, { |
652 | .name = "mfc", | |
653 | .devname = "s5p-mfc", | |
654 | .enable = exynos4_clk_ip_mfc_ctrl, | |
655 | .ctrlbit = (1 << 0), | |
82260bf3 JL |
656 | }, { |
657 | .name = "i2c", | |
badc4f2d | 658 | .devname = "s3c2440-i2c.0", |
a855039e | 659 | .parent = &exynos4_clk_aclk_100.clk, |
b3ed3a17 | 660 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 JL |
661 | .ctrlbit = (1 << 6), |
662 | }, { | |
663 | .name = "i2c", | |
badc4f2d | 664 | .devname = "s3c2440-i2c.1", |
a855039e | 665 | .parent = &exynos4_clk_aclk_100.clk, |
b3ed3a17 | 666 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 JL |
667 | .ctrlbit = (1 << 7), |
668 | }, { | |
669 | .name = "i2c", | |
badc4f2d | 670 | .devname = "s3c2440-i2c.2", |
a855039e | 671 | .parent = &exynos4_clk_aclk_100.clk, |
b3ed3a17 | 672 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 JL |
673 | .ctrlbit = (1 << 8), |
674 | }, { | |
675 | .name = "i2c", | |
badc4f2d | 676 | .devname = "s3c2440-i2c.3", |
a855039e | 677 | .parent = &exynos4_clk_aclk_100.clk, |
b3ed3a17 | 678 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 JL |
679 | .ctrlbit = (1 << 9), |
680 | }, { | |
681 | .name = "i2c", | |
badc4f2d | 682 | .devname = "s3c2440-i2c.4", |
a855039e | 683 | .parent = &exynos4_clk_aclk_100.clk, |
b3ed3a17 | 684 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 JL |
685 | .ctrlbit = (1 << 10), |
686 | }, { | |
687 | .name = "i2c", | |
badc4f2d | 688 | .devname = "s3c2440-i2c.5", |
a855039e | 689 | .parent = &exynos4_clk_aclk_100.clk, |
b3ed3a17 | 690 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 JL |
691 | .ctrlbit = (1 << 11), |
692 | }, { | |
693 | .name = "i2c", | |
badc4f2d | 694 | .devname = "s3c2440-i2c.6", |
a855039e | 695 | .parent = &exynos4_clk_aclk_100.clk, |
b3ed3a17 | 696 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 JL |
697 | .ctrlbit = (1 << 12), |
698 | }, { | |
699 | .name = "i2c", | |
badc4f2d | 700 | .devname = "s3c2440-i2c.7", |
a855039e | 701 | .parent = &exynos4_clk_aclk_100.clk, |
b3ed3a17 | 702 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 | 703 | .ctrlbit = (1 << 13), |
c40e7e0d TS |
704 | }, { |
705 | .name = "i2c", | |
706 | .devname = "s3c2440-hdmiphy-i2c", | |
a855039e | 707 | .parent = &exynos4_clk_aclk_100.clk, |
c40e7e0d TS |
708 | .enable = exynos4_clk_ip_peril_ctrl, |
709 | .ctrlbit = (1 << 14), | |
b0b6ff0b | 710 | }, { |
25e9d28d CK |
711 | .name = "sysmmu", |
712 | .devname = "exynos-sysmmu.0", | |
bca10b90 KC |
713 | .enable = exynos4_clk_ip_mfc_ctrl, |
714 | .ctrlbit = (1 << 1), | |
715 | }, { | |
25e9d28d CK |
716 | .name = "sysmmu", |
717 | .devname = "exynos-sysmmu.1", | |
bca10b90 KC |
718 | .enable = exynos4_clk_ip_mfc_ctrl, |
719 | .ctrlbit = (1 << 2), | |
720 | }, { | |
25e9d28d CK |
721 | .name = "sysmmu", |
722 | .devname = "exynos-sysmmu.2", | |
bca10b90 KC |
723 | .enable = exynos4_clk_ip_tv_ctrl, |
724 | .ctrlbit = (1 << 4), | |
725 | }, { | |
25e9d28d CK |
726 | .name = "sysmmu", |
727 | .devname = "exynos-sysmmu.3", | |
bca10b90 KC |
728 | .enable = exynos4_clk_ip_cam_ctrl, |
729 | .ctrlbit = (1 << 11), | |
730 | }, { | |
25e9d28d CK |
731 | .name = "sysmmu", |
732 | .devname = "exynos-sysmmu.4", | |
b0b6ff0b | 733 | .enable = exynos4_clk_ip_image_ctrl, |
bca10b90 | 734 | .ctrlbit = (1 << 4), |
b0b6ff0b | 735 | }, { |
25e9d28d CK |
736 | .name = "sysmmu", |
737 | .devname = "exynos-sysmmu.5", | |
b0b6ff0b KC |
738 | .enable = exynos4_clk_ip_cam_ctrl, |
739 | .ctrlbit = (1 << 7), | |
740 | }, { | |
25e9d28d CK |
741 | .name = "sysmmu", |
742 | .devname = "exynos-sysmmu.6", | |
b0b6ff0b KC |
743 | .enable = exynos4_clk_ip_cam_ctrl, |
744 | .ctrlbit = (1 << 8), | |
745 | }, { | |
25e9d28d CK |
746 | .name = "sysmmu", |
747 | .devname = "exynos-sysmmu.7", | |
b0b6ff0b KC |
748 | .enable = exynos4_clk_ip_cam_ctrl, |
749 | .ctrlbit = (1 << 9), | |
750 | }, { | |
25e9d28d CK |
751 | .name = "sysmmu", |
752 | .devname = "exynos-sysmmu.8", | |
b0b6ff0b KC |
753 | .enable = exynos4_clk_ip_cam_ctrl, |
754 | .ctrlbit = (1 << 10), | |
755 | }, { | |
25e9d28d CK |
756 | .name = "sysmmu", |
757 | .devname = "exynos-sysmmu.10", | |
b0b6ff0b KC |
758 | .enable = exynos4_clk_ip_lcd0_ctrl, |
759 | .ctrlbit = (1 << 4), | |
b0b6ff0b | 760 | } |
c8bef140 CY |
761 | }; |
762 | ||
a855039e | 763 | static struct clk exynos4_init_clocks_on[] = { |
5a847b4a JL |
764 | { |
765 | .name = "uart", | |
badc4f2d | 766 | .devname = "s5pv210-uart.0", |
b3ed3a17 | 767 | .enable = exynos4_clk_ip_peril_ctrl, |
5a847b4a JL |
768 | .ctrlbit = (1 << 0), |
769 | }, { | |
770 | .name = "uart", | |
badc4f2d | 771 | .devname = "s5pv210-uart.1", |
b3ed3a17 | 772 | .enable = exynos4_clk_ip_peril_ctrl, |
5a847b4a JL |
773 | .ctrlbit = (1 << 1), |
774 | }, { | |
775 | .name = "uart", | |
badc4f2d | 776 | .devname = "s5pv210-uart.2", |
b3ed3a17 | 777 | .enable = exynos4_clk_ip_peril_ctrl, |
5a847b4a JL |
778 | .ctrlbit = (1 << 2), |
779 | }, { | |
780 | .name = "uart", | |
badc4f2d | 781 | .devname = "s5pv210-uart.3", |
b3ed3a17 | 782 | .enable = exynos4_clk_ip_peril_ctrl, |
5a847b4a JL |
783 | .ctrlbit = (1 << 3), |
784 | }, { | |
785 | .name = "uart", | |
badc4f2d | 786 | .devname = "s5pv210-uart.4", |
b3ed3a17 | 787 | .enable = exynos4_clk_ip_peril_ctrl, |
5a847b4a JL |
788 | .ctrlbit = (1 << 4), |
789 | }, { | |
790 | .name = "uart", | |
badc4f2d | 791 | .devname = "s5pv210-uart.5", |
b3ed3a17 | 792 | .enable = exynos4_clk_ip_peril_ctrl, |
5a847b4a JL |
793 | .ctrlbit = (1 << 5), |
794 | } | |
c8bef140 CY |
795 | }; |
796 | ||
a855039e | 797 | static struct clk exynos4_clk_pdma0 = { |
66fdb29d TA |
798 | .name = "dma", |
799 | .devname = "dma-pl330.0", | |
800 | .enable = exynos4_clk_ip_fsys_ctrl, | |
801 | .ctrlbit = (1 << 0), | |
802 | }; | |
803 | ||
a855039e | 804 | static struct clk exynos4_clk_pdma1 = { |
66fdb29d TA |
805 | .name = "dma", |
806 | .devname = "dma-pl330.1", | |
807 | .enable = exynos4_clk_ip_fsys_ctrl, | |
808 | .ctrlbit = (1 << 1), | |
809 | }; | |
810 | ||
9ed76e03 BK |
811 | static struct clk exynos4_clk_mdma1 = { |
812 | .name = "dma", | |
813 | .devname = "dma-pl330.2", | |
814 | .enable = exynos4_clk_ip_image_ctrl, | |
815 | .ctrlbit = ((1 << 8) | (1 << 5) | (1 << 2)), | |
816 | }; | |
817 | ||
79025466 TB |
818 | static struct clk exynos4_clk_fimd0 = { |
819 | .name = "fimd", | |
820 | .devname = "exynos4-fb.0", | |
821 | .enable = exynos4_clk_ip_lcd0_ctrl, | |
822 | .ctrlbit = (1 << 0), | |
823 | }; | |
824 | ||
a855039e | 825 | struct clk *exynos4_clkset_group_list[] = { |
c8bef140 CY |
826 | [0] = &clk_ext_xtal_mux, |
827 | [1] = &clk_xusbxti, | |
a855039e KK |
828 | [2] = &exynos4_clk_sclk_hdmi27m, |
829 | [3] = &exynos4_clk_sclk_usbphy0, | |
830 | [4] = &exynos4_clk_sclk_usbphy1, | |
831 | [5] = &exynos4_clk_sclk_hdmiphy, | |
832 | [6] = &exynos4_clk_mout_mpll.clk, | |
833 | [7] = &exynos4_clk_mout_epll.clk, | |
834 | [8] = &exynos4_clk_sclk_vpll.clk, | |
c8bef140 CY |
835 | }; |
836 | ||
a855039e KK |
837 | struct clksrc_sources exynos4_clkset_group = { |
838 | .sources = exynos4_clkset_group_list, | |
839 | .nr_sources = ARRAY_SIZE(exynos4_clkset_group_list), | |
c8bef140 CY |
840 | }; |
841 | ||
a855039e KK |
842 | static struct clk *exynos4_clkset_mout_g2d0_list[] = { |
843 | [0] = &exynos4_clk_mout_mpll.clk, | |
844 | [1] = &exynos4_clk_sclk_apll.clk, | |
06cba8d5 JL |
845 | }; |
846 | ||
8bf56466 | 847 | struct clksrc_sources exynos4_clkset_mout_g2d0 = { |
a855039e KK |
848 | .sources = exynos4_clkset_mout_g2d0_list, |
849 | .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list), | |
06cba8d5 JL |
850 | }; |
851 | ||
a855039e KK |
852 | static struct clk *exynos4_clkset_mout_g2d1_list[] = { |
853 | [0] = &exynos4_clk_mout_epll.clk, | |
854 | [1] = &exynos4_clk_sclk_vpll.clk, | |
06cba8d5 JL |
855 | }; |
856 | ||
8bf56466 | 857 | struct clksrc_sources exynos4_clkset_mout_g2d1 = { |
a855039e KK |
858 | .sources = exynos4_clkset_mout_g2d1_list, |
859 | .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list), | |
06cba8d5 JL |
860 | }; |
861 | ||
a855039e KK |
862 | static struct clk *exynos4_clkset_mout_mfc0_list[] = { |
863 | [0] = &exynos4_clk_mout_mpll.clk, | |
864 | [1] = &exynos4_clk_sclk_apll.clk, | |
0f75a96b KD |
865 | }; |
866 | ||
a855039e KK |
867 | static struct clksrc_sources exynos4_clkset_mout_mfc0 = { |
868 | .sources = exynos4_clkset_mout_mfc0_list, | |
869 | .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc0_list), | |
0f75a96b KD |
870 | }; |
871 | ||
a855039e | 872 | static struct clksrc_clk exynos4_clk_mout_mfc0 = { |
0f75a96b KD |
873 | .clk = { |
874 | .name = "mout_mfc0", | |
875 | }, | |
a855039e KK |
876 | .sources = &exynos4_clkset_mout_mfc0, |
877 | .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 0, .size = 1 }, | |
0f75a96b KD |
878 | }; |
879 | ||
a855039e KK |
880 | static struct clk *exynos4_clkset_mout_mfc1_list[] = { |
881 | [0] = &exynos4_clk_mout_epll.clk, | |
882 | [1] = &exynos4_clk_sclk_vpll.clk, | |
0f75a96b KD |
883 | }; |
884 | ||
a855039e KK |
885 | static struct clksrc_sources exynos4_clkset_mout_mfc1 = { |
886 | .sources = exynos4_clkset_mout_mfc1_list, | |
887 | .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc1_list), | |
0f75a96b KD |
888 | }; |
889 | ||
a855039e | 890 | static struct clksrc_clk exynos4_clk_mout_mfc1 = { |
0f75a96b KD |
891 | .clk = { |
892 | .name = "mout_mfc1", | |
893 | }, | |
a855039e KK |
894 | .sources = &exynos4_clkset_mout_mfc1, |
895 | .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 4, .size = 1 }, | |
0f75a96b KD |
896 | }; |
897 | ||
a855039e KK |
898 | static struct clk *exynos4_clkset_mout_mfc_list[] = { |
899 | [0] = &exynos4_clk_mout_mfc0.clk, | |
900 | [1] = &exynos4_clk_mout_mfc1.clk, | |
0f75a96b KD |
901 | }; |
902 | ||
a855039e KK |
903 | static struct clksrc_sources exynos4_clkset_mout_mfc = { |
904 | .sources = exynos4_clkset_mout_mfc_list, | |
905 | .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc_list), | |
0f75a96b KD |
906 | }; |
907 | ||
a855039e KK |
908 | static struct clk *exynos4_clkset_sclk_dac_list[] = { |
909 | [0] = &exynos4_clk_sclk_vpll.clk, | |
910 | [1] = &exynos4_clk_sclk_hdmiphy, | |
fbf05563 TS |
911 | }; |
912 | ||
a855039e KK |
913 | static struct clksrc_sources exynos4_clkset_sclk_dac = { |
914 | .sources = exynos4_clkset_sclk_dac_list, | |
915 | .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_dac_list), | |
fbf05563 TS |
916 | }; |
917 | ||
a855039e | 918 | static struct clksrc_clk exynos4_clk_sclk_dac = { |
fbf05563 TS |
919 | .clk = { |
920 | .name = "sclk_dac", | |
921 | .enable = exynos4_clksrc_mask_tv_ctrl, | |
922 | .ctrlbit = (1 << 8), | |
923 | }, | |
a855039e KK |
924 | .sources = &exynos4_clkset_sclk_dac, |
925 | .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 8, .size = 1 }, | |
fbf05563 TS |
926 | }; |
927 | ||
a855039e | 928 | static struct clksrc_clk exynos4_clk_sclk_pixel = { |
fbf05563 TS |
929 | .clk = { |
930 | .name = "sclk_pixel", | |
a855039e | 931 | .parent = &exynos4_clk_sclk_vpll.clk, |
fbf05563 | 932 | }, |
a855039e | 933 | .reg_div = { .reg = EXYNOS4_CLKDIV_TV, .shift = 0, .size = 4 }, |
fbf05563 TS |
934 | }; |
935 | ||
a855039e KK |
936 | static struct clk *exynos4_clkset_sclk_hdmi_list[] = { |
937 | [0] = &exynos4_clk_sclk_pixel.clk, | |
938 | [1] = &exynos4_clk_sclk_hdmiphy, | |
fbf05563 TS |
939 | }; |
940 | ||
a855039e KK |
941 | static struct clksrc_sources exynos4_clkset_sclk_hdmi = { |
942 | .sources = exynos4_clkset_sclk_hdmi_list, | |
943 | .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list), | |
fbf05563 TS |
944 | }; |
945 | ||
a855039e | 946 | static struct clksrc_clk exynos4_clk_sclk_hdmi = { |
fbf05563 TS |
947 | .clk = { |
948 | .name = "sclk_hdmi", | |
949 | .enable = exynos4_clksrc_mask_tv_ctrl, | |
950 | .ctrlbit = (1 << 0), | |
951 | }, | |
a855039e KK |
952 | .sources = &exynos4_clkset_sclk_hdmi, |
953 | .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 0, .size = 1 }, | |
fbf05563 TS |
954 | }; |
955 | ||
a855039e KK |
956 | static struct clk *exynos4_clkset_sclk_mixer_list[] = { |
957 | [0] = &exynos4_clk_sclk_dac.clk, | |
958 | [1] = &exynos4_clk_sclk_hdmi.clk, | |
fbf05563 TS |
959 | }; |
960 | ||
a855039e KK |
961 | static struct clksrc_sources exynos4_clkset_sclk_mixer = { |
962 | .sources = exynos4_clkset_sclk_mixer_list, | |
963 | .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_mixer_list), | |
fbf05563 TS |
964 | }; |
965 | ||
a855039e | 966 | static struct clksrc_clk exynos4_clk_sclk_mixer = { |
ce9c00ee | 967 | .clk = { |
fbf05563 TS |
968 | .name = "sclk_mixer", |
969 | .enable = exynos4_clksrc_mask_tv_ctrl, | |
970 | .ctrlbit = (1 << 4), | |
971 | }, | |
a855039e KK |
972 | .sources = &exynos4_clkset_sclk_mixer, |
973 | .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 4, .size = 1 }, | |
fbf05563 TS |
974 | }; |
975 | ||
a855039e KK |
976 | static struct clksrc_clk *exynos4_sclk_tv[] = { |
977 | &exynos4_clk_sclk_dac, | |
978 | &exynos4_clk_sclk_pixel, | |
979 | &exynos4_clk_sclk_hdmi, | |
980 | &exynos4_clk_sclk_mixer, | |
fbf05563 TS |
981 | }; |
982 | ||
a855039e | 983 | static struct clksrc_clk exynos4_clk_dout_mmc0 = { |
ce9c00ee | 984 | .clk = { |
340ea1ef | 985 | .name = "dout_mmc0", |
340ea1ef | 986 | }, |
a855039e KK |
987 | .sources = &exynos4_clkset_group, |
988 | .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 0, .size = 4 }, | |
989 | .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 0, .size = 4 }, | |
340ea1ef JL |
990 | }; |
991 | ||
a855039e | 992 | static struct clksrc_clk exynos4_clk_dout_mmc1 = { |
ce9c00ee | 993 | .clk = { |
340ea1ef | 994 | .name = "dout_mmc1", |
340ea1ef | 995 | }, |
a855039e KK |
996 | .sources = &exynos4_clkset_group, |
997 | .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 4, .size = 4 }, | |
998 | .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 16, .size = 4 }, | |
340ea1ef JL |
999 | }; |
1000 | ||
a855039e | 1001 | static struct clksrc_clk exynos4_clk_dout_mmc2 = { |
ce9c00ee | 1002 | .clk = { |
340ea1ef | 1003 | .name = "dout_mmc2", |
340ea1ef | 1004 | }, |
a855039e KK |
1005 | .sources = &exynos4_clkset_group, |
1006 | .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 8, .size = 4 }, | |
1007 | .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 0, .size = 4 }, | |
340ea1ef JL |
1008 | }; |
1009 | ||
a855039e | 1010 | static struct clksrc_clk exynos4_clk_dout_mmc3 = { |
ce9c00ee | 1011 | .clk = { |
340ea1ef | 1012 | .name = "dout_mmc3", |
340ea1ef | 1013 | }, |
a855039e KK |
1014 | .sources = &exynos4_clkset_group, |
1015 | .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 12, .size = 4 }, | |
1016 | .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 16, .size = 4 }, | |
340ea1ef JL |
1017 | }; |
1018 | ||
a855039e | 1019 | static struct clksrc_clk exynos4_clk_dout_mmc4 = { |
340ea1ef JL |
1020 | .clk = { |
1021 | .name = "dout_mmc4", | |
340ea1ef | 1022 | }, |
a855039e KK |
1023 | .sources = &exynos4_clkset_group, |
1024 | .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 16, .size = 4 }, | |
1025 | .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 0, .size = 4 }, | |
340ea1ef JL |
1026 | }; |
1027 | ||
a855039e | 1028 | static struct clksrc_clk exynos4_clksrcs[] = { |
c8bef140 | 1029 | { |
ce9c00ee | 1030 | .clk = { |
c8bef140 | 1031 | .name = "sclk_pwm", |
b3ed3a17 | 1032 | .enable = exynos4_clksrc_mask_peril0_ctrl, |
c8bef140 CY |
1033 | .ctrlbit = (1 << 24), |
1034 | }, | |
a855039e KK |
1035 | .sources = &exynos4_clkset_group, |
1036 | .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 24, .size = 4 }, | |
1037 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL3, .shift = 0, .size = 4 }, | |
33f469d2 | 1038 | }, { |
ce9c00ee | 1039 | .clk = { |
33f469d2 | 1040 | .name = "sclk_csis", |
badc4f2d | 1041 | .devname = "s5p-mipi-csis.0", |
b3ed3a17 | 1042 | .enable = exynos4_clksrc_mask_cam_ctrl, |
33f469d2 JL |
1043 | .ctrlbit = (1 << 24), |
1044 | }, | |
a855039e KK |
1045 | .sources = &exynos4_clkset_group, |
1046 | .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 24, .size = 4 }, | |
1047 | .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 24, .size = 4 }, | |
33f469d2 | 1048 | }, { |
ce9c00ee | 1049 | .clk = { |
33f469d2 | 1050 | .name = "sclk_csis", |
badc4f2d | 1051 | .devname = "s5p-mipi-csis.1", |
b3ed3a17 | 1052 | .enable = exynos4_clksrc_mask_cam_ctrl, |
33f469d2 JL |
1053 | .ctrlbit = (1 << 28), |
1054 | }, | |
a855039e KK |
1055 | .sources = &exynos4_clkset_group, |
1056 | .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 28, .size = 4 }, | |
1057 | .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 28, .size = 4 }, | |
33f469d2 | 1058 | }, { |
ce9c00ee | 1059 | .clk = { |
00aaad22 | 1060 | .name = "sclk_cam0", |
b3ed3a17 | 1061 | .enable = exynos4_clksrc_mask_cam_ctrl, |
33f469d2 JL |
1062 | .ctrlbit = (1 << 16), |
1063 | }, | |
a855039e KK |
1064 | .sources = &exynos4_clkset_group, |
1065 | .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 16, .size = 4 }, | |
1066 | .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 16, .size = 4 }, | |
33f469d2 | 1067 | }, { |
ce9c00ee | 1068 | .clk = { |
00aaad22 | 1069 | .name = "sclk_cam1", |
b3ed3a17 | 1070 | .enable = exynos4_clksrc_mask_cam_ctrl, |
33f469d2 JL |
1071 | .ctrlbit = (1 << 20), |
1072 | }, | |
a855039e KK |
1073 | .sources = &exynos4_clkset_group, |
1074 | .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 20, .size = 4 }, | |
1075 | .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 20, .size = 4 }, | |
33f469d2 | 1076 | }, { |
ce9c00ee | 1077 | .clk = { |
33f469d2 | 1078 | .name = "sclk_fimc", |
badc4f2d | 1079 | .devname = "exynos4-fimc.0", |
b3ed3a17 | 1080 | .enable = exynos4_clksrc_mask_cam_ctrl, |
33f469d2 JL |
1081 | .ctrlbit = (1 << 0), |
1082 | }, | |
a855039e KK |
1083 | .sources = &exynos4_clkset_group, |
1084 | .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 0, .size = 4 }, | |
1085 | .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 0, .size = 4 }, | |
33f469d2 | 1086 | }, { |
ce9c00ee | 1087 | .clk = { |
33f469d2 | 1088 | .name = "sclk_fimc", |
badc4f2d | 1089 | .devname = "exynos4-fimc.1", |
b3ed3a17 | 1090 | .enable = exynos4_clksrc_mask_cam_ctrl, |
33f469d2 JL |
1091 | .ctrlbit = (1 << 4), |
1092 | }, | |
a855039e KK |
1093 | .sources = &exynos4_clkset_group, |
1094 | .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 4, .size = 4 }, | |
1095 | .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 4, .size = 4 }, | |
33f469d2 | 1096 | }, { |
ce9c00ee | 1097 | .clk = { |
33f469d2 | 1098 | .name = "sclk_fimc", |
badc4f2d | 1099 | .devname = "exynos4-fimc.2", |
b3ed3a17 | 1100 | .enable = exynos4_clksrc_mask_cam_ctrl, |
33f469d2 JL |
1101 | .ctrlbit = (1 << 8), |
1102 | }, | |
a855039e KK |
1103 | .sources = &exynos4_clkset_group, |
1104 | .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 8, .size = 4 }, | |
1105 | .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 8, .size = 4 }, | |
33f469d2 | 1106 | }, { |
ce9c00ee | 1107 | .clk = { |
33f469d2 | 1108 | .name = "sclk_fimc", |
badc4f2d | 1109 | .devname = "exynos4-fimc.3", |
b3ed3a17 | 1110 | .enable = exynos4_clksrc_mask_cam_ctrl, |
33f469d2 JL |
1111 | .ctrlbit = (1 << 12), |
1112 | }, | |
a855039e KK |
1113 | .sources = &exynos4_clkset_group, |
1114 | .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 12, .size = 4 }, | |
1115 | .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 12, .size = 4 }, | |
33f469d2 | 1116 | }, { |
ce9c00ee | 1117 | .clk = { |
33f469d2 | 1118 | .name = "sclk_fimd", |
268a7ef2 | 1119 | .devname = "exynos4-fb.0", |
b3ed3a17 | 1120 | .enable = exynos4_clksrc_mask_lcd0_ctrl, |
33f469d2 JL |
1121 | .ctrlbit = (1 << 0), |
1122 | }, | |
a855039e KK |
1123 | .sources = &exynos4_clkset_group, |
1124 | .reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 }, | |
1125 | .reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 }, | |
0f75a96b | 1126 | }, { |
ce9c00ee | 1127 | .clk = { |
0f75a96b KD |
1128 | .name = "sclk_mfc", |
1129 | .devname = "s5p-mfc", | |
1130 | }, | |
a855039e KK |
1131 | .sources = &exynos4_clkset_mout_mfc, |
1132 | .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 }, | |
1133 | .reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 }, | |
340ea1ef | 1134 | }, { |
ce9c00ee | 1135 | .clk = { |
454696fd | 1136 | .name = "ciu", |
a855039e | 1137 | .parent = &exynos4_clk_dout_mmc4.clk, |
b3ed3a17 | 1138 | .enable = exynos4_clksrc_mask_fsys_ctrl, |
340ea1ef JL |
1139 | .ctrlbit = (1 << 16), |
1140 | }, | |
a855039e | 1141 | .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 }, |
340ea1ef | 1142 | } |
c8bef140 CY |
1143 | }; |
1144 | ||
a855039e | 1145 | static struct clksrc_clk exynos4_clk_sclk_uart0 = { |
0cfb26e1 TA |
1146 | .clk = { |
1147 | .name = "uclk1", | |
1148 | .devname = "exynos4210-uart.0", | |
1149 | .enable = exynos4_clksrc_mask_peril0_ctrl, | |
1150 | .ctrlbit = (1 << 0), | |
1151 | }, | |
a855039e KK |
1152 | .sources = &exynos4_clkset_group, |
1153 | .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 0, .size = 4 }, | |
1154 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 0, .size = 4 }, | |
0cfb26e1 TA |
1155 | }; |
1156 | ||
a855039e | 1157 | static struct clksrc_clk exynos4_clk_sclk_uart1 = { |
ce9c00ee | 1158 | .clk = { |
0cfb26e1 TA |
1159 | .name = "uclk1", |
1160 | .devname = "exynos4210-uart.1", | |
1161 | .enable = exynos4_clksrc_mask_peril0_ctrl, | |
1162 | .ctrlbit = (1 << 4), | |
1163 | }, | |
a855039e KK |
1164 | .sources = &exynos4_clkset_group, |
1165 | .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 4, .size = 4 }, | |
1166 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 4, .size = 4 }, | |
0cfb26e1 TA |
1167 | }; |
1168 | ||
a855039e | 1169 | static struct clksrc_clk exynos4_clk_sclk_uart2 = { |
ce9c00ee | 1170 | .clk = { |
0cfb26e1 TA |
1171 | .name = "uclk1", |
1172 | .devname = "exynos4210-uart.2", | |
1173 | .enable = exynos4_clksrc_mask_peril0_ctrl, | |
1174 | .ctrlbit = (1 << 8), | |
1175 | }, | |
a855039e KK |
1176 | .sources = &exynos4_clkset_group, |
1177 | .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 8, .size = 4 }, | |
1178 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 8, .size = 4 }, | |
0cfb26e1 TA |
1179 | }; |
1180 | ||
a855039e | 1181 | static struct clksrc_clk exynos4_clk_sclk_uart3 = { |
ce9c00ee | 1182 | .clk = { |
0cfb26e1 TA |
1183 | .name = "uclk1", |
1184 | .devname = "exynos4210-uart.3", | |
1185 | .enable = exynos4_clksrc_mask_peril0_ctrl, | |
1186 | .ctrlbit = (1 << 12), | |
1187 | }, | |
a855039e KK |
1188 | .sources = &exynos4_clkset_group, |
1189 | .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 12, .size = 4 }, | |
1190 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 12, .size = 4 }, | |
0cfb26e1 TA |
1191 | }; |
1192 | ||
a855039e | 1193 | static struct clksrc_clk exynos4_clk_sclk_mmc0 = { |
ce9c00ee | 1194 | .clk = { |
a361d10a | 1195 | .name = "sclk_mmc", |
8482c81c | 1196 | .devname = "exynos4-sdhci.0", |
a855039e | 1197 | .parent = &exynos4_clk_dout_mmc0.clk, |
a361d10a RS |
1198 | .enable = exynos4_clksrc_mask_fsys_ctrl, |
1199 | .ctrlbit = (1 << 0), | |
1200 | }, | |
a855039e | 1201 | .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 8, .size = 8 }, |
a361d10a RS |
1202 | }; |
1203 | ||
a855039e | 1204 | static struct clksrc_clk exynos4_clk_sclk_mmc1 = { |
ce9c00ee | 1205 | .clk = { |
a361d10a | 1206 | .name = "sclk_mmc", |
8482c81c | 1207 | .devname = "exynos4-sdhci.1", |
a855039e | 1208 | .parent = &exynos4_clk_dout_mmc1.clk, |
a361d10a RS |
1209 | .enable = exynos4_clksrc_mask_fsys_ctrl, |
1210 | .ctrlbit = (1 << 4), | |
1211 | }, | |
a855039e | 1212 | .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 24, .size = 8 }, |
a361d10a RS |
1213 | }; |
1214 | ||
a855039e | 1215 | static struct clksrc_clk exynos4_clk_sclk_mmc2 = { |
ce9c00ee | 1216 | .clk = { |
a361d10a | 1217 | .name = "sclk_mmc", |
8482c81c | 1218 | .devname = "exynos4-sdhci.2", |
a855039e | 1219 | .parent = &exynos4_clk_dout_mmc2.clk, |
a361d10a RS |
1220 | .enable = exynos4_clksrc_mask_fsys_ctrl, |
1221 | .ctrlbit = (1 << 8), | |
1222 | }, | |
a855039e | 1223 | .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 8, .size = 8 }, |
a361d10a RS |
1224 | }; |
1225 | ||
a855039e | 1226 | static struct clksrc_clk exynos4_clk_sclk_mmc3 = { |
ce9c00ee | 1227 | .clk = { |
a361d10a | 1228 | .name = "sclk_mmc", |
8482c81c | 1229 | .devname = "exynos4-sdhci.3", |
a855039e | 1230 | .parent = &exynos4_clk_dout_mmc3.clk, |
a361d10a RS |
1231 | .enable = exynos4_clksrc_mask_fsys_ctrl, |
1232 | .ctrlbit = (1 << 12), | |
1233 | }, | |
a855039e | 1234 | .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 }, |
a361d10a RS |
1235 | }; |
1236 | ||
46fda15c TA |
1237 | static struct clksrc_clk exynos4_clk_mdout_spi0 = { |
1238 | .clk = { | |
1239 | .name = "mdout_spi", | |
1240 | .devname = "exynos4210-spi.0", | |
1241 | }, | |
1242 | .sources = &exynos4_clkset_group, | |
1243 | .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 }, | |
1244 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 }, | |
1245 | }; | |
1246 | ||
1247 | static struct clksrc_clk exynos4_clk_mdout_spi1 = { | |
1248 | .clk = { | |
1249 | .name = "mdout_spi", | |
1250 | .devname = "exynos4210-spi.1", | |
1251 | }, | |
1252 | .sources = &exynos4_clkset_group, | |
1253 | .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 }, | |
1254 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 }, | |
1255 | }; | |
1256 | ||
1257 | static struct clksrc_clk exynos4_clk_mdout_spi2 = { | |
1258 | .clk = { | |
1259 | .name = "mdout_spi", | |
1260 | .devname = "exynos4210-spi.2", | |
1261 | }, | |
1262 | .sources = &exynos4_clkset_group, | |
1263 | .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 }, | |
1264 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 }, | |
1265 | }; | |
1266 | ||
a855039e | 1267 | static struct clksrc_clk exynos4_clk_sclk_spi0 = { |
ce9c00ee | 1268 | .clk = { |
74ac23a3 | 1269 | .name = "sclk_spi", |
a5238e36 | 1270 | .devname = "exynos4210-spi.0", |
46fda15c | 1271 | .parent = &exynos4_clk_mdout_spi0.clk, |
74ac23a3 | 1272 | .enable = exynos4_clksrc_mask_peril1_ctrl, |
ce9c00ee | 1273 | .ctrlbit = (1 << 16), |
74ac23a3 | 1274 | }, |
46fda15c | 1275 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 8, .size = 8 }, |
74ac23a3 PV |
1276 | }; |
1277 | ||
a855039e | 1278 | static struct clksrc_clk exynos4_clk_sclk_spi1 = { |
ce9c00ee | 1279 | .clk = { |
74ac23a3 | 1280 | .name = "sclk_spi", |
a5238e36 | 1281 | .devname = "exynos4210-spi.1", |
46fda15c | 1282 | .parent = &exynos4_clk_mdout_spi1.clk, |
74ac23a3 | 1283 | .enable = exynos4_clksrc_mask_peril1_ctrl, |
ce9c00ee | 1284 | .ctrlbit = (1 << 20), |
74ac23a3 | 1285 | }, |
46fda15c | 1286 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 24, .size = 8 }, |
74ac23a3 PV |
1287 | }; |
1288 | ||
a855039e | 1289 | static struct clksrc_clk exynos4_clk_sclk_spi2 = { |
ce9c00ee | 1290 | .clk = { |
74ac23a3 | 1291 | .name = "sclk_spi", |
a5238e36 | 1292 | .devname = "exynos4210-spi.2", |
46fda15c | 1293 | .parent = &exynos4_clk_mdout_spi2.clk, |
74ac23a3 | 1294 | .enable = exynos4_clksrc_mask_peril1_ctrl, |
ce9c00ee | 1295 | .ctrlbit = (1 << 24), |
74ac23a3 | 1296 | }, |
46fda15c | 1297 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 8, .size = 8 }, |
74ac23a3 PV |
1298 | }; |
1299 | ||
c8bef140 | 1300 | /* Clock initialization code */ |
a855039e KK |
1301 | static struct clksrc_clk *exynos4_sysclks[] = { |
1302 | &exynos4_clk_mout_apll, | |
1303 | &exynos4_clk_sclk_apll, | |
1304 | &exynos4_clk_mout_epll, | |
1305 | &exynos4_clk_mout_mpll, | |
1306 | &exynos4_clk_moutcore, | |
1307 | &exynos4_clk_coreclk, | |
1308 | &exynos4_clk_armclk, | |
1309 | &exynos4_clk_aclk_corem0, | |
1310 | &exynos4_clk_aclk_cores, | |
1311 | &exynos4_clk_aclk_corem1, | |
1312 | &exynos4_clk_periphclk, | |
1313 | &exynos4_clk_mout_corebus, | |
1314 | &exynos4_clk_sclk_dmc, | |
1315 | &exynos4_clk_aclk_cored, | |
1316 | &exynos4_clk_aclk_corep, | |
1317 | &exynos4_clk_aclk_acp, | |
1318 | &exynos4_clk_pclk_acp, | |
1319 | &exynos4_clk_vpllsrc, | |
1320 | &exynos4_clk_sclk_vpll, | |
1321 | &exynos4_clk_aclk_200, | |
1322 | &exynos4_clk_aclk_100, | |
1323 | &exynos4_clk_aclk_160, | |
1324 | &exynos4_clk_aclk_133, | |
1325 | &exynos4_clk_dout_mmc0, | |
1326 | &exynos4_clk_dout_mmc1, | |
1327 | &exynos4_clk_dout_mmc2, | |
1328 | &exynos4_clk_dout_mmc3, | |
1329 | &exynos4_clk_dout_mmc4, | |
1330 | &exynos4_clk_mout_mfc0, | |
1331 | &exynos4_clk_mout_mfc1, | |
1332 | }; | |
1333 | ||
1334 | static struct clk *exynos4_clk_cdev[] = { | |
1335 | &exynos4_clk_pdma0, | |
1336 | &exynos4_clk_pdma1, | |
9ed76e03 | 1337 | &exynos4_clk_mdma1, |
79025466 | 1338 | &exynos4_clk_fimd0, |
a855039e KK |
1339 | }; |
1340 | ||
1341 | static struct clksrc_clk *exynos4_clksrc_cdev[] = { | |
1342 | &exynos4_clk_sclk_uart0, | |
1343 | &exynos4_clk_sclk_uart1, | |
1344 | &exynos4_clk_sclk_uart2, | |
1345 | &exynos4_clk_sclk_uart3, | |
1346 | &exynos4_clk_sclk_mmc0, | |
1347 | &exynos4_clk_sclk_mmc1, | |
1348 | &exynos4_clk_sclk_mmc2, | |
1349 | &exynos4_clk_sclk_mmc3, | |
1350 | &exynos4_clk_sclk_spi0, | |
1351 | &exynos4_clk_sclk_spi1, | |
1352 | &exynos4_clk_sclk_spi2, | |
46fda15c TA |
1353 | &exynos4_clk_mdout_spi0, |
1354 | &exynos4_clk_mdout_spi1, | |
1355 | &exynos4_clk_mdout_spi2, | |
0cfb26e1 TA |
1356 | }; |
1357 | ||
1358 | static struct clk_lookup exynos4_clk_lookup[] = { | |
a855039e KK |
1359 | CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos4_clk_sclk_uart0.clk), |
1360 | CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk), | |
1361 | CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk), | |
1362 | CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk), | |
8482c81c TA |
1363 | CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk), |
1364 | CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk), | |
1365 | CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk), | |
1366 | CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk), | |
79025466 | 1367 | CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0), |
a855039e KK |
1368 | CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0), |
1369 | CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1), | |
8f7b1321 | 1370 | CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1), |
a5238e36 TA |
1371 | CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk), |
1372 | CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk), | |
1373 | CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk), | |
0cfb26e1 TA |
1374 | }; |
1375 | ||
877d1b57 JL |
1376 | static int xtal_rate; |
1377 | ||
b3ed3a17 | 1378 | static unsigned long exynos4_fout_apll_get_rate(struct clk *clk) |
877d1b57 | 1379 | { |
2bc02c0d | 1380 | if (soc_is_exynos4210()) |
a855039e | 1381 | return s5p_get_pll45xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0), |
2bc02c0d | 1382 | pll_4508); |
b88b1cc7 | 1383 | else if (soc_is_exynos4212() || soc_is_exynos4412()) |
a855039e | 1384 | return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0)); |
2bc02c0d KK |
1385 | else |
1386 | return 0; | |
877d1b57 JL |
1387 | } |
1388 | ||
b3ed3a17 KK |
1389 | static struct clk_ops exynos4_fout_apll_ops = { |
1390 | .get_rate = exynos4_fout_apll_get_rate, | |
877d1b57 JL |
1391 | }; |
1392 | ||
a855039e | 1393 | static u32 exynos4_vpll_div[][8] = { |
fbf05563 TS |
1394 | { 54000000, 3, 53, 3, 1024, 0, 17, 0 }, |
1395 | { 108000000, 3, 53, 2, 1024, 0, 17, 0 }, | |
1396 | }; | |
1397 | ||
1398 | static unsigned long exynos4_vpll_get_rate(struct clk *clk) | |
1399 | { | |
1400 | return clk->rate; | |
1401 | } | |
1402 | ||
1403 | static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate) | |
1404 | { | |
1405 | unsigned int vpll_con0, vpll_con1 = 0; | |
1406 | unsigned int i; | |
1407 | ||
1408 | /* Return if nothing changed */ | |
1409 | if (clk->rate == rate) | |
1410 | return 0; | |
1411 | ||
a855039e | 1412 | vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0); |
fbf05563 TS |
1413 | vpll_con0 &= ~(0x1 << 27 | \ |
1414 | PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \ | |
1415 | PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \ | |
1416 | PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT); | |
1417 | ||
a855039e | 1418 | vpll_con1 = __raw_readl(EXYNOS4_VPLL_CON1); |
fbf05563 TS |
1419 | vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT | \ |
1420 | PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \ | |
1421 | PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT); | |
1422 | ||
a855039e KK |
1423 | for (i = 0; i < ARRAY_SIZE(exynos4_vpll_div); i++) { |
1424 | if (exynos4_vpll_div[i][0] == rate) { | |
1425 | vpll_con0 |= exynos4_vpll_div[i][1] << PLL46XX_PDIV_SHIFT; | |
1426 | vpll_con0 |= exynos4_vpll_div[i][2] << PLL46XX_MDIV_SHIFT; | |
1427 | vpll_con0 |= exynos4_vpll_div[i][3] << PLL46XX_SDIV_SHIFT; | |
1428 | vpll_con1 |= exynos4_vpll_div[i][4] << PLL46XX_KDIV_SHIFT; | |
1429 | vpll_con1 |= exynos4_vpll_div[i][5] << PLL46XX_MFR_SHIFT; | |
1430 | vpll_con1 |= exynos4_vpll_div[i][6] << PLL46XX_MRR_SHIFT; | |
1431 | vpll_con0 |= exynos4_vpll_div[i][7] << 27; | |
fbf05563 TS |
1432 | break; |
1433 | } | |
1434 | } | |
1435 | ||
a855039e | 1436 | if (i == ARRAY_SIZE(exynos4_vpll_div)) { |
fbf05563 TS |
1437 | printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n", |
1438 | __func__); | |
1439 | return -EINVAL; | |
1440 | } | |
1441 | ||
a855039e KK |
1442 | __raw_writel(vpll_con0, EXYNOS4_VPLL_CON0); |
1443 | __raw_writel(vpll_con1, EXYNOS4_VPLL_CON1); | |
fbf05563 TS |
1444 | |
1445 | /* Wait for VPLL lock */ | |
a855039e | 1446 | while (!(__raw_readl(EXYNOS4_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT))) |
fbf05563 TS |
1447 | continue; |
1448 | ||
1449 | clk->rate = rate; | |
1450 | return 0; | |
1451 | } | |
1452 | ||
1453 | static struct clk_ops exynos4_vpll_ops = { | |
1454 | .get_rate = exynos4_vpll_get_rate, | |
1455 | .set_rate = exynos4_vpll_set_rate, | |
1456 | }; | |
1457 | ||
b3ed3a17 | 1458 | void __init_or_cpufreq exynos4_setup_clocks(void) |
c8bef140 CY |
1459 | { |
1460 | struct clk *xtal_clk; | |
2bc02c0d KK |
1461 | unsigned long apll = 0; |
1462 | unsigned long mpll = 0; | |
1463 | unsigned long epll = 0; | |
1464 | unsigned long vpll = 0; | |
c8bef140 CY |
1465 | unsigned long vpllsrc; |
1466 | unsigned long xtal; | |
1467 | unsigned long armclk; | |
c8bef140 | 1468 | unsigned long sclk_dmc; |
228ef987 JL |
1469 | unsigned long aclk_200; |
1470 | unsigned long aclk_100; | |
1471 | unsigned long aclk_160; | |
1472 | unsigned long aclk_133; | |
c8bef140 CY |
1473 | unsigned int ptr; |
1474 | ||
1475 | printk(KERN_DEBUG "%s: registering clocks\n", __func__); | |
1476 | ||
1477 | xtal_clk = clk_get(NULL, "xtal"); | |
1478 | BUG_ON(IS_ERR(xtal_clk)); | |
1479 | ||
1480 | xtal = clk_get_rate(xtal_clk); | |
877d1b57 JL |
1481 | |
1482 | xtal_rate = xtal; | |
1483 | ||
c8bef140 CY |
1484 | clk_put(xtal_clk); |
1485 | ||
1486 | printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); | |
1487 | ||
2bc02c0d | 1488 | if (soc_is_exynos4210()) { |
a855039e | 1489 | apll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_APLL_CON0), |
2bc02c0d | 1490 | pll_4508); |
a855039e | 1491 | mpll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0), |
2bc02c0d | 1492 | pll_4508); |
a855039e KK |
1493 | epll = s5p_get_pll46xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0), |
1494 | __raw_readl(EXYNOS4_EPLL_CON1), pll_4600); | |
2bc02c0d | 1495 | |
a855039e KK |
1496 | vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk); |
1497 | vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0), | |
1498 | __raw_readl(EXYNOS4_VPLL_CON1), pll_4650c); | |
b88b1cc7 | 1499 | } else if (soc_is_exynos4212() || soc_is_exynos4412()) { |
a855039e KK |
1500 | apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_APLL_CON0)); |
1501 | mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0)); | |
1502 | epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0), | |
1503 | __raw_readl(EXYNOS4_EPLL_CON1)); | |
1504 | ||
1505 | vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk); | |
1506 | vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0), | |
1507 | __raw_readl(EXYNOS4_VPLL_CON1)); | |
2bc02c0d KK |
1508 | } else { |
1509 | /* nothing */ | |
1510 | } | |
c8bef140 | 1511 | |
b3ed3a17 | 1512 | clk_fout_apll.ops = &exynos4_fout_apll_ops; |
c8bef140 CY |
1513 | clk_fout_mpll.rate = mpll; |
1514 | clk_fout_epll.rate = epll; | |
fbf05563 | 1515 | clk_fout_vpll.ops = &exynos4_vpll_ops; |
c8bef140 CY |
1516 | clk_fout_vpll.rate = vpll; |
1517 | ||
b3ed3a17 | 1518 | printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld", |
c8bef140 CY |
1519 | apll, mpll, epll, vpll); |
1520 | ||
a855039e KK |
1521 | armclk = clk_get_rate(&exynos4_clk_armclk.clk); |
1522 | sclk_dmc = clk_get_rate(&exynos4_clk_sclk_dmc.clk); | |
a6aa7a55 | 1523 | |
a855039e KK |
1524 | aclk_200 = clk_get_rate(&exynos4_clk_aclk_200.clk); |
1525 | aclk_100 = clk_get_rate(&exynos4_clk_aclk_100.clk); | |
1526 | aclk_160 = clk_get_rate(&exynos4_clk_aclk_160.clk); | |
1527 | aclk_133 = clk_get_rate(&exynos4_clk_aclk_133.clk); | |
228ef987 | 1528 | |
b3ed3a17 | 1529 | printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n" |
228ef987 JL |
1530 | "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n", |
1531 | armclk, sclk_dmc, aclk_200, | |
1532 | aclk_100, aclk_160, aclk_133); | |
c8bef140 CY |
1533 | |
1534 | clk_f.rate = armclk; | |
1535 | clk_h.rate = sclk_dmc; | |
228ef987 | 1536 | clk_p.rate = aclk_100; |
c8bef140 | 1537 | |
a855039e KK |
1538 | for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrcs); ptr++) |
1539 | s3c_set_clksrc(&exynos4_clksrcs[ptr], true); | |
c8bef140 CY |
1540 | } |
1541 | ||
a855039e KK |
1542 | static struct clk *exynos4_clks[] __initdata = { |
1543 | &exynos4_clk_sclk_hdmi27m, | |
1544 | &exynos4_clk_sclk_hdmiphy, | |
1545 | &exynos4_clk_sclk_usbphy0, | |
1546 | &exynos4_clk_sclk_usbphy1, | |
c8bef140 CY |
1547 | }; |
1548 | ||
acd35616 JC |
1549 | #ifdef CONFIG_PM_SLEEP |
1550 | static int exynos4_clock_suspend(void) | |
1551 | { | |
1552 | s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save)); | |
1553 | return 0; | |
1554 | } | |
1555 | ||
1556 | static void exynos4_clock_resume(void) | |
1557 | { | |
1558 | s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save)); | |
1559 | } | |
1560 | ||
1561 | #else | |
1562 | #define exynos4_clock_suspend NULL | |
1563 | #define exynos4_clock_resume NULL | |
1564 | #endif | |
1565 | ||
e745e06f | 1566 | static struct syscore_ops exynos4_clock_syscore_ops = { |
acd35616 JC |
1567 | .suspend = exynos4_clock_suspend, |
1568 | .resume = exynos4_clock_resume, | |
1569 | }; | |
1570 | ||
b3ed3a17 | 1571 | void __init exynos4_register_clocks(void) |
c8bef140 | 1572 | { |
c8bef140 CY |
1573 | int ptr; |
1574 | ||
a855039e | 1575 | s3c24xx_register_clocks(exynos4_clks, ARRAY_SIZE(exynos4_clks)); |
c8bef140 | 1576 | |
a855039e KK |
1577 | for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sysclks); ptr++) |
1578 | s3c_register_clksrc(exynos4_sysclks[ptr], 1); | |
c8bef140 | 1579 | |
a855039e KK |
1580 | for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sclk_tv); ptr++) |
1581 | s3c_register_clksrc(exynos4_sclk_tv[ptr], 1); | |
fbf05563 | 1582 | |
a855039e KK |
1583 | for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrc_cdev); ptr++) |
1584 | s3c_register_clksrc(exynos4_clksrc_cdev[ptr], 1); | |
0cfb26e1 | 1585 | |
a855039e KK |
1586 | s3c_register_clksrc(exynos4_clksrcs, ARRAY_SIZE(exynos4_clksrcs)); |
1587 | s3c_register_clocks(exynos4_init_clocks_on, ARRAY_SIZE(exynos4_init_clocks_on)); | |
c8bef140 | 1588 | |
a855039e KK |
1589 | s3c24xx_register_clocks(exynos4_clk_cdev, ARRAY_SIZE(exynos4_clk_cdev)); |
1590 | for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clk_cdev); ptr++) | |
1591 | s3c_disable_clocks(exynos4_clk_cdev[ptr], 1); | |
66fdb29d | 1592 | |
a855039e KK |
1593 | s3c_register_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off)); |
1594 | s3c_disable_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off)); | |
0cfb26e1 | 1595 | clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup)); |
c8bef140 | 1596 | |
acd35616 | 1597 | register_syscore_ops(&exynos4_clock_syscore_ops); |
bf856fbb BK |
1598 | s3c24xx_register_clock(&dummy_apb_pclk); |
1599 | ||
c8bef140 CY |
1600 | s3c_pwmclk_init(); |
1601 | } |