]>
Commit | Line | Data |
---|---|---|
ce9c00ee | 1 | /* |
a855039e | 2 | * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd. |
b3ed3a17 | 3 | * http://www.samsung.com |
c8bef140 | 4 | * |
b3ed3a17 | 5 | * EXYNOS4 - Clock support |
c8bef140 CY |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/err.h> | |
14 | #include <linux/io.h> | |
acd35616 | 15 | #include <linux/syscore_ops.h> |
c8bef140 CY |
16 | |
17 | #include <plat/cpu-freq.h> | |
18 | #include <plat/clock.h> | |
19 | #include <plat/cpu.h> | |
20 | #include <plat/pll.h> | |
21 | #include <plat/s5p-clock.h> | |
22 | #include <plat/clock-clksrc.h> | |
acd35616 | 23 | #include <plat/pm.h> |
c8bef140 CY |
24 | |
25 | #include <mach/map.h> | |
26 | #include <mach/regs-clock.h> | |
b0b6ff0b | 27 | #include <mach/sysmmu.h> |
c8bef140 | 28 | |
cc511b8d | 29 | #include "common.h" |
ce9c00ee | 30 | #include "clock-exynos4.h" |
cc511b8d | 31 | |
7cdf04d7 | 32 | #ifdef CONFIG_PM_SLEEP |
acd35616 | 33 | static struct sleep_save exynos4_clock_save[] = { |
a855039e KK |
34 | SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS), |
35 | SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS), | |
36 | SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS), | |
37 | SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS), | |
38 | SAVE_ITEM(EXYNOS4_CLKSRC_TOP0), | |
39 | SAVE_ITEM(EXYNOS4_CLKSRC_TOP1), | |
40 | SAVE_ITEM(EXYNOS4_CLKSRC_CAM), | |
41 | SAVE_ITEM(EXYNOS4_CLKSRC_TV), | |
42 | SAVE_ITEM(EXYNOS4_CLKSRC_MFC), | |
43 | SAVE_ITEM(EXYNOS4_CLKSRC_G3D), | |
44 | SAVE_ITEM(EXYNOS4_CLKSRC_LCD0), | |
45 | SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO), | |
46 | SAVE_ITEM(EXYNOS4_CLKSRC_FSYS), | |
47 | SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0), | |
48 | SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1), | |
49 | SAVE_ITEM(EXYNOS4_CLKDIV_CAM), | |
50 | SAVE_ITEM(EXYNOS4_CLKDIV_TV), | |
51 | SAVE_ITEM(EXYNOS4_CLKDIV_MFC), | |
52 | SAVE_ITEM(EXYNOS4_CLKDIV_G3D), | |
53 | SAVE_ITEM(EXYNOS4_CLKDIV_LCD0), | |
54 | SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO), | |
55 | SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0), | |
56 | SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1), | |
57 | SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2), | |
58 | SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3), | |
59 | SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0), | |
60 | SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1), | |
61 | SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2), | |
62 | SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3), | |
63 | SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4), | |
64 | SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5), | |
65 | SAVE_ITEM(EXYNOS4_CLKDIV_TOP), | |
66 | SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP), | |
67 | SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM), | |
68 | SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV), | |
69 | SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0), | |
70 | SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO), | |
71 | SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS), | |
72 | SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0), | |
73 | SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1), | |
74 | SAVE_ITEM(EXYNOS4_CLKDIV2_RATIO), | |
75 | SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM), | |
76 | SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM), | |
77 | SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV), | |
78 | SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC), | |
79 | SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D), | |
80 | SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0), | |
81 | SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS), | |
82 | SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS), | |
83 | SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL), | |
84 | SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK), | |
85 | SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC), | |
86 | SAVE_ITEM(EXYNOS4_CLKSRC_DMC), | |
87 | SAVE_ITEM(EXYNOS4_CLKDIV_DMC0), | |
88 | SAVE_ITEM(EXYNOS4_CLKDIV_DMC1), | |
89 | SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC), | |
90 | SAVE_ITEM(EXYNOS4_CLKSRC_CPU), | |
91 | SAVE_ITEM(EXYNOS4_CLKDIV_CPU), | |
92 | SAVE_ITEM(EXYNOS4_CLKDIV_CPU + 0x4), | |
93 | SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU), | |
94 | SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU), | |
acd35616 | 95 | }; |
7cdf04d7 | 96 | #endif |
acd35616 | 97 | |
a855039e | 98 | static struct clk exynos4_clk_sclk_hdmi27m = { |
c8bef140 | 99 | .name = "sclk_hdmi27m", |
c8bef140 CY |
100 | .rate = 27000000, |
101 | }; | |
102 | ||
a855039e | 103 | static struct clk exynos4_clk_sclk_hdmiphy = { |
b99380e1 | 104 | .name = "sclk_hdmiphy", |
b99380e1 JL |
105 | }; |
106 | ||
a855039e | 107 | static struct clk exynos4_clk_sclk_usbphy0 = { |
b99380e1 | 108 | .name = "sclk_usbphy0", |
b99380e1 JL |
109 | .rate = 27000000, |
110 | }; | |
111 | ||
a855039e | 112 | static struct clk exynos4_clk_sclk_usbphy1 = { |
b99380e1 | 113 | .name = "sclk_usbphy1", |
b99380e1 JL |
114 | }; |
115 | ||
bf856fbb BK |
116 | static struct clk dummy_apb_pclk = { |
117 | .name = "apb_pclk", | |
118 | .id = -1, | |
119 | }; | |
120 | ||
b3ed3a17 | 121 | static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable) |
37e01729 | 122 | { |
a855039e | 123 | return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable); |
37e01729 JL |
124 | } |
125 | ||
b3ed3a17 | 126 | static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable) |
33f469d2 | 127 | { |
a855039e | 128 | return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM, clk, enable); |
33f469d2 JL |
129 | } |
130 | ||
b3ed3a17 | 131 | static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable) |
33f469d2 | 132 | { |
a855039e | 133 | return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0, clk, enable); |
33f469d2 JL |
134 | } |
135 | ||
2bc02c0d | 136 | int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable) |
340ea1ef | 137 | { |
a855039e | 138 | return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS, clk, enable); |
340ea1ef JL |
139 | } |
140 | ||
b3ed3a17 | 141 | static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable) |
3297c2e6 | 142 | { |
a855039e | 143 | return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0, clk, enable); |
3297c2e6 JL |
144 | } |
145 | ||
b3ed3a17 | 146 | static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable) |
33f469d2 | 147 | { |
a855039e | 148 | return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1, clk, enable); |
33f469d2 JL |
149 | } |
150 | ||
b0b6ff0b KC |
151 | static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable) |
152 | { | |
a855039e | 153 | return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC, clk, enable); |
b0b6ff0b KC |
154 | } |
155 | ||
fbf05563 TS |
156 | static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable) |
157 | { | |
a855039e | 158 | return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV, clk, enable); |
fbf05563 TS |
159 | } |
160 | ||
b3ed3a17 | 161 | static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable) |
82260bf3 | 162 | { |
a855039e | 163 | return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM, clk, enable); |
82260bf3 JL |
164 | } |
165 | ||
b0b6ff0b KC |
166 | static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable) |
167 | { | |
a855039e | 168 | return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable); |
b0b6ff0b KC |
169 | } |
170 | ||
bca10b90 | 171 | int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable) |
82260bf3 | 172 | { |
a855039e | 173 | return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable); |
82260bf3 JL |
174 | } |
175 | ||
b3ed3a17 | 176 | static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable) |
82260bf3 | 177 | { |
a855039e | 178 | return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0, clk, enable); |
82260bf3 JL |
179 | } |
180 | ||
2bc02c0d | 181 | int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable) |
82260bf3 | 182 | { |
a855039e | 183 | return s5p_gatectrl(EXYNOS4210_CLKGATE_IP_LCD1, clk, enable); |
82260bf3 JL |
184 | } |
185 | ||
2bc02c0d | 186 | int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable) |
340ea1ef | 187 | { |
a855039e | 188 | return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS, clk, enable); |
340ea1ef JL |
189 | } |
190 | ||
b3ed3a17 | 191 | static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable) |
5a847b4a | 192 | { |
a855039e | 193 | return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL, clk, enable); |
5a847b4a JL |
194 | } |
195 | ||
b3ed3a17 | 196 | static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable) |
82260bf3 | 197 | { |
a855039e | 198 | return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable); |
82260bf3 JL |
199 | } |
200 | ||
bca10b90 KC |
201 | int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable) |
202 | { | |
203 | return s5p_gatectrl(EXYNOS4_CLKGATE_IP_DMC, clk, enable); | |
204 | } | |
205 | ||
fbf05563 TS |
206 | static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable) |
207 | { | |
208 | return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable); | |
209 | } | |
210 | ||
211 | static int exynos4_clk_dac_ctrl(struct clk *clk, int enable) | |
212 | { | |
213 | return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable); | |
214 | } | |
215 | ||
c8bef140 CY |
216 | /* Core list of CMU_CPU side */ |
217 | ||
a855039e | 218 | static struct clksrc_clk exynos4_clk_mout_apll = { |
c8bef140 CY |
219 | .clk = { |
220 | .name = "mout_apll", | |
c8bef140 | 221 | }, |
ce9c00ee | 222 | .sources = &clk_src_apll, |
a855039e | 223 | .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 0, .size = 1 }, |
3ff31020 JL |
224 | }; |
225 | ||
a855039e | 226 | static struct clksrc_clk exynos4_clk_sclk_apll = { |
3ff31020 JL |
227 | .clk = { |
228 | .name = "sclk_apll", | |
a855039e | 229 | .parent = &exynos4_clk_mout_apll.clk, |
3ff31020 | 230 | }, |
a855039e | 231 | .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 24, .size = 3 }, |
c8bef140 CY |
232 | }; |
233 | ||
a855039e | 234 | static struct clksrc_clk exynos4_clk_mout_epll = { |
c8bef140 CY |
235 | .clk = { |
236 | .name = "mout_epll", | |
c8bef140 | 237 | }, |
ce9c00ee | 238 | .sources = &clk_src_epll, |
a855039e | 239 | .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 4, .size = 1 }, |
c8bef140 CY |
240 | }; |
241 | ||
a855039e | 242 | struct clksrc_clk exynos4_clk_mout_mpll = { |
ce9c00ee | 243 | .clk = { |
c8bef140 | 244 | .name = "mout_mpll", |
c8bef140 | 245 | }, |
ce9c00ee | 246 | .sources = &clk_src_mpll, |
2bc02c0d KK |
247 | |
248 | /* reg_src will be added in each SoCs' clock */ | |
c8bef140 CY |
249 | }; |
250 | ||
a855039e KK |
251 | static struct clk *exynos4_clkset_moutcore_list[] = { |
252 | [0] = &exynos4_clk_mout_apll.clk, | |
253 | [1] = &exynos4_clk_mout_mpll.clk, | |
c8bef140 CY |
254 | }; |
255 | ||
a855039e KK |
256 | static struct clksrc_sources exynos4_clkset_moutcore = { |
257 | .sources = exynos4_clkset_moutcore_list, | |
258 | .nr_sources = ARRAY_SIZE(exynos4_clkset_moutcore_list), | |
c8bef140 CY |
259 | }; |
260 | ||
a855039e | 261 | static struct clksrc_clk exynos4_clk_moutcore = { |
c8bef140 CY |
262 | .clk = { |
263 | .name = "moutcore", | |
c8bef140 | 264 | }, |
a855039e KK |
265 | .sources = &exynos4_clkset_moutcore, |
266 | .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 16, .size = 1 }, | |
c8bef140 CY |
267 | }; |
268 | ||
a855039e | 269 | static struct clksrc_clk exynos4_clk_coreclk = { |
c8bef140 CY |
270 | .clk = { |
271 | .name = "core_clk", | |
a855039e | 272 | .parent = &exynos4_clk_moutcore.clk, |
c8bef140 | 273 | }, |
a855039e | 274 | .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 0, .size = 3 }, |
c8bef140 CY |
275 | }; |
276 | ||
a855039e | 277 | static struct clksrc_clk exynos4_clk_armclk = { |
c8bef140 CY |
278 | .clk = { |
279 | .name = "armclk", | |
a855039e | 280 | .parent = &exynos4_clk_coreclk.clk, |
c8bef140 CY |
281 | }, |
282 | }; | |
283 | ||
a855039e | 284 | static struct clksrc_clk exynos4_clk_aclk_corem0 = { |
c8bef140 CY |
285 | .clk = { |
286 | .name = "aclk_corem0", | |
a855039e | 287 | .parent = &exynos4_clk_coreclk.clk, |
c8bef140 | 288 | }, |
a855039e | 289 | .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 }, |
c8bef140 CY |
290 | }; |
291 | ||
a855039e | 292 | static struct clksrc_clk exynos4_clk_aclk_cores = { |
c8bef140 CY |
293 | .clk = { |
294 | .name = "aclk_cores", | |
a855039e | 295 | .parent = &exynos4_clk_coreclk.clk, |
c8bef140 | 296 | }, |
a855039e | 297 | .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 }, |
c8bef140 CY |
298 | }; |
299 | ||
a855039e | 300 | static struct clksrc_clk exynos4_clk_aclk_corem1 = { |
c8bef140 CY |
301 | .clk = { |
302 | .name = "aclk_corem1", | |
a855039e | 303 | .parent = &exynos4_clk_coreclk.clk, |
c8bef140 | 304 | }, |
a855039e | 305 | .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 8, .size = 3 }, |
c8bef140 CY |
306 | }; |
307 | ||
a855039e | 308 | static struct clksrc_clk exynos4_clk_periphclk = { |
c8bef140 CY |
309 | .clk = { |
310 | .name = "periphclk", | |
a855039e | 311 | .parent = &exynos4_clk_coreclk.clk, |
c8bef140 | 312 | }, |
a855039e | 313 | .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 }, |
c8bef140 CY |
314 | }; |
315 | ||
c8bef140 CY |
316 | /* Core list of CMU_CORE side */ |
317 | ||
a855039e KK |
318 | static struct clk *exynos4_clkset_corebus_list[] = { |
319 | [0] = &exynos4_clk_mout_mpll.clk, | |
320 | [1] = &exynos4_clk_sclk_apll.clk, | |
c8bef140 CY |
321 | }; |
322 | ||
a855039e KK |
323 | struct clksrc_sources exynos4_clkset_mout_corebus = { |
324 | .sources = exynos4_clkset_corebus_list, | |
325 | .nr_sources = ARRAY_SIZE(exynos4_clkset_corebus_list), | |
c8bef140 CY |
326 | }; |
327 | ||
a855039e | 328 | static struct clksrc_clk exynos4_clk_mout_corebus = { |
c8bef140 CY |
329 | .clk = { |
330 | .name = "mout_corebus", | |
c8bef140 | 331 | }, |
a855039e KK |
332 | .sources = &exynos4_clkset_mout_corebus, |
333 | .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 4, .size = 1 }, | |
c8bef140 CY |
334 | }; |
335 | ||
a855039e | 336 | static struct clksrc_clk exynos4_clk_sclk_dmc = { |
c8bef140 CY |
337 | .clk = { |
338 | .name = "sclk_dmc", | |
a855039e | 339 | .parent = &exynos4_clk_mout_corebus.clk, |
c8bef140 | 340 | }, |
a855039e | 341 | .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 12, .size = 3 }, |
c8bef140 CY |
342 | }; |
343 | ||
a855039e | 344 | static struct clksrc_clk exynos4_clk_aclk_cored = { |
c8bef140 CY |
345 | .clk = { |
346 | .name = "aclk_cored", | |
a855039e | 347 | .parent = &exynos4_clk_sclk_dmc.clk, |
c8bef140 | 348 | }, |
a855039e | 349 | .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 16, .size = 3 }, |
c8bef140 CY |
350 | }; |
351 | ||
a855039e | 352 | static struct clksrc_clk exynos4_clk_aclk_corep = { |
c8bef140 CY |
353 | .clk = { |
354 | .name = "aclk_corep", | |
a855039e | 355 | .parent = &exynos4_clk_aclk_cored.clk, |
c8bef140 | 356 | }, |
a855039e | 357 | .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 20, .size = 3 }, |
c8bef140 CY |
358 | }; |
359 | ||
a855039e | 360 | static struct clksrc_clk exynos4_clk_aclk_acp = { |
c8bef140 CY |
361 | .clk = { |
362 | .name = "aclk_acp", | |
a855039e | 363 | .parent = &exynos4_clk_mout_corebus.clk, |
c8bef140 | 364 | }, |
a855039e | 365 | .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 0, .size = 3 }, |
c8bef140 CY |
366 | }; |
367 | ||
a855039e | 368 | static struct clksrc_clk exynos4_clk_pclk_acp = { |
c8bef140 CY |
369 | .clk = { |
370 | .name = "pclk_acp", | |
a855039e | 371 | .parent = &exynos4_clk_aclk_acp.clk, |
c8bef140 | 372 | }, |
a855039e | 373 | .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 4, .size = 3 }, |
c8bef140 CY |
374 | }; |
375 | ||
376 | /* Core list of CMU_TOP side */ | |
377 | ||
a855039e KK |
378 | struct clk *exynos4_clkset_aclk_top_list[] = { |
379 | [0] = &exynos4_clk_mout_mpll.clk, | |
380 | [1] = &exynos4_clk_sclk_apll.clk, | |
c8bef140 CY |
381 | }; |
382 | ||
a855039e KK |
383 | static struct clksrc_sources exynos4_clkset_aclk = { |
384 | .sources = exynos4_clkset_aclk_top_list, | |
385 | .nr_sources = ARRAY_SIZE(exynos4_clkset_aclk_top_list), | |
c8bef140 CY |
386 | }; |
387 | ||
a855039e | 388 | static struct clksrc_clk exynos4_clk_aclk_200 = { |
c8bef140 CY |
389 | .clk = { |
390 | .name = "aclk_200", | |
c8bef140 | 391 | }, |
a855039e KK |
392 | .sources = &exynos4_clkset_aclk, |
393 | .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 12, .size = 1 }, | |
394 | .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 0, .size = 3 }, | |
c8bef140 CY |
395 | }; |
396 | ||
a855039e | 397 | static struct clksrc_clk exynos4_clk_aclk_100 = { |
c8bef140 CY |
398 | .clk = { |
399 | .name = "aclk_100", | |
c8bef140 | 400 | }, |
a855039e KK |
401 | .sources = &exynos4_clkset_aclk, |
402 | .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 16, .size = 1 }, | |
403 | .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 4, .size = 4 }, | |
c8bef140 CY |
404 | }; |
405 | ||
a855039e | 406 | static struct clksrc_clk exynos4_clk_aclk_160 = { |
c8bef140 CY |
407 | .clk = { |
408 | .name = "aclk_160", | |
c8bef140 | 409 | }, |
a855039e KK |
410 | .sources = &exynos4_clkset_aclk, |
411 | .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 20, .size = 1 }, | |
412 | .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 8, .size = 3 }, | |
c8bef140 CY |
413 | }; |
414 | ||
a855039e | 415 | struct clksrc_clk exynos4_clk_aclk_133 = { |
c8bef140 CY |
416 | .clk = { |
417 | .name = "aclk_133", | |
c8bef140 | 418 | }, |
a855039e KK |
419 | .sources = &exynos4_clkset_aclk, |
420 | .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 24, .size = 1 }, | |
421 | .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 12, .size = 3 }, | |
c8bef140 CY |
422 | }; |
423 | ||
a855039e | 424 | static struct clk *exynos4_clkset_vpllsrc_list[] = { |
c8bef140 | 425 | [0] = &clk_fin_vpll, |
a855039e | 426 | [1] = &exynos4_clk_sclk_hdmi27m, |
c8bef140 CY |
427 | }; |
428 | ||
a855039e KK |
429 | static struct clksrc_sources exynos4_clkset_vpllsrc = { |
430 | .sources = exynos4_clkset_vpllsrc_list, | |
431 | .nr_sources = ARRAY_SIZE(exynos4_clkset_vpllsrc_list), | |
c8bef140 CY |
432 | }; |
433 | ||
a855039e | 434 | static struct clksrc_clk exynos4_clk_vpllsrc = { |
c8bef140 CY |
435 | .clk = { |
436 | .name = "vpll_src", | |
b3ed3a17 | 437 | .enable = exynos4_clksrc_mask_top_ctrl, |
37e01729 | 438 | .ctrlbit = (1 << 0), |
c8bef140 | 439 | }, |
a855039e KK |
440 | .sources = &exynos4_clkset_vpllsrc, |
441 | .reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 0, .size = 1 }, | |
c8bef140 CY |
442 | }; |
443 | ||
a855039e KK |
444 | static struct clk *exynos4_clkset_sclk_vpll_list[] = { |
445 | [0] = &exynos4_clk_vpllsrc.clk, | |
c8bef140 CY |
446 | [1] = &clk_fout_vpll, |
447 | }; | |
448 | ||
a855039e KK |
449 | static struct clksrc_sources exynos4_clkset_sclk_vpll = { |
450 | .sources = exynos4_clkset_sclk_vpll_list, | |
451 | .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_vpll_list), | |
c8bef140 CY |
452 | }; |
453 | ||
a855039e | 454 | static struct clksrc_clk exynos4_clk_sclk_vpll = { |
c8bef140 CY |
455 | .clk = { |
456 | .name = "sclk_vpll", | |
c8bef140 | 457 | }, |
a855039e KK |
458 | .sources = &exynos4_clkset_sclk_vpll, |
459 | .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 }, | |
c8bef140 CY |
460 | }; |
461 | ||
a855039e | 462 | static struct clk exynos4_init_clocks_off[] = { |
c8bef140 CY |
463 | { |
464 | .name = "timers", | |
a855039e | 465 | .parent = &exynos4_clk_aclk_100.clk, |
b3ed3a17 | 466 | .enable = exynos4_clk_ip_peril_ctrl, |
c8bef140 | 467 | .ctrlbit = (1<<24), |
82260bf3 JL |
468 | }, { |
469 | .name = "csis", | |
badc4f2d | 470 | .devname = "s5p-mipi-csis.0", |
b3ed3a17 | 471 | .enable = exynos4_clk_ip_cam_ctrl, |
82260bf3 JL |
472 | .ctrlbit = (1 << 4), |
473 | }, { | |
474 | .name = "csis", | |
badc4f2d | 475 | .devname = "s5p-mipi-csis.1", |
b3ed3a17 | 476 | .enable = exynos4_clk_ip_cam_ctrl, |
82260bf3 | 477 | .ctrlbit = (1 << 5), |
853a0231 AB |
478 | }, { |
479 | .name = "jpeg", | |
480 | .id = 0, | |
481 | .enable = exynos4_clk_ip_cam_ctrl, | |
482 | .ctrlbit = (1 << 6), | |
82260bf3 JL |
483 | }, { |
484 | .name = "fimc", | |
badc4f2d | 485 | .devname = "exynos4-fimc.0", |
b3ed3a17 | 486 | .enable = exynos4_clk_ip_cam_ctrl, |
82260bf3 JL |
487 | .ctrlbit = (1 << 0), |
488 | }, { | |
489 | .name = "fimc", | |
badc4f2d | 490 | .devname = "exynos4-fimc.1", |
b3ed3a17 | 491 | .enable = exynos4_clk_ip_cam_ctrl, |
82260bf3 JL |
492 | .ctrlbit = (1 << 1), |
493 | }, { | |
494 | .name = "fimc", | |
badc4f2d | 495 | .devname = "exynos4-fimc.2", |
b3ed3a17 | 496 | .enable = exynos4_clk_ip_cam_ctrl, |
82260bf3 JL |
497 | .ctrlbit = (1 << 2), |
498 | }, { | |
499 | .name = "fimc", | |
badc4f2d | 500 | .devname = "exynos4-fimc.3", |
b3ed3a17 | 501 | .enable = exynos4_clk_ip_cam_ctrl, |
82260bf3 | 502 | .ctrlbit = (1 << 3), |
340ea1ef JL |
503 | }, { |
504 | .name = "hsmmc", | |
8482c81c | 505 | .devname = "exynos4-sdhci.0", |
a855039e | 506 | .parent = &exynos4_clk_aclk_133.clk, |
b3ed3a17 | 507 | .enable = exynos4_clk_ip_fsys_ctrl, |
340ea1ef JL |
508 | .ctrlbit = (1 << 5), |
509 | }, { | |
510 | .name = "hsmmc", | |
8482c81c | 511 | .devname = "exynos4-sdhci.1", |
a855039e | 512 | .parent = &exynos4_clk_aclk_133.clk, |
b3ed3a17 | 513 | .enable = exynos4_clk_ip_fsys_ctrl, |
340ea1ef JL |
514 | .ctrlbit = (1 << 6), |
515 | }, { | |
516 | .name = "hsmmc", | |
8482c81c | 517 | .devname = "exynos4-sdhci.2", |
a855039e | 518 | .parent = &exynos4_clk_aclk_133.clk, |
b3ed3a17 | 519 | .enable = exynos4_clk_ip_fsys_ctrl, |
340ea1ef JL |
520 | .ctrlbit = (1 << 7), |
521 | }, { | |
522 | .name = "hsmmc", | |
8482c81c | 523 | .devname = "exynos4-sdhci.3", |
a855039e | 524 | .parent = &exynos4_clk_aclk_133.clk, |
b3ed3a17 | 525 | .enable = exynos4_clk_ip_fsys_ctrl, |
340ea1ef JL |
526 | .ctrlbit = (1 << 8), |
527 | }, { | |
badc4f2d | 528 | .name = "dwmmc", |
a855039e | 529 | .parent = &exynos4_clk_aclk_133.clk, |
b3ed3a17 | 530 | .enable = exynos4_clk_ip_fsys_ctrl, |
340ea1ef | 531 | .ctrlbit = (1 << 9), |
3055c6da | 532 | }, { |
fbf05563 TS |
533 | .name = "dac", |
534 | .devname = "s5p-sdo", | |
535 | .enable = exynos4_clk_ip_tv_ctrl, | |
536 | .ctrlbit = (1 << 2), | |
537 | }, { | |
538 | .name = "mixer", | |
539 | .devname = "s5p-mixer", | |
540 | .enable = exynos4_clk_ip_tv_ctrl, | |
541 | .ctrlbit = (1 << 1), | |
542 | }, { | |
543 | .name = "vp", | |
544 | .devname = "s5p-mixer", | |
545 | .enable = exynos4_clk_ip_tv_ctrl, | |
546 | .ctrlbit = (1 << 0), | |
547 | }, { | |
548 | .name = "hdmi", | |
549 | .devname = "exynos4-hdmi", | |
550 | .enable = exynos4_clk_ip_tv_ctrl, | |
551 | .ctrlbit = (1 << 3), | |
552 | }, { | |
553 | .name = "hdmiphy", | |
554 | .devname = "exynos4-hdmi", | |
555 | .enable = exynos4_clk_hdmiphy_ctrl, | |
556 | .ctrlbit = (1 << 0), | |
557 | }, { | |
558 | .name = "dacphy", | |
559 | .devname = "s5p-sdo", | |
560 | .enable = exynos4_clk_dac_ctrl, | |
561 | .ctrlbit = (1 << 0), | |
82260bf3 JL |
562 | }, { |
563 | .name = "adc", | |
b3ed3a17 | 564 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 | 565 | .ctrlbit = (1 << 15), |
f9d7bcbc NKC |
566 | }, { |
567 | .name = "keypad", | |
f9d7bcbc NKC |
568 | .enable = exynos4_clk_ip_perir_ctrl, |
569 | .ctrlbit = (1 << 16), | |
cdff6e6f CY |
570 | }, { |
571 | .name = "rtc", | |
b3ed3a17 | 572 | .enable = exynos4_clk_ip_perir_ctrl, |
cdff6e6f | 573 | .ctrlbit = (1 << 15), |
82260bf3 JL |
574 | }, { |
575 | .name = "watchdog", | |
a855039e | 576 | .parent = &exynos4_clk_aclk_100.clk, |
b3ed3a17 | 577 | .enable = exynos4_clk_ip_perir_ctrl, |
82260bf3 JL |
578 | .ctrlbit = (1 << 14), |
579 | }, { | |
580 | .name = "usbhost", | |
b3ed3a17 | 581 | .enable = exynos4_clk_ip_fsys_ctrl , |
82260bf3 JL |
582 | .ctrlbit = (1 << 12), |
583 | }, { | |
584 | .name = "otg", | |
b3ed3a17 | 585 | .enable = exynos4_clk_ip_fsys_ctrl, |
82260bf3 JL |
586 | .ctrlbit = (1 << 13), |
587 | }, { | |
588 | .name = "spi", | |
a5238e36 | 589 | .devname = "exynos4210-spi.0", |
b3ed3a17 | 590 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 JL |
591 | .ctrlbit = (1 << 16), |
592 | }, { | |
593 | .name = "spi", | |
a5238e36 | 594 | .devname = "exynos4210-spi.1", |
b3ed3a17 | 595 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 JL |
596 | .ctrlbit = (1 << 17), |
597 | }, { | |
598 | .name = "spi", | |
a5238e36 | 599 | .devname = "exynos4210-spi.2", |
b3ed3a17 | 600 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 | 601 | .ctrlbit = (1 << 18), |
2d27043f JB |
602 | }, { |
603 | .name = "iis", | |
badc4f2d | 604 | .devname = "samsung-i2s.0", |
b3ed3a17 | 605 | .enable = exynos4_clk_ip_peril_ctrl, |
2d27043f JB |
606 | .ctrlbit = (1 << 19), |
607 | }, { | |
608 | .name = "iis", | |
badc4f2d | 609 | .devname = "samsung-i2s.1", |
b3ed3a17 | 610 | .enable = exynos4_clk_ip_peril_ctrl, |
2d27043f JB |
611 | .ctrlbit = (1 << 20), |
612 | }, { | |
613 | .name = "iis", | |
badc4f2d | 614 | .devname = "samsung-i2s.2", |
b3ed3a17 | 615 | .enable = exynos4_clk_ip_peril_ctrl, |
2d27043f | 616 | .ctrlbit = (1 << 21), |
aa227557 JB |
617 | }, { |
618 | .name = "ac97", | |
af8a9f63 | 619 | .devname = "samsung-ac97", |
b3ed3a17 | 620 | .enable = exynos4_clk_ip_peril_ctrl, |
aa227557 | 621 | .ctrlbit = (1 << 27), |
82260bf3 JL |
622 | }, { |
623 | .name = "fimg2d", | |
b3ed3a17 | 624 | .enable = exynos4_clk_ip_image_ctrl, |
82260bf3 | 625 | .ctrlbit = (1 << 0), |
0f75a96b KD |
626 | }, { |
627 | .name = "mfc", | |
628 | .devname = "s5p-mfc", | |
629 | .enable = exynos4_clk_ip_mfc_ctrl, | |
630 | .ctrlbit = (1 << 0), | |
82260bf3 JL |
631 | }, { |
632 | .name = "i2c", | |
badc4f2d | 633 | .devname = "s3c2440-i2c.0", |
a855039e | 634 | .parent = &exynos4_clk_aclk_100.clk, |
b3ed3a17 | 635 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 JL |
636 | .ctrlbit = (1 << 6), |
637 | }, { | |
638 | .name = "i2c", | |
badc4f2d | 639 | .devname = "s3c2440-i2c.1", |
a855039e | 640 | .parent = &exynos4_clk_aclk_100.clk, |
b3ed3a17 | 641 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 JL |
642 | .ctrlbit = (1 << 7), |
643 | }, { | |
644 | .name = "i2c", | |
badc4f2d | 645 | .devname = "s3c2440-i2c.2", |
a855039e | 646 | .parent = &exynos4_clk_aclk_100.clk, |
b3ed3a17 | 647 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 JL |
648 | .ctrlbit = (1 << 8), |
649 | }, { | |
650 | .name = "i2c", | |
badc4f2d | 651 | .devname = "s3c2440-i2c.3", |
a855039e | 652 | .parent = &exynos4_clk_aclk_100.clk, |
b3ed3a17 | 653 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 JL |
654 | .ctrlbit = (1 << 9), |
655 | }, { | |
656 | .name = "i2c", | |
badc4f2d | 657 | .devname = "s3c2440-i2c.4", |
a855039e | 658 | .parent = &exynos4_clk_aclk_100.clk, |
b3ed3a17 | 659 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 JL |
660 | .ctrlbit = (1 << 10), |
661 | }, { | |
662 | .name = "i2c", | |
badc4f2d | 663 | .devname = "s3c2440-i2c.5", |
a855039e | 664 | .parent = &exynos4_clk_aclk_100.clk, |
b3ed3a17 | 665 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 JL |
666 | .ctrlbit = (1 << 11), |
667 | }, { | |
668 | .name = "i2c", | |
badc4f2d | 669 | .devname = "s3c2440-i2c.6", |
a855039e | 670 | .parent = &exynos4_clk_aclk_100.clk, |
b3ed3a17 | 671 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 JL |
672 | .ctrlbit = (1 << 12), |
673 | }, { | |
674 | .name = "i2c", | |
badc4f2d | 675 | .devname = "s3c2440-i2c.7", |
a855039e | 676 | .parent = &exynos4_clk_aclk_100.clk, |
b3ed3a17 | 677 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 | 678 | .ctrlbit = (1 << 13), |
c40e7e0d TS |
679 | }, { |
680 | .name = "i2c", | |
681 | .devname = "s3c2440-hdmiphy-i2c", | |
a855039e | 682 | .parent = &exynos4_clk_aclk_100.clk, |
c40e7e0d TS |
683 | .enable = exynos4_clk_ip_peril_ctrl, |
684 | .ctrlbit = (1 << 14), | |
b0b6ff0b | 685 | }, { |
bca10b90 KC |
686 | .name = SYSMMU_CLOCK_NAME, |
687 | .devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0), | |
688 | .enable = exynos4_clk_ip_mfc_ctrl, | |
689 | .ctrlbit = (1 << 1), | |
690 | }, { | |
691 | .name = SYSMMU_CLOCK_NAME, | |
692 | .devname = SYSMMU_CLOCK_DEVNAME(mfc_r, 1), | |
693 | .enable = exynos4_clk_ip_mfc_ctrl, | |
694 | .ctrlbit = (1 << 2), | |
695 | }, { | |
696 | .name = SYSMMU_CLOCK_NAME, | |
697 | .devname = SYSMMU_CLOCK_DEVNAME(tv, 2), | |
698 | .enable = exynos4_clk_ip_tv_ctrl, | |
699 | .ctrlbit = (1 << 4), | |
700 | }, { | |
701 | .name = SYSMMU_CLOCK_NAME, | |
702 | .devname = SYSMMU_CLOCK_DEVNAME(jpeg, 3), | |
703 | .enable = exynos4_clk_ip_cam_ctrl, | |
704 | .ctrlbit = (1 << 11), | |
705 | }, { | |
706 | .name = SYSMMU_CLOCK_NAME, | |
707 | .devname = SYSMMU_CLOCK_DEVNAME(rot, 4), | |
b0b6ff0b | 708 | .enable = exynos4_clk_ip_image_ctrl, |
bca10b90 | 709 | .ctrlbit = (1 << 4), |
b0b6ff0b | 710 | }, { |
bca10b90 KC |
711 | .name = SYSMMU_CLOCK_NAME, |
712 | .devname = SYSMMU_CLOCK_DEVNAME(fimc0, 5), | |
b0b6ff0b KC |
713 | .enable = exynos4_clk_ip_cam_ctrl, |
714 | .ctrlbit = (1 << 7), | |
715 | }, { | |
bca10b90 KC |
716 | .name = SYSMMU_CLOCK_NAME, |
717 | .devname = SYSMMU_CLOCK_DEVNAME(fimc1, 6), | |
b0b6ff0b KC |
718 | .enable = exynos4_clk_ip_cam_ctrl, |
719 | .ctrlbit = (1 << 8), | |
720 | }, { | |
bca10b90 KC |
721 | .name = SYSMMU_CLOCK_NAME, |
722 | .devname = SYSMMU_CLOCK_DEVNAME(fimc2, 7), | |
b0b6ff0b KC |
723 | .enable = exynos4_clk_ip_cam_ctrl, |
724 | .ctrlbit = (1 << 9), | |
725 | }, { | |
bca10b90 KC |
726 | .name = SYSMMU_CLOCK_NAME, |
727 | .devname = SYSMMU_CLOCK_DEVNAME(fimc3, 8), | |
b0b6ff0b KC |
728 | .enable = exynos4_clk_ip_cam_ctrl, |
729 | .ctrlbit = (1 << 10), | |
730 | }, { | |
bca10b90 KC |
731 | .name = SYSMMU_CLOCK_NAME, |
732 | .devname = SYSMMU_CLOCK_DEVNAME(fimd0, 10), | |
b0b6ff0b KC |
733 | .enable = exynos4_clk_ip_lcd0_ctrl, |
734 | .ctrlbit = (1 << 4), | |
b0b6ff0b | 735 | } |
c8bef140 CY |
736 | }; |
737 | ||
a855039e | 738 | static struct clk exynos4_init_clocks_on[] = { |
5a847b4a JL |
739 | { |
740 | .name = "uart", | |
badc4f2d | 741 | .devname = "s5pv210-uart.0", |
b3ed3a17 | 742 | .enable = exynos4_clk_ip_peril_ctrl, |
5a847b4a JL |
743 | .ctrlbit = (1 << 0), |
744 | }, { | |
745 | .name = "uart", | |
badc4f2d | 746 | .devname = "s5pv210-uart.1", |
b3ed3a17 | 747 | .enable = exynos4_clk_ip_peril_ctrl, |
5a847b4a JL |
748 | .ctrlbit = (1 << 1), |
749 | }, { | |
750 | .name = "uart", | |
badc4f2d | 751 | .devname = "s5pv210-uart.2", |
b3ed3a17 | 752 | .enable = exynos4_clk_ip_peril_ctrl, |
5a847b4a JL |
753 | .ctrlbit = (1 << 2), |
754 | }, { | |
755 | .name = "uart", | |
badc4f2d | 756 | .devname = "s5pv210-uart.3", |
b3ed3a17 | 757 | .enable = exynos4_clk_ip_peril_ctrl, |
5a847b4a JL |
758 | .ctrlbit = (1 << 3), |
759 | }, { | |
760 | .name = "uart", | |
badc4f2d | 761 | .devname = "s5pv210-uart.4", |
b3ed3a17 | 762 | .enable = exynos4_clk_ip_peril_ctrl, |
5a847b4a JL |
763 | .ctrlbit = (1 << 4), |
764 | }, { | |
765 | .name = "uart", | |
badc4f2d | 766 | .devname = "s5pv210-uart.5", |
b3ed3a17 | 767 | .enable = exynos4_clk_ip_peril_ctrl, |
5a847b4a JL |
768 | .ctrlbit = (1 << 5), |
769 | } | |
c8bef140 CY |
770 | }; |
771 | ||
a855039e | 772 | static struct clk exynos4_clk_pdma0 = { |
66fdb29d TA |
773 | .name = "dma", |
774 | .devname = "dma-pl330.0", | |
775 | .enable = exynos4_clk_ip_fsys_ctrl, | |
776 | .ctrlbit = (1 << 0), | |
777 | }; | |
778 | ||
a855039e | 779 | static struct clk exynos4_clk_pdma1 = { |
66fdb29d TA |
780 | .name = "dma", |
781 | .devname = "dma-pl330.1", | |
782 | .enable = exynos4_clk_ip_fsys_ctrl, | |
783 | .ctrlbit = (1 << 1), | |
784 | }; | |
785 | ||
9ed76e03 BK |
786 | static struct clk exynos4_clk_mdma1 = { |
787 | .name = "dma", | |
788 | .devname = "dma-pl330.2", | |
789 | .enable = exynos4_clk_ip_image_ctrl, | |
790 | .ctrlbit = ((1 << 8) | (1 << 5) | (1 << 2)), | |
791 | }; | |
792 | ||
79025466 TB |
793 | static struct clk exynos4_clk_fimd0 = { |
794 | .name = "fimd", | |
795 | .devname = "exynos4-fb.0", | |
796 | .enable = exynos4_clk_ip_lcd0_ctrl, | |
797 | .ctrlbit = (1 << 0), | |
798 | }; | |
799 | ||
a855039e | 800 | struct clk *exynos4_clkset_group_list[] = { |
c8bef140 CY |
801 | [0] = &clk_ext_xtal_mux, |
802 | [1] = &clk_xusbxti, | |
a855039e KK |
803 | [2] = &exynos4_clk_sclk_hdmi27m, |
804 | [3] = &exynos4_clk_sclk_usbphy0, | |
805 | [4] = &exynos4_clk_sclk_usbphy1, | |
806 | [5] = &exynos4_clk_sclk_hdmiphy, | |
807 | [6] = &exynos4_clk_mout_mpll.clk, | |
808 | [7] = &exynos4_clk_mout_epll.clk, | |
809 | [8] = &exynos4_clk_sclk_vpll.clk, | |
c8bef140 CY |
810 | }; |
811 | ||
a855039e KK |
812 | struct clksrc_sources exynos4_clkset_group = { |
813 | .sources = exynos4_clkset_group_list, | |
814 | .nr_sources = ARRAY_SIZE(exynos4_clkset_group_list), | |
c8bef140 CY |
815 | }; |
816 | ||
a855039e KK |
817 | static struct clk *exynos4_clkset_mout_g2d0_list[] = { |
818 | [0] = &exynos4_clk_mout_mpll.clk, | |
819 | [1] = &exynos4_clk_sclk_apll.clk, | |
06cba8d5 JL |
820 | }; |
821 | ||
a855039e KK |
822 | static struct clksrc_sources exynos4_clkset_mout_g2d0 = { |
823 | .sources = exynos4_clkset_mout_g2d0_list, | |
824 | .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list), | |
06cba8d5 JL |
825 | }; |
826 | ||
a855039e | 827 | static struct clksrc_clk exynos4_clk_mout_g2d0 = { |
06cba8d5 JL |
828 | .clk = { |
829 | .name = "mout_g2d0", | |
06cba8d5 | 830 | }, |
a855039e KK |
831 | .sources = &exynos4_clkset_mout_g2d0, |
832 | .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 }, | |
06cba8d5 JL |
833 | }; |
834 | ||
a855039e KK |
835 | static struct clk *exynos4_clkset_mout_g2d1_list[] = { |
836 | [0] = &exynos4_clk_mout_epll.clk, | |
837 | [1] = &exynos4_clk_sclk_vpll.clk, | |
06cba8d5 JL |
838 | }; |
839 | ||
a855039e KK |
840 | static struct clksrc_sources exynos4_clkset_mout_g2d1 = { |
841 | .sources = exynos4_clkset_mout_g2d1_list, | |
842 | .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list), | |
06cba8d5 JL |
843 | }; |
844 | ||
a855039e | 845 | static struct clksrc_clk exynos4_clk_mout_g2d1 = { |
06cba8d5 JL |
846 | .clk = { |
847 | .name = "mout_g2d1", | |
06cba8d5 | 848 | }, |
a855039e KK |
849 | .sources = &exynos4_clkset_mout_g2d1, |
850 | .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 }, | |
06cba8d5 JL |
851 | }; |
852 | ||
a855039e KK |
853 | static struct clk *exynos4_clkset_mout_g2d_list[] = { |
854 | [0] = &exynos4_clk_mout_g2d0.clk, | |
855 | [1] = &exynos4_clk_mout_g2d1.clk, | |
06cba8d5 JL |
856 | }; |
857 | ||
a855039e KK |
858 | static struct clksrc_sources exynos4_clkset_mout_g2d = { |
859 | .sources = exynos4_clkset_mout_g2d_list, | |
860 | .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d_list), | |
06cba8d5 JL |
861 | }; |
862 | ||
a855039e KK |
863 | static struct clk *exynos4_clkset_mout_mfc0_list[] = { |
864 | [0] = &exynos4_clk_mout_mpll.clk, | |
865 | [1] = &exynos4_clk_sclk_apll.clk, | |
0f75a96b KD |
866 | }; |
867 | ||
a855039e KK |
868 | static struct clksrc_sources exynos4_clkset_mout_mfc0 = { |
869 | .sources = exynos4_clkset_mout_mfc0_list, | |
870 | .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc0_list), | |
0f75a96b KD |
871 | }; |
872 | ||
a855039e | 873 | static struct clksrc_clk exynos4_clk_mout_mfc0 = { |
0f75a96b KD |
874 | .clk = { |
875 | .name = "mout_mfc0", | |
876 | }, | |
a855039e KK |
877 | .sources = &exynos4_clkset_mout_mfc0, |
878 | .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 0, .size = 1 }, | |
0f75a96b KD |
879 | }; |
880 | ||
a855039e KK |
881 | static struct clk *exynos4_clkset_mout_mfc1_list[] = { |
882 | [0] = &exynos4_clk_mout_epll.clk, | |
883 | [1] = &exynos4_clk_sclk_vpll.clk, | |
0f75a96b KD |
884 | }; |
885 | ||
a855039e KK |
886 | static struct clksrc_sources exynos4_clkset_mout_mfc1 = { |
887 | .sources = exynos4_clkset_mout_mfc1_list, | |
888 | .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc1_list), | |
0f75a96b KD |
889 | }; |
890 | ||
a855039e | 891 | static struct clksrc_clk exynos4_clk_mout_mfc1 = { |
0f75a96b KD |
892 | .clk = { |
893 | .name = "mout_mfc1", | |
894 | }, | |
a855039e KK |
895 | .sources = &exynos4_clkset_mout_mfc1, |
896 | .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 4, .size = 1 }, | |
0f75a96b KD |
897 | }; |
898 | ||
a855039e KK |
899 | static struct clk *exynos4_clkset_mout_mfc_list[] = { |
900 | [0] = &exynos4_clk_mout_mfc0.clk, | |
901 | [1] = &exynos4_clk_mout_mfc1.clk, | |
0f75a96b KD |
902 | }; |
903 | ||
a855039e KK |
904 | static struct clksrc_sources exynos4_clkset_mout_mfc = { |
905 | .sources = exynos4_clkset_mout_mfc_list, | |
906 | .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc_list), | |
0f75a96b KD |
907 | }; |
908 | ||
a855039e KK |
909 | static struct clk *exynos4_clkset_sclk_dac_list[] = { |
910 | [0] = &exynos4_clk_sclk_vpll.clk, | |
911 | [1] = &exynos4_clk_sclk_hdmiphy, | |
fbf05563 TS |
912 | }; |
913 | ||
a855039e KK |
914 | static struct clksrc_sources exynos4_clkset_sclk_dac = { |
915 | .sources = exynos4_clkset_sclk_dac_list, | |
916 | .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_dac_list), | |
fbf05563 TS |
917 | }; |
918 | ||
a855039e | 919 | static struct clksrc_clk exynos4_clk_sclk_dac = { |
fbf05563 TS |
920 | .clk = { |
921 | .name = "sclk_dac", | |
922 | .enable = exynos4_clksrc_mask_tv_ctrl, | |
923 | .ctrlbit = (1 << 8), | |
924 | }, | |
a855039e KK |
925 | .sources = &exynos4_clkset_sclk_dac, |
926 | .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 8, .size = 1 }, | |
fbf05563 TS |
927 | }; |
928 | ||
a855039e | 929 | static struct clksrc_clk exynos4_clk_sclk_pixel = { |
fbf05563 TS |
930 | .clk = { |
931 | .name = "sclk_pixel", | |
a855039e | 932 | .parent = &exynos4_clk_sclk_vpll.clk, |
fbf05563 | 933 | }, |
a855039e | 934 | .reg_div = { .reg = EXYNOS4_CLKDIV_TV, .shift = 0, .size = 4 }, |
fbf05563 TS |
935 | }; |
936 | ||
a855039e KK |
937 | static struct clk *exynos4_clkset_sclk_hdmi_list[] = { |
938 | [0] = &exynos4_clk_sclk_pixel.clk, | |
939 | [1] = &exynos4_clk_sclk_hdmiphy, | |
fbf05563 TS |
940 | }; |
941 | ||
a855039e KK |
942 | static struct clksrc_sources exynos4_clkset_sclk_hdmi = { |
943 | .sources = exynos4_clkset_sclk_hdmi_list, | |
944 | .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list), | |
fbf05563 TS |
945 | }; |
946 | ||
a855039e | 947 | static struct clksrc_clk exynos4_clk_sclk_hdmi = { |
fbf05563 TS |
948 | .clk = { |
949 | .name = "sclk_hdmi", | |
950 | .enable = exynos4_clksrc_mask_tv_ctrl, | |
951 | .ctrlbit = (1 << 0), | |
952 | }, | |
a855039e KK |
953 | .sources = &exynos4_clkset_sclk_hdmi, |
954 | .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 0, .size = 1 }, | |
fbf05563 TS |
955 | }; |
956 | ||
a855039e KK |
957 | static struct clk *exynos4_clkset_sclk_mixer_list[] = { |
958 | [0] = &exynos4_clk_sclk_dac.clk, | |
959 | [1] = &exynos4_clk_sclk_hdmi.clk, | |
fbf05563 TS |
960 | }; |
961 | ||
a855039e KK |
962 | static struct clksrc_sources exynos4_clkset_sclk_mixer = { |
963 | .sources = exynos4_clkset_sclk_mixer_list, | |
964 | .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_mixer_list), | |
fbf05563 TS |
965 | }; |
966 | ||
a855039e | 967 | static struct clksrc_clk exynos4_clk_sclk_mixer = { |
ce9c00ee | 968 | .clk = { |
fbf05563 TS |
969 | .name = "sclk_mixer", |
970 | .enable = exynos4_clksrc_mask_tv_ctrl, | |
971 | .ctrlbit = (1 << 4), | |
972 | }, | |
a855039e KK |
973 | .sources = &exynos4_clkset_sclk_mixer, |
974 | .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 4, .size = 1 }, | |
fbf05563 TS |
975 | }; |
976 | ||
a855039e KK |
977 | static struct clksrc_clk *exynos4_sclk_tv[] = { |
978 | &exynos4_clk_sclk_dac, | |
979 | &exynos4_clk_sclk_pixel, | |
980 | &exynos4_clk_sclk_hdmi, | |
981 | &exynos4_clk_sclk_mixer, | |
fbf05563 TS |
982 | }; |
983 | ||
a855039e | 984 | static struct clksrc_clk exynos4_clk_dout_mmc0 = { |
ce9c00ee | 985 | .clk = { |
340ea1ef | 986 | .name = "dout_mmc0", |
340ea1ef | 987 | }, |
a855039e KK |
988 | .sources = &exynos4_clkset_group, |
989 | .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 0, .size = 4 }, | |
990 | .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 0, .size = 4 }, | |
340ea1ef JL |
991 | }; |
992 | ||
a855039e | 993 | static struct clksrc_clk exynos4_clk_dout_mmc1 = { |
ce9c00ee | 994 | .clk = { |
340ea1ef | 995 | .name = "dout_mmc1", |
340ea1ef | 996 | }, |
a855039e KK |
997 | .sources = &exynos4_clkset_group, |
998 | .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 4, .size = 4 }, | |
999 | .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 16, .size = 4 }, | |
340ea1ef JL |
1000 | }; |
1001 | ||
a855039e | 1002 | static struct clksrc_clk exynos4_clk_dout_mmc2 = { |
ce9c00ee | 1003 | .clk = { |
340ea1ef | 1004 | .name = "dout_mmc2", |
340ea1ef | 1005 | }, |
a855039e KK |
1006 | .sources = &exynos4_clkset_group, |
1007 | .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 8, .size = 4 }, | |
1008 | .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 0, .size = 4 }, | |
340ea1ef JL |
1009 | }; |
1010 | ||
a855039e | 1011 | static struct clksrc_clk exynos4_clk_dout_mmc3 = { |
ce9c00ee | 1012 | .clk = { |
340ea1ef | 1013 | .name = "dout_mmc3", |
340ea1ef | 1014 | }, |
a855039e KK |
1015 | .sources = &exynos4_clkset_group, |
1016 | .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 12, .size = 4 }, | |
1017 | .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 16, .size = 4 }, | |
340ea1ef JL |
1018 | }; |
1019 | ||
a855039e | 1020 | static struct clksrc_clk exynos4_clk_dout_mmc4 = { |
340ea1ef JL |
1021 | .clk = { |
1022 | .name = "dout_mmc4", | |
340ea1ef | 1023 | }, |
a855039e KK |
1024 | .sources = &exynos4_clkset_group, |
1025 | .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 16, .size = 4 }, | |
1026 | .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 0, .size = 4 }, | |
340ea1ef JL |
1027 | }; |
1028 | ||
a855039e | 1029 | static struct clksrc_clk exynos4_clksrcs[] = { |
c8bef140 | 1030 | { |
ce9c00ee | 1031 | .clk = { |
c8bef140 | 1032 | .name = "sclk_pwm", |
b3ed3a17 | 1033 | .enable = exynos4_clksrc_mask_peril0_ctrl, |
c8bef140 CY |
1034 | .ctrlbit = (1 << 24), |
1035 | }, | |
a855039e KK |
1036 | .sources = &exynos4_clkset_group, |
1037 | .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 24, .size = 4 }, | |
1038 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL3, .shift = 0, .size = 4 }, | |
33f469d2 | 1039 | }, { |
ce9c00ee | 1040 | .clk = { |
33f469d2 | 1041 | .name = "sclk_csis", |
badc4f2d | 1042 | .devname = "s5p-mipi-csis.0", |
b3ed3a17 | 1043 | .enable = exynos4_clksrc_mask_cam_ctrl, |
33f469d2 JL |
1044 | .ctrlbit = (1 << 24), |
1045 | }, | |
a855039e KK |
1046 | .sources = &exynos4_clkset_group, |
1047 | .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 24, .size = 4 }, | |
1048 | .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 24, .size = 4 }, | |
33f469d2 | 1049 | }, { |
ce9c00ee | 1050 | .clk = { |
33f469d2 | 1051 | .name = "sclk_csis", |
badc4f2d | 1052 | .devname = "s5p-mipi-csis.1", |
b3ed3a17 | 1053 | .enable = exynos4_clksrc_mask_cam_ctrl, |
33f469d2 JL |
1054 | .ctrlbit = (1 << 28), |
1055 | }, | |
a855039e KK |
1056 | .sources = &exynos4_clkset_group, |
1057 | .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 28, .size = 4 }, | |
1058 | .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 28, .size = 4 }, | |
33f469d2 | 1059 | }, { |
ce9c00ee | 1060 | .clk = { |
00aaad22 | 1061 | .name = "sclk_cam0", |
b3ed3a17 | 1062 | .enable = exynos4_clksrc_mask_cam_ctrl, |
33f469d2 JL |
1063 | .ctrlbit = (1 << 16), |
1064 | }, | |
a855039e KK |
1065 | .sources = &exynos4_clkset_group, |
1066 | .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 16, .size = 4 }, | |
1067 | .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 16, .size = 4 }, | |
33f469d2 | 1068 | }, { |
ce9c00ee | 1069 | .clk = { |
00aaad22 | 1070 | .name = "sclk_cam1", |
b3ed3a17 | 1071 | .enable = exynos4_clksrc_mask_cam_ctrl, |
33f469d2 JL |
1072 | .ctrlbit = (1 << 20), |
1073 | }, | |
a855039e KK |
1074 | .sources = &exynos4_clkset_group, |
1075 | .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 20, .size = 4 }, | |
1076 | .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 20, .size = 4 }, | |
33f469d2 | 1077 | }, { |
ce9c00ee | 1078 | .clk = { |
33f469d2 | 1079 | .name = "sclk_fimc", |
badc4f2d | 1080 | .devname = "exynos4-fimc.0", |
b3ed3a17 | 1081 | .enable = exynos4_clksrc_mask_cam_ctrl, |
33f469d2 JL |
1082 | .ctrlbit = (1 << 0), |
1083 | }, | |
a855039e KK |
1084 | .sources = &exynos4_clkset_group, |
1085 | .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 0, .size = 4 }, | |
1086 | .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 0, .size = 4 }, | |
33f469d2 | 1087 | }, { |
ce9c00ee | 1088 | .clk = { |
33f469d2 | 1089 | .name = "sclk_fimc", |
badc4f2d | 1090 | .devname = "exynos4-fimc.1", |
b3ed3a17 | 1091 | .enable = exynos4_clksrc_mask_cam_ctrl, |
33f469d2 JL |
1092 | .ctrlbit = (1 << 4), |
1093 | }, | |
a855039e KK |
1094 | .sources = &exynos4_clkset_group, |
1095 | .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 4, .size = 4 }, | |
1096 | .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 4, .size = 4 }, | |
33f469d2 | 1097 | }, { |
ce9c00ee | 1098 | .clk = { |
33f469d2 | 1099 | .name = "sclk_fimc", |
badc4f2d | 1100 | .devname = "exynos4-fimc.2", |
b3ed3a17 | 1101 | .enable = exynos4_clksrc_mask_cam_ctrl, |
33f469d2 JL |
1102 | .ctrlbit = (1 << 8), |
1103 | }, | |
a855039e KK |
1104 | .sources = &exynos4_clkset_group, |
1105 | .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 8, .size = 4 }, | |
1106 | .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 8, .size = 4 }, | |
33f469d2 | 1107 | }, { |
ce9c00ee | 1108 | .clk = { |
33f469d2 | 1109 | .name = "sclk_fimc", |
badc4f2d | 1110 | .devname = "exynos4-fimc.3", |
b3ed3a17 | 1111 | .enable = exynos4_clksrc_mask_cam_ctrl, |
33f469d2 JL |
1112 | .ctrlbit = (1 << 12), |
1113 | }, | |
a855039e KK |
1114 | .sources = &exynos4_clkset_group, |
1115 | .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 12, .size = 4 }, | |
1116 | .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 12, .size = 4 }, | |
33f469d2 | 1117 | }, { |
ce9c00ee | 1118 | .clk = { |
33f469d2 | 1119 | .name = "sclk_fimd", |
268a7ef2 | 1120 | .devname = "exynos4-fb.0", |
b3ed3a17 | 1121 | .enable = exynos4_clksrc_mask_lcd0_ctrl, |
33f469d2 JL |
1122 | .ctrlbit = (1 << 0), |
1123 | }, | |
a855039e KK |
1124 | .sources = &exynos4_clkset_group, |
1125 | .reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 }, | |
1126 | .reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 }, | |
33f469d2 | 1127 | }, { |
ce9c00ee | 1128 | .clk = { |
33f469d2 | 1129 | .name = "sclk_fimg2d", |
33f469d2 | 1130 | }, |
a855039e KK |
1131 | .sources = &exynos4_clkset_mout_g2d, |
1132 | .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 }, | |
1133 | .reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 }, | |
0f75a96b | 1134 | }, { |
ce9c00ee | 1135 | .clk = { |
0f75a96b KD |
1136 | .name = "sclk_mfc", |
1137 | .devname = "s5p-mfc", | |
1138 | }, | |
a855039e KK |
1139 | .sources = &exynos4_clkset_mout_mfc, |
1140 | .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 }, | |
1141 | .reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 }, | |
340ea1ef | 1142 | }, { |
ce9c00ee | 1143 | .clk = { |
badc4f2d | 1144 | .name = "sclk_dwmmc", |
a855039e | 1145 | .parent = &exynos4_clk_dout_mmc4.clk, |
b3ed3a17 | 1146 | .enable = exynos4_clksrc_mask_fsys_ctrl, |
340ea1ef JL |
1147 | .ctrlbit = (1 << 16), |
1148 | }, | |
a855039e | 1149 | .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 }, |
340ea1ef | 1150 | } |
c8bef140 CY |
1151 | }; |
1152 | ||
a855039e | 1153 | static struct clksrc_clk exynos4_clk_sclk_uart0 = { |
0cfb26e1 TA |
1154 | .clk = { |
1155 | .name = "uclk1", | |
1156 | .devname = "exynos4210-uart.0", | |
1157 | .enable = exynos4_clksrc_mask_peril0_ctrl, | |
1158 | .ctrlbit = (1 << 0), | |
1159 | }, | |
a855039e KK |
1160 | .sources = &exynos4_clkset_group, |
1161 | .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 0, .size = 4 }, | |
1162 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 0, .size = 4 }, | |
0cfb26e1 TA |
1163 | }; |
1164 | ||
a855039e | 1165 | static struct clksrc_clk exynos4_clk_sclk_uart1 = { |
ce9c00ee | 1166 | .clk = { |
0cfb26e1 TA |
1167 | .name = "uclk1", |
1168 | .devname = "exynos4210-uart.1", | |
1169 | .enable = exynos4_clksrc_mask_peril0_ctrl, | |
1170 | .ctrlbit = (1 << 4), | |
1171 | }, | |
a855039e KK |
1172 | .sources = &exynos4_clkset_group, |
1173 | .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 4, .size = 4 }, | |
1174 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 4, .size = 4 }, | |
0cfb26e1 TA |
1175 | }; |
1176 | ||
a855039e | 1177 | static struct clksrc_clk exynos4_clk_sclk_uart2 = { |
ce9c00ee | 1178 | .clk = { |
0cfb26e1 TA |
1179 | .name = "uclk1", |
1180 | .devname = "exynos4210-uart.2", | |
1181 | .enable = exynos4_clksrc_mask_peril0_ctrl, | |
1182 | .ctrlbit = (1 << 8), | |
1183 | }, | |
a855039e KK |
1184 | .sources = &exynos4_clkset_group, |
1185 | .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 8, .size = 4 }, | |
1186 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 8, .size = 4 }, | |
0cfb26e1 TA |
1187 | }; |
1188 | ||
a855039e | 1189 | static struct clksrc_clk exynos4_clk_sclk_uart3 = { |
ce9c00ee | 1190 | .clk = { |
0cfb26e1 TA |
1191 | .name = "uclk1", |
1192 | .devname = "exynos4210-uart.3", | |
1193 | .enable = exynos4_clksrc_mask_peril0_ctrl, | |
1194 | .ctrlbit = (1 << 12), | |
1195 | }, | |
a855039e KK |
1196 | .sources = &exynos4_clkset_group, |
1197 | .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 12, .size = 4 }, | |
1198 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 12, .size = 4 }, | |
0cfb26e1 TA |
1199 | }; |
1200 | ||
a855039e | 1201 | static struct clksrc_clk exynos4_clk_sclk_mmc0 = { |
ce9c00ee | 1202 | .clk = { |
a361d10a | 1203 | .name = "sclk_mmc", |
8482c81c | 1204 | .devname = "exynos4-sdhci.0", |
a855039e | 1205 | .parent = &exynos4_clk_dout_mmc0.clk, |
a361d10a RS |
1206 | .enable = exynos4_clksrc_mask_fsys_ctrl, |
1207 | .ctrlbit = (1 << 0), | |
1208 | }, | |
a855039e | 1209 | .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 8, .size = 8 }, |
a361d10a RS |
1210 | }; |
1211 | ||
a855039e | 1212 | static struct clksrc_clk exynos4_clk_sclk_mmc1 = { |
ce9c00ee | 1213 | .clk = { |
a361d10a | 1214 | .name = "sclk_mmc", |
8482c81c | 1215 | .devname = "exynos4-sdhci.1", |
a855039e | 1216 | .parent = &exynos4_clk_dout_mmc1.clk, |
a361d10a RS |
1217 | .enable = exynos4_clksrc_mask_fsys_ctrl, |
1218 | .ctrlbit = (1 << 4), | |
1219 | }, | |
a855039e | 1220 | .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 24, .size = 8 }, |
a361d10a RS |
1221 | }; |
1222 | ||
a855039e | 1223 | static struct clksrc_clk exynos4_clk_sclk_mmc2 = { |
ce9c00ee | 1224 | .clk = { |
a361d10a | 1225 | .name = "sclk_mmc", |
8482c81c | 1226 | .devname = "exynos4-sdhci.2", |
a855039e | 1227 | .parent = &exynos4_clk_dout_mmc2.clk, |
a361d10a RS |
1228 | .enable = exynos4_clksrc_mask_fsys_ctrl, |
1229 | .ctrlbit = (1 << 8), | |
1230 | }, | |
a855039e | 1231 | .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 8, .size = 8 }, |
a361d10a RS |
1232 | }; |
1233 | ||
a855039e | 1234 | static struct clksrc_clk exynos4_clk_sclk_mmc3 = { |
ce9c00ee | 1235 | .clk = { |
a361d10a | 1236 | .name = "sclk_mmc", |
8482c81c | 1237 | .devname = "exynos4-sdhci.3", |
a855039e | 1238 | .parent = &exynos4_clk_dout_mmc3.clk, |
a361d10a RS |
1239 | .enable = exynos4_clksrc_mask_fsys_ctrl, |
1240 | .ctrlbit = (1 << 12), | |
1241 | }, | |
a855039e | 1242 | .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 }, |
a361d10a RS |
1243 | }; |
1244 | ||
a855039e | 1245 | static struct clksrc_clk exynos4_clk_sclk_spi0 = { |
ce9c00ee | 1246 | .clk = { |
74ac23a3 | 1247 | .name = "sclk_spi", |
a5238e36 | 1248 | .devname = "exynos4210-spi.0", |
74ac23a3 | 1249 | .enable = exynos4_clksrc_mask_peril1_ctrl, |
ce9c00ee | 1250 | .ctrlbit = (1 << 16), |
74ac23a3 | 1251 | }, |
a855039e KK |
1252 | .sources = &exynos4_clkset_group, |
1253 | .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 }, | |
1254 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 }, | |
74ac23a3 PV |
1255 | }; |
1256 | ||
a855039e | 1257 | static struct clksrc_clk exynos4_clk_sclk_spi1 = { |
ce9c00ee | 1258 | .clk = { |
74ac23a3 | 1259 | .name = "sclk_spi", |
a5238e36 | 1260 | .devname = "exynos4210-spi.1", |
74ac23a3 | 1261 | .enable = exynos4_clksrc_mask_peril1_ctrl, |
ce9c00ee | 1262 | .ctrlbit = (1 << 20), |
74ac23a3 | 1263 | }, |
a855039e KK |
1264 | .sources = &exynos4_clkset_group, |
1265 | .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 }, | |
1266 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 }, | |
74ac23a3 PV |
1267 | }; |
1268 | ||
a855039e | 1269 | static struct clksrc_clk exynos4_clk_sclk_spi2 = { |
ce9c00ee | 1270 | .clk = { |
74ac23a3 | 1271 | .name = "sclk_spi", |
a5238e36 | 1272 | .devname = "exynos4210-spi.2", |
74ac23a3 | 1273 | .enable = exynos4_clksrc_mask_peril1_ctrl, |
ce9c00ee | 1274 | .ctrlbit = (1 << 24), |
74ac23a3 | 1275 | }, |
a855039e KK |
1276 | .sources = &exynos4_clkset_group, |
1277 | .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 }, | |
1278 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 }, | |
74ac23a3 PV |
1279 | }; |
1280 | ||
c8bef140 | 1281 | /* Clock initialization code */ |
a855039e KK |
1282 | static struct clksrc_clk *exynos4_sysclks[] = { |
1283 | &exynos4_clk_mout_apll, | |
1284 | &exynos4_clk_sclk_apll, | |
1285 | &exynos4_clk_mout_epll, | |
1286 | &exynos4_clk_mout_mpll, | |
1287 | &exynos4_clk_moutcore, | |
1288 | &exynos4_clk_coreclk, | |
1289 | &exynos4_clk_armclk, | |
1290 | &exynos4_clk_aclk_corem0, | |
1291 | &exynos4_clk_aclk_cores, | |
1292 | &exynos4_clk_aclk_corem1, | |
1293 | &exynos4_clk_periphclk, | |
1294 | &exynos4_clk_mout_corebus, | |
1295 | &exynos4_clk_sclk_dmc, | |
1296 | &exynos4_clk_aclk_cored, | |
1297 | &exynos4_clk_aclk_corep, | |
1298 | &exynos4_clk_aclk_acp, | |
1299 | &exynos4_clk_pclk_acp, | |
1300 | &exynos4_clk_vpllsrc, | |
1301 | &exynos4_clk_sclk_vpll, | |
1302 | &exynos4_clk_aclk_200, | |
1303 | &exynos4_clk_aclk_100, | |
1304 | &exynos4_clk_aclk_160, | |
1305 | &exynos4_clk_aclk_133, | |
1306 | &exynos4_clk_dout_mmc0, | |
1307 | &exynos4_clk_dout_mmc1, | |
1308 | &exynos4_clk_dout_mmc2, | |
1309 | &exynos4_clk_dout_mmc3, | |
1310 | &exynos4_clk_dout_mmc4, | |
1311 | &exynos4_clk_mout_mfc0, | |
1312 | &exynos4_clk_mout_mfc1, | |
1313 | }; | |
1314 | ||
1315 | static struct clk *exynos4_clk_cdev[] = { | |
1316 | &exynos4_clk_pdma0, | |
1317 | &exynos4_clk_pdma1, | |
9ed76e03 | 1318 | &exynos4_clk_mdma1, |
79025466 | 1319 | &exynos4_clk_fimd0, |
a855039e KK |
1320 | }; |
1321 | ||
1322 | static struct clksrc_clk *exynos4_clksrc_cdev[] = { | |
1323 | &exynos4_clk_sclk_uart0, | |
1324 | &exynos4_clk_sclk_uart1, | |
1325 | &exynos4_clk_sclk_uart2, | |
1326 | &exynos4_clk_sclk_uart3, | |
1327 | &exynos4_clk_sclk_mmc0, | |
1328 | &exynos4_clk_sclk_mmc1, | |
1329 | &exynos4_clk_sclk_mmc2, | |
1330 | &exynos4_clk_sclk_mmc3, | |
1331 | &exynos4_clk_sclk_spi0, | |
1332 | &exynos4_clk_sclk_spi1, | |
1333 | &exynos4_clk_sclk_spi2, | |
74ac23a3 | 1334 | |
0cfb26e1 TA |
1335 | }; |
1336 | ||
1337 | static struct clk_lookup exynos4_clk_lookup[] = { | |
a855039e KK |
1338 | CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos4_clk_sclk_uart0.clk), |
1339 | CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk), | |
1340 | CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk), | |
1341 | CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk), | |
8482c81c TA |
1342 | CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk), |
1343 | CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk), | |
1344 | CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk), | |
1345 | CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk), | |
79025466 | 1346 | CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0), |
a855039e KK |
1347 | CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0), |
1348 | CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1), | |
8f7b1321 | 1349 | CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1), |
a5238e36 TA |
1350 | CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk), |
1351 | CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk), | |
1352 | CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk), | |
0cfb26e1 TA |
1353 | }; |
1354 | ||
877d1b57 JL |
1355 | static int xtal_rate; |
1356 | ||
b3ed3a17 | 1357 | static unsigned long exynos4_fout_apll_get_rate(struct clk *clk) |
877d1b57 | 1358 | { |
2bc02c0d | 1359 | if (soc_is_exynos4210()) |
a855039e | 1360 | return s5p_get_pll45xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0), |
2bc02c0d | 1361 | pll_4508); |
b88b1cc7 | 1362 | else if (soc_is_exynos4212() || soc_is_exynos4412()) |
a855039e | 1363 | return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0)); |
2bc02c0d KK |
1364 | else |
1365 | return 0; | |
877d1b57 JL |
1366 | } |
1367 | ||
b3ed3a17 KK |
1368 | static struct clk_ops exynos4_fout_apll_ops = { |
1369 | .get_rate = exynos4_fout_apll_get_rate, | |
877d1b57 JL |
1370 | }; |
1371 | ||
a855039e | 1372 | static u32 exynos4_vpll_div[][8] = { |
fbf05563 TS |
1373 | { 54000000, 3, 53, 3, 1024, 0, 17, 0 }, |
1374 | { 108000000, 3, 53, 2, 1024, 0, 17, 0 }, | |
1375 | }; | |
1376 | ||
1377 | static unsigned long exynos4_vpll_get_rate(struct clk *clk) | |
1378 | { | |
1379 | return clk->rate; | |
1380 | } | |
1381 | ||
1382 | static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate) | |
1383 | { | |
1384 | unsigned int vpll_con0, vpll_con1 = 0; | |
1385 | unsigned int i; | |
1386 | ||
1387 | /* Return if nothing changed */ | |
1388 | if (clk->rate == rate) | |
1389 | return 0; | |
1390 | ||
a855039e | 1391 | vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0); |
fbf05563 TS |
1392 | vpll_con0 &= ~(0x1 << 27 | \ |
1393 | PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \ | |
1394 | PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \ | |
1395 | PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT); | |
1396 | ||
a855039e | 1397 | vpll_con1 = __raw_readl(EXYNOS4_VPLL_CON1); |
fbf05563 TS |
1398 | vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT | \ |
1399 | PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \ | |
1400 | PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT); | |
1401 | ||
a855039e KK |
1402 | for (i = 0; i < ARRAY_SIZE(exynos4_vpll_div); i++) { |
1403 | if (exynos4_vpll_div[i][0] == rate) { | |
1404 | vpll_con0 |= exynos4_vpll_div[i][1] << PLL46XX_PDIV_SHIFT; | |
1405 | vpll_con0 |= exynos4_vpll_div[i][2] << PLL46XX_MDIV_SHIFT; | |
1406 | vpll_con0 |= exynos4_vpll_div[i][3] << PLL46XX_SDIV_SHIFT; | |
1407 | vpll_con1 |= exynos4_vpll_div[i][4] << PLL46XX_KDIV_SHIFT; | |
1408 | vpll_con1 |= exynos4_vpll_div[i][5] << PLL46XX_MFR_SHIFT; | |
1409 | vpll_con1 |= exynos4_vpll_div[i][6] << PLL46XX_MRR_SHIFT; | |
1410 | vpll_con0 |= exynos4_vpll_div[i][7] << 27; | |
fbf05563 TS |
1411 | break; |
1412 | } | |
1413 | } | |
1414 | ||
a855039e | 1415 | if (i == ARRAY_SIZE(exynos4_vpll_div)) { |
fbf05563 TS |
1416 | printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n", |
1417 | __func__); | |
1418 | return -EINVAL; | |
1419 | } | |
1420 | ||
a855039e KK |
1421 | __raw_writel(vpll_con0, EXYNOS4_VPLL_CON0); |
1422 | __raw_writel(vpll_con1, EXYNOS4_VPLL_CON1); | |
fbf05563 TS |
1423 | |
1424 | /* Wait for VPLL lock */ | |
a855039e | 1425 | while (!(__raw_readl(EXYNOS4_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT))) |
fbf05563 TS |
1426 | continue; |
1427 | ||
1428 | clk->rate = rate; | |
1429 | return 0; | |
1430 | } | |
1431 | ||
1432 | static struct clk_ops exynos4_vpll_ops = { | |
1433 | .get_rate = exynos4_vpll_get_rate, | |
1434 | .set_rate = exynos4_vpll_set_rate, | |
1435 | }; | |
1436 | ||
b3ed3a17 | 1437 | void __init_or_cpufreq exynos4_setup_clocks(void) |
c8bef140 CY |
1438 | { |
1439 | struct clk *xtal_clk; | |
2bc02c0d KK |
1440 | unsigned long apll = 0; |
1441 | unsigned long mpll = 0; | |
1442 | unsigned long epll = 0; | |
1443 | unsigned long vpll = 0; | |
c8bef140 CY |
1444 | unsigned long vpllsrc; |
1445 | unsigned long xtal; | |
1446 | unsigned long armclk; | |
c8bef140 | 1447 | unsigned long sclk_dmc; |
228ef987 JL |
1448 | unsigned long aclk_200; |
1449 | unsigned long aclk_100; | |
1450 | unsigned long aclk_160; | |
1451 | unsigned long aclk_133; | |
c8bef140 CY |
1452 | unsigned int ptr; |
1453 | ||
1454 | printk(KERN_DEBUG "%s: registering clocks\n", __func__); | |
1455 | ||
1456 | xtal_clk = clk_get(NULL, "xtal"); | |
1457 | BUG_ON(IS_ERR(xtal_clk)); | |
1458 | ||
1459 | xtal = clk_get_rate(xtal_clk); | |
877d1b57 JL |
1460 | |
1461 | xtal_rate = xtal; | |
1462 | ||
c8bef140 CY |
1463 | clk_put(xtal_clk); |
1464 | ||
1465 | printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); | |
1466 | ||
2bc02c0d | 1467 | if (soc_is_exynos4210()) { |
a855039e | 1468 | apll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_APLL_CON0), |
2bc02c0d | 1469 | pll_4508); |
a855039e | 1470 | mpll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0), |
2bc02c0d | 1471 | pll_4508); |
a855039e KK |
1472 | epll = s5p_get_pll46xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0), |
1473 | __raw_readl(EXYNOS4_EPLL_CON1), pll_4600); | |
2bc02c0d | 1474 | |
a855039e KK |
1475 | vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk); |
1476 | vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0), | |
1477 | __raw_readl(EXYNOS4_VPLL_CON1), pll_4650c); | |
b88b1cc7 | 1478 | } else if (soc_is_exynos4212() || soc_is_exynos4412()) { |
a855039e KK |
1479 | apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_APLL_CON0)); |
1480 | mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0)); | |
1481 | epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0), | |
1482 | __raw_readl(EXYNOS4_EPLL_CON1)); | |
1483 | ||
1484 | vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk); | |
1485 | vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0), | |
1486 | __raw_readl(EXYNOS4_VPLL_CON1)); | |
2bc02c0d KK |
1487 | } else { |
1488 | /* nothing */ | |
1489 | } | |
c8bef140 | 1490 | |
b3ed3a17 | 1491 | clk_fout_apll.ops = &exynos4_fout_apll_ops; |
c8bef140 CY |
1492 | clk_fout_mpll.rate = mpll; |
1493 | clk_fout_epll.rate = epll; | |
fbf05563 | 1494 | clk_fout_vpll.ops = &exynos4_vpll_ops; |
c8bef140 CY |
1495 | clk_fout_vpll.rate = vpll; |
1496 | ||
b3ed3a17 | 1497 | printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld", |
c8bef140 CY |
1498 | apll, mpll, epll, vpll); |
1499 | ||
a855039e KK |
1500 | armclk = clk_get_rate(&exynos4_clk_armclk.clk); |
1501 | sclk_dmc = clk_get_rate(&exynos4_clk_sclk_dmc.clk); | |
a6aa7a55 | 1502 | |
a855039e KK |
1503 | aclk_200 = clk_get_rate(&exynos4_clk_aclk_200.clk); |
1504 | aclk_100 = clk_get_rate(&exynos4_clk_aclk_100.clk); | |
1505 | aclk_160 = clk_get_rate(&exynos4_clk_aclk_160.clk); | |
1506 | aclk_133 = clk_get_rate(&exynos4_clk_aclk_133.clk); | |
228ef987 | 1507 | |
b3ed3a17 | 1508 | printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n" |
228ef987 JL |
1509 | "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n", |
1510 | armclk, sclk_dmc, aclk_200, | |
1511 | aclk_100, aclk_160, aclk_133); | |
c8bef140 CY |
1512 | |
1513 | clk_f.rate = armclk; | |
1514 | clk_h.rate = sclk_dmc; | |
228ef987 | 1515 | clk_p.rate = aclk_100; |
c8bef140 | 1516 | |
a855039e KK |
1517 | for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrcs); ptr++) |
1518 | s3c_set_clksrc(&exynos4_clksrcs[ptr], true); | |
c8bef140 CY |
1519 | } |
1520 | ||
a855039e KK |
1521 | static struct clk *exynos4_clks[] __initdata = { |
1522 | &exynos4_clk_sclk_hdmi27m, | |
1523 | &exynos4_clk_sclk_hdmiphy, | |
1524 | &exynos4_clk_sclk_usbphy0, | |
1525 | &exynos4_clk_sclk_usbphy1, | |
c8bef140 CY |
1526 | }; |
1527 | ||
acd35616 JC |
1528 | #ifdef CONFIG_PM_SLEEP |
1529 | static int exynos4_clock_suspend(void) | |
1530 | { | |
1531 | s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save)); | |
1532 | return 0; | |
1533 | } | |
1534 | ||
1535 | static void exynos4_clock_resume(void) | |
1536 | { | |
1537 | s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save)); | |
1538 | } | |
1539 | ||
1540 | #else | |
1541 | #define exynos4_clock_suspend NULL | |
1542 | #define exynos4_clock_resume NULL | |
1543 | #endif | |
1544 | ||
e745e06f | 1545 | static struct syscore_ops exynos4_clock_syscore_ops = { |
acd35616 JC |
1546 | .suspend = exynos4_clock_suspend, |
1547 | .resume = exynos4_clock_resume, | |
1548 | }; | |
1549 | ||
b3ed3a17 | 1550 | void __init exynos4_register_clocks(void) |
c8bef140 | 1551 | { |
c8bef140 CY |
1552 | int ptr; |
1553 | ||
a855039e | 1554 | s3c24xx_register_clocks(exynos4_clks, ARRAY_SIZE(exynos4_clks)); |
c8bef140 | 1555 | |
a855039e KK |
1556 | for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sysclks); ptr++) |
1557 | s3c_register_clksrc(exynos4_sysclks[ptr], 1); | |
c8bef140 | 1558 | |
a855039e KK |
1559 | for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sclk_tv); ptr++) |
1560 | s3c_register_clksrc(exynos4_sclk_tv[ptr], 1); | |
fbf05563 | 1561 | |
a855039e KK |
1562 | for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrc_cdev); ptr++) |
1563 | s3c_register_clksrc(exynos4_clksrc_cdev[ptr], 1); | |
0cfb26e1 | 1564 | |
a855039e KK |
1565 | s3c_register_clksrc(exynos4_clksrcs, ARRAY_SIZE(exynos4_clksrcs)); |
1566 | s3c_register_clocks(exynos4_init_clocks_on, ARRAY_SIZE(exynos4_init_clocks_on)); | |
c8bef140 | 1567 | |
a855039e KK |
1568 | s3c24xx_register_clocks(exynos4_clk_cdev, ARRAY_SIZE(exynos4_clk_cdev)); |
1569 | for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clk_cdev); ptr++) | |
1570 | s3c_disable_clocks(exynos4_clk_cdev[ptr], 1); | |
66fdb29d | 1571 | |
a855039e KK |
1572 | s3c_register_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off)); |
1573 | s3c_disable_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off)); | |
0cfb26e1 | 1574 | clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup)); |
c8bef140 | 1575 | |
acd35616 | 1576 | register_syscore_ops(&exynos4_clock_syscore_ops); |
bf856fbb BK |
1577 | s3c24xx_register_clock(&dummy_apb_pclk); |
1578 | ||
c8bef140 CY |
1579 | s3c_pwmclk_init(); |
1580 | } |