[mirror_ubuntu-bionic-kernel.git] / arch / arm / mach-exynos / common.c

/*
 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * Common Codes for EXYNOS
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/io.h>
#include <linux/device.h>
#include <linux/gpio.h>
#include <clocksource/samsung_pwm.h>
#include <linux/sched.h>
#include <linux/serial_core.h>
#include <linux/of.h>
#include <linux/of_fdt.h>
#include <linux/of_irq.h>
#include <linux/pm_domain.h>
#include <linux/export.h>
#include <linux/irqdomain.h>
#include <linux/of_address.h>
#include <linux/irqchip/arm-gic.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/platform_device.h>

#include <asm/proc-fns.h>
#include <asm/exception.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/cacheflush.h>

#include <plat/cpu.h>
#include <plat/pm.h>
#include <plat/regs-serial.h>

#include "common.h"
#include "regs-pmu.h"

#define L2_AUX_VAL 0x7C470001
#define L2_AUX_MASK 0xC200ffff

static const char name_exynos4210[] = "EXYNOS4210";
static const char name_exynos4212[] = "EXYNOS4212";
static const char name_exynos4412[] = "EXYNOS4412";
static const char name_exynos5250[] = "EXYNOS5250";
static const char name_exynos5420[] = "EXYNOS5420";
static const char name_exynos5440[] = "EXYNOS5440";

static void exynos4_map_io(void);
static void exynos5_map_io(void);
static int exynos_init(void);

static struct cpu_table cpu_ids[] __initdata = {
	{
		.idcode		= EXYNOS4210_CPU_ID,
		.idmask		= EXYNOS4_CPU_MASK,
		.map_io		= exynos4_map_io,
		.init		= exynos_init,
		.name		= name_exynos4210,
	}, {
		.idcode		= EXYNOS4212_CPU_ID,
		.idmask		= EXYNOS4_CPU_MASK,
		.map_io		= exynos4_map_io,
		.init		= exynos_init,
		.name		= name_exynos4212,
	}, {
		.idcode		= EXYNOS4412_CPU_ID,
		.idmask		= EXYNOS4_CPU_MASK,
		.map_io		= exynos4_map_io,
		.init		= exynos_init,
		.name		= name_exynos4412,
	}, {
		.idcode		= EXYNOS5250_SOC_ID,
		.idmask		= EXYNOS5_SOC_MASK,
		.map_io		= exynos5_map_io,
		.init		= exynos_init,
		.name		= name_exynos5250,
	}, {
		.idcode		= EXYNOS5420_SOC_ID,
		.idmask		= EXYNOS5_SOC_MASK,
		.map_io		= exynos5_map_io,
		.init		= exynos_init,
		.name		= name_exynos5420,
	}, {
		.idcode		= EXYNOS5440_SOC_ID,
		.idmask		= EXYNOS5_SOC_MASK,
		.init		= exynos_init,
		.name		= name_exynos5440,
	},
};

/* Initial IO mappings */

static struct map_desc exynos4_iodesc[] __initdata = {
	{
		.virtual	= (unsigned long)S3C_VA_SYS,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_SYSCON),
		.length		= SZ_64K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_TIMER,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_TIMER),
		.length		= SZ_16K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_WATCHDOG,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_SROMC,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_SROMC),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_SYSTIMER,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_PMU,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_PMU),
		.length		= SZ_64K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_COMBINER_BASE,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_COMBINER),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_GIC_CPU,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
		.length		= SZ_64K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_GIC_DIST,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
		.length		= SZ_64K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_CMU,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_CMU),
		.length		= SZ_128K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_COREPERI_BASE,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_COREPERI),
		.length		= SZ_8K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_L2CC,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_L2CC),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_DMC0,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_DMC0),
		.length		= SZ_64K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_DMC1,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_DMC1),
		.length		= SZ_64K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_USB_HSPHY,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_HSPHY),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	},
};

static struct map_desc exynos4_iodesc0[] __initdata = {
	{
		.virtual	= (unsigned long)S5P_VA_SYSRAM,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	},
};

static struct map_desc exynos4_iodesc1[] __initdata = {
	{
		.virtual	= (unsigned long)S5P_VA_SYSRAM,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	},
};

static struct map_desc exynos4210_iodesc[] __initdata = {
	{
		.virtual	= (unsigned long)S5P_VA_SYSRAM_NS,
		.pfn		= __phys_to_pfn(EXYNOS4210_PA_SYSRAM_NS),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	},
};

static struct map_desc exynos4x12_iodesc[] __initdata = {
	{
		.virtual	= (unsigned long)S5P_VA_SYSRAM_NS,
		.pfn		= __phys_to_pfn(EXYNOS4x12_PA_SYSRAM_NS),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	},
};

static struct map_desc exynos5250_iodesc[] __initdata = {
	{
		.virtual	= (unsigned long)S5P_VA_SYSRAM_NS,
		.pfn		= __phys_to_pfn(EXYNOS5250_PA_SYSRAM_NS),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	},
};

static struct map_desc exynos5_iodesc[] __initdata = {
	{
		.virtual	= (unsigned long)S3C_VA_SYS,
		.pfn		= __phys_to_pfn(EXYNOS5_PA_SYSCON),
		.length		= SZ_64K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_TIMER,
		.pfn		= __phys_to_pfn(EXYNOS5_PA_TIMER),
		.length		= SZ_16K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_WATCHDOG,
		.pfn		= __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_SROMC,
		.pfn		= __phys_to_pfn(EXYNOS5_PA_SROMC),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_SYSRAM,
		.pfn		= __phys_to_pfn(EXYNOS5_PA_SYSRAM),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_CMU,
		.pfn		= __phys_to_pfn(EXYNOS5_PA_CMU),
		.length		= 144 * SZ_1K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_PMU,
		.pfn		= __phys_to_pfn(EXYNOS5_PA_PMU),
		.length		= SZ_64K,
		.type		= MT_DEVICE,
	},
};

void exynos4_restart(enum reboot_mode mode, const char *cmd)
{
	__raw_writel(0x1, S5P_SWRESET);
}

void exynos5_restart(enum reboot_mode mode, const char *cmd)
{
	struct device_node *np;
	u32 val;
	void __iomem *addr;

	val = 0x1;
	addr = EXYNOS_SWRESET;

	if (of_machine_is_compatible("samsung,exynos5440")) {
		u32 status;
		np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");

		addr = of_iomap(np, 0) + 0xbc;
		status = __raw_readl(addr);

		addr = of_iomap(np, 0) + 0xcc;
		val = __raw_readl(addr);

		val = (val & 0xffff0000) | (status & 0xffff);
	}

	__raw_writel(val, addr);
}

static struct platform_device exynos_cpuidle = {
	.name		= "exynos_cpuidle",
	.id		= -1,
};

void __init exynos_cpuidle_init(void)
{
	platform_device_register(&exynos_cpuidle);
}

void __init exynos_cpufreq_init(void)
{
	platform_device_register_simple("exynos-cpufreq", -1, NULL, 0);
}

void __init exynos_init_late(void)
{
	if (of_machine_is_compatible("samsung,exynos5440"))
		/* to be supported later */
		return;

	pm_genpd_poweroff_unused();
}

static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
					int depth, void *data)
{
	struct map_desc iodesc;
	__be32 *reg;
	unsigned long len;

	if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid") &&
		!of_flat_dt_is_compatible(node, "samsung,exynos5440-clock"))
		return 0;

	reg = of_get_flat_dt_prop(node, "reg", &len);
	if (reg == NULL || len != (sizeof(unsigned long) * 2))
		return 0;

	iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
	iodesc.length = be32_to_cpu(reg[1]) - 1;
	iodesc.virtual = (unsigned long)S5P_VA_CHIPID;
	iodesc.type = MT_DEVICE;
	iotable_init(&iodesc, 1);
	return 1;
}

/*
 * exynos_map_io
 *
 * register the standard cpu IO areas
 */

void __init exynos_init_io(void)
{
	debug_ll_io_init();

	of_scan_flat_dt(exynos_fdt_map_chipid, NULL);

	/* detect cpu id and rev. */
	s5p_init_cpu(S5P_VA_CHIPID);

	s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
}

static void __init exynos4_map_io(void)
{
	iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));

	if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
		iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
	else
		iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));

	if (soc_is_exynos4210())
		iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
	if (soc_is_exynos4212() || soc_is_exynos4412())
		iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
}

static void __init exynos5_map_io(void)
{
	iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));

	if (soc_is_exynos5250())
		iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
}

struct bus_type exynos_subsys = {
	.name		= "exynos-core",
	.dev_name	= "exynos-core",
};

static struct device exynos4_dev = {
	.bus	= &exynos_subsys,
};

static int __init exynos_core_init(void)
{
	return subsys_system_register(&exynos_subsys, NULL);
}
core_initcall(exynos_core_init);

static int __init exynos4_l2x0_cache_init(void)
{
	int ret;

	ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
	if (ret)
		return ret;

	l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
	clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
	return 0;
}
early_initcall(exynos4_l2x0_cache_init);

static int __init exynos_init(void)
{
	printk(KERN_INFO "EXYNOS: Initializing architecture\n");

	return device_register(&exynos4_dev);
}
Commit	Line	Data
cc511b8d KK	1	/*
	2	* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
	3	* http://www.samsung.com
	4	*
	5	* Common Codes for EXYNOS
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/kernel.h>
68a433f1	13	#include <linux/bitops.h>
cc511b8d KK	14	#include <linux/interrupt.h>
cc511b8d KK	15	#include <linux/irq.h>
a900e5d9	16	#include <linux/irqchip.h>
cc511b8d	17	#include <linux/io.h>
7affca35	18	#include <linux/device.h>
cc511b8d	19	#include <linux/gpio.h>
68a433f1	20	#include <clocksource/samsung_pwm.h>
cc511b8d KK	21	#include <linux/sched.h>
cc511b8d KK	22	#include <linux/serial_core.h>
237c78be	23	#include <linux/of.h>
5b7897db	24	#include <linux/of_fdt.h>
237c78be	25	#include <linux/of_irq.h>
1fd3cbcc	26	#include <linux/pm_domain.h>
1e60bc0b TA	27	#include <linux/export.h>
1e60bc0b TA	28	#include <linux/irqdomain.h>
e873a47c	29	#include <linux/of_address.h>
520f7bd7	30	#include <linux/irqchip/arm-gic.h>
de88cbb7	31	#include <linux/irqchip/chained_irq.h>
35baa336	32	#include <linux/platform_device.h>
cc511b8d KK	33
cc511b8d KK	34	#include <asm/proc-fns.h>
40ba95fd	35	#include <asm/exception.h>
cc511b8d	36	#include <asm/hardware/cache-l2x0.h>
cc511b8d KK	37	#include <asm/mach/map.h>
cc511b8d KK	38	#include <asm/mach/irq.h>
b756a50f	39	#include <asm/cacheflush.h>
cc511b8d	40
cc511b8d	41	#include <plat/cpu.h>
cc511b8d	42	#include <plat/pm.h>
cc511b8d KK	43	#include <plat/regs-serial.h>
	44
	45	#include "common.h"
65c9a853 KK	46	#include "regs-pmu.h"
65c9a853 KK	47
6cdeddcc ADK	48	#define L2_AUX_VAL 0x7C470001
6cdeddcc ADK	49	#define L2_AUX_MASK 0xC200ffff
cc511b8d	50
cc511b8d KK	51	static const char name_exynos4210[] = "EXYNOS4210";
	52	static const char name_exynos4212[] = "EXYNOS4212";
	53	static const char name_exynos4412[] = "EXYNOS4412";
94c7ca71	54	static const char name_exynos5250[] = "EXYNOS5250";
191d754f	55	static const char name_exynos5420[] = "EXYNOS5420";
2edb36c4	56	static const char name_exynos5440[] = "EXYNOS5440";
cc511b8d	57
906c789c	58	static void exynos4_map_io(void);
94c7ca71	59	static void exynos5_map_io(void);
906c789c	60	static int exynos_init(void);
cc511b8d KK	61
	62	static struct cpu_table cpu_ids[] __initdata = {
	63	{
	64	.idcode = EXYNOS4210_CPU_ID,
	65	.idmask = EXYNOS4_CPU_MASK,
	66	.map_io = exynos4_map_io,
cc511b8d KK	67	.init = exynos_init,
	68	.name = name_exynos4210,
	69	}, {
	70	.idcode = EXYNOS4212_CPU_ID,
	71	.idmask = EXYNOS4_CPU_MASK,
	72	.map_io = exynos4_map_io,
cc511b8d KK	73	.init = exynos_init,
	74	.name = name_exynos4212,
	75	}, {
	76	.idcode = EXYNOS4412_CPU_ID,
	77	.idmask = EXYNOS4_CPU_MASK,
	78	.map_io = exynos4_map_io,
cc511b8d KK	79	.init = exynos_init,
cc511b8d KK	80	.name = name_exynos4412,
94c7ca71 KK	81	}, {
	82	.idcode = EXYNOS5250_SOC_ID,
	83	.idmask = EXYNOS5_SOC_MASK,
	84	.map_io = exynos5_map_io,
94c7ca71 KK	85	.init = exynos_init,
94c7ca71 KK	86	.name = name_exynos5250,
191d754f CK	87	}, {
	88	.idcode = EXYNOS5420_SOC_ID,
	89	.idmask = EXYNOS5_SOC_MASK,
	90	.map_io = exynos5_map_io,
	91	.init = exynos_init,
	92	.name = name_exynos5420,
2edb36c4 KK	93	}, {
	94	.idcode = EXYNOS5440_SOC_ID,
	95	.idmask = EXYNOS5_SOC_MASK,
2edb36c4 KK	96	.init = exynos_init,
2edb36c4 KK	97	.name = name_exynos5440,
cc511b8d KK	98	},
	99	};
	100
	101	/* Initial IO mappings */
	102
94c7ca71 KK	103	static struct map_desc exynos4_iodesc[] __initdata = {
94c7ca71 KK	104	{
cc511b8d KK	105	.virtual = (unsigned long)S3C_VA_SYS,
	106	.pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
	107	.length = SZ_64K,
	108	.type = MT_DEVICE,
	109	}, {
	110	.virtual = (unsigned long)S3C_VA_TIMER,
	111	.pfn = __phys_to_pfn(EXYNOS4_PA_TIMER),
	112	.length = SZ_16K,
	113	.type = MT_DEVICE,
	114	}, {
	115	.virtual = (unsigned long)S3C_VA_WATCHDOG,
	116	.pfn = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
	117	.length = SZ_4K,
	118	.type = MT_DEVICE,
	119	}, {
	120	.virtual = (unsigned long)S5P_VA_SROMC,
	121	.pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
	122	.length = SZ_4K,
	123	.type = MT_DEVICE,
	124	}, {
	125	.virtual = (unsigned long)S5P_VA_SYSTIMER,
	126	.pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
	127	.length = SZ_4K,
	128	.type = MT_DEVICE,
	129	}, {
	130	.virtual = (unsigned long)S5P_VA_PMU,
	131	.pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
	132	.length = SZ_64K,
	133	.type = MT_DEVICE,
	134	}, {
	135	.virtual = (unsigned long)S5P_VA_COMBINER_BASE,
	136	.pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
	137	.length = SZ_4K,
	138	.type = MT_DEVICE,
	139	}, {
	140	.virtual = (unsigned long)S5P_VA_GIC_CPU,
	141	.pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
	142	.length = SZ_64K,
	143	.type = MT_DEVICE,
	144	}, {
	145	.virtual = (unsigned long)S5P_VA_GIC_DIST,
	146	.pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
	147	.length = SZ_64K,
	148	.type = MT_DEVICE,
94c7ca71	149	}, {
cc511b8d KK	150	.virtual = (unsigned long)S5P_VA_CMU,
	151	.pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
	152	.length = SZ_128K,
	153	.type = MT_DEVICE,
	154	}, {
	155	.virtual = (unsigned long)S5P_VA_COREPERI_BASE,
	156	.pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
	157	.length = SZ_8K,
	158	.type = MT_DEVICE,
	159	}, {
	160	.virtual = (unsigned long)S5P_VA_L2CC,
	161	.pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
	162	.length = SZ_4K,
	163	.type = MT_DEVICE,
cc511b8d KK	164	}, {
	165	.virtual = (unsigned long)S5P_VA_DMC0,
	166	.pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
2bde0b08 MH	167	.length = SZ_64K,
	168	.type = MT_DEVICE,
	169	}, {
	170	.virtual = (unsigned long)S5P_VA_DMC1,
	171	.pfn = __phys_to_pfn(EXYNOS4_PA_DMC1),
	172	.length = SZ_64K,
cc511b8d	173	.type = MT_DEVICE,
cc511b8d KK	174	}, {
	175	.virtual = (unsigned long)S3C_VA_USB_HSPHY,
	176	.pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
	177	.length = SZ_4K,
	178	.type = MT_DEVICE,
	179	},
	180	};
	181
	182	static struct map_desc exynos4_iodesc0[] __initdata = {
	183	{
	184	.virtual = (unsigned long)S5P_VA_SYSRAM,
	185	.pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
	186	.length = SZ_4K,
	187	.type = MT_DEVICE,
	188	},
	189	};
	190
	191	static struct map_desc exynos4_iodesc1[] __initdata = {
	192	{
	193	.virtual = (unsigned long)S5P_VA_SYSRAM,
	194	.pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
	195	.length = SZ_4K,
	196	.type = MT_DEVICE,
	197	},
	198	};
	199
41de8986 TF	200	static struct map_desc exynos4210_iodesc[] __initdata = {
	201	{
	202	.virtual = (unsigned long)S5P_VA_SYSRAM_NS,
	203	.pfn = __phys_to_pfn(EXYNOS4210_PA_SYSRAM_NS),
	204	.length = SZ_4K,
	205	.type = MT_DEVICE,
	206	},
	207	};
	208
	209	static struct map_desc exynos4x12_iodesc[] __initdata = {
	210	{
	211	.virtual = (unsigned long)S5P_VA_SYSRAM_NS,
	212	.pfn = __phys_to_pfn(EXYNOS4x12_PA_SYSRAM_NS),
	213	.length = SZ_4K,
	214	.type = MT_DEVICE,
	215	},
	216	};
	217
	218	static struct map_desc exynos5250_iodesc[] __initdata = {
	219	{
	220	.virtual = (unsigned long)S5P_VA_SYSRAM_NS,
	221	.pfn = __phys_to_pfn(EXYNOS5250_PA_SYSRAM_NS),
	222	.length = SZ_4K,
	223	.type = MT_DEVICE,
	224	},
	225	};
	226
94c7ca71 KK	227	static struct map_desc exynos5_iodesc[] __initdata = {
	228	{
	229	.virtual = (unsigned long)S3C_VA_SYS,
	230	.pfn = __phys_to_pfn(EXYNOS5_PA_SYSCON),
	231	.length = SZ_64K,
	232	.type = MT_DEVICE,
	233	}, {
	234	.virtual = (unsigned long)S3C_VA_TIMER,
	235	.pfn = __phys_to_pfn(EXYNOS5_PA_TIMER),
	236	.length = SZ_16K,
	237	.type = MT_DEVICE,
	238	}, {
	239	.virtual = (unsigned long)S3C_VA_WATCHDOG,
	240	.pfn = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
	241	.length = SZ_4K,
	242	.type = MT_DEVICE,
	243	}, {
	244	.virtual = (unsigned long)S5P_VA_SROMC,
	245	.pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
	246	.length = SZ_4K,
	247	.type = MT_DEVICE,
94c7ca71 KK	248	}, {
	249	.virtual = (unsigned long)S5P_VA_SYSRAM,
	250	.pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
	251	.length = SZ_4K,
	252	.type = MT_DEVICE,
	253	}, {
	254	.virtual = (unsigned long)S5P_VA_CMU,
	255	.pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
	256	.length = 144 * SZ_1K,
	257	.type = MT_DEVICE,
	258	}, {
	259	.virtual = (unsigned long)S5P_VA_PMU,
	260	.pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
	261	.length = SZ_64K,
	262	.type = MT_DEVICE,
2edb36c4 KK	263	},
	264	};
	265
7b6d864b	266	void exynos4_restart(enum reboot_mode mode, const char *cmd)
cc511b8d KK	267	{
	268	__raw_writel(0x1, S5P_SWRESET);
	269	}
	270
7b6d864b	271	void exynos5_restart(enum reboot_mode mode, const char *cmd)
94c7ca71	272	{
60db7e5f	273	struct device_node *np;
2edb36c4 KK	274	u32 val;
	275	void __iomem *addr;
	276
eff4e7c7 CK	277	val = 0x1;
	278	addr = EXYNOS_SWRESET;
	279
	280	if (of_machine_is_compatible("samsung,exynos5440")) {
1ba830c9	281	u32 status;
60db7e5f	282	np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
1ba830c9 JL	283
	284	addr = of_iomap(np, 0) + 0xbc;
	285	status = __raw_readl(addr);
	286
60db7e5f	287	addr = of_iomap(np, 0) + 0xcc;
1ba830c9 JL	288	val = __raw_readl(addr);
	289
	290	val = (val & 0xffff0000) \| (status & 0xffff);
2edb36c4 KK	291	}
	292
	293	__raw_writel(val, addr);
94c7ca71 KK	294	}
94c7ca71 KK	295
35baa336 BZ	296	static struct platform_device exynos_cpuidle = {
	297	.name = "exynos_cpuidle",
	298	.id = -1,
	299	};
	300
	301	void __init exynos_cpuidle_init(void)
	302	{
	303	platform_device_register(&exynos_cpuidle);
	304	}
	305
d568b6f7 LM	306	void __init exynos_cpufreq_init(void)
	307	{
	308	platform_device_register_simple("exynos-cpufreq", -1, NULL, 0);
	309	}
	310
bb13fabc SG	311	void __init exynos_init_late(void)
bb13fabc SG	312	{
2edb36c4 KK	313	if (of_machine_is_compatible("samsung,exynos5440"))
	314	/* to be supported later */
	315	return;
	316
1fd3cbcc	317	pm_genpd_poweroff_unused();
bb13fabc SG	318	}
bb13fabc SG	319
564d06b1	320	static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
f5f83c71 TA	321	int depth, void *data)
	322	{
	323	struct map_desc iodesc;
	324	__be32 *reg;
	325	unsigned long len;
	326
	327	if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid") &&
	328	!of_flat_dt_is_compatible(node, "samsung,exynos5440-clock"))
	329	return 0;
	330
	331	reg = of_get_flat_dt_prop(node, "reg", &len);
	332	if (reg == NULL \|\| len != (sizeof(unsigned long) * 2))
	333	return 0;
	334
	335	iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
	336	iodesc.length = be32_to_cpu(reg[1]) - 1;
	337	iodesc.virtual = (unsigned long)S5P_VA_CHIPID;
	338	iodesc.type = MT_DEVICE;
	339	iotable_init(&iodesc, 1);
	340	return 1;
	341	}
f5f83c71	342
cc511b8d KK	343	/*
	344	* exynos_map_io
	345	*
	346	* register the standard cpu IO areas
	347	*/
	348
0e2238ec	349	void __init exynos_init_io(void)
cc511b8d	350	{
9c1fcdcc DA	351	debug_ll_io_init();
9c1fcdcc DA	352
04fae596	353	of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
2edb36c4	354
cc511b8d KK	355	/* detect cpu id and rev. */
	356	s5p_init_cpu(S5P_VA_CHIPID);
	357
	358	s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
	359	}
	360
906c789c	361	static void __init exynos4_map_io(void)
cc511b8d KK	362	{
	363	iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
	364
	365	if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
	366	iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
	367	else
	368	iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
	369
41de8986 TF	370	if (soc_is_exynos4210())
	371	iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
	372	if (soc_is_exynos4212() \|\| soc_is_exynos4412())
	373	iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
cc511b8d KK	374	}
cc511b8d KK	375
94c7ca71 KK	376	static void __init exynos5_map_io(void)
	377	{
	378	iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
41de8986 TF	379
	380	if (soc_is_exynos5250())
	381	iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
94c7ca71 KK	382	}
94c7ca71 KK	383
9ee6af9c TA	384	struct bus_type exynos_subsys = {
	385	.name = "exynos-core",
	386	.dev_name = "exynos-core",
94c7ca71 KK	387	};
94c7ca71 KK	388
7affca35	389	static struct device exynos4_dev = {
9ee6af9c	390	.bus = &exynos_subsys,
94c7ca71 KK	391	};
	392
	393	static int __init exynos_core_init(void)
cc511b8d	394	{
9ee6af9c	395	return subsys_system_register(&exynos_subsys, NULL);
cc511b8d	396	}
94c7ca71	397	core_initcall(exynos_core_init);
cc511b8d	398
cc511b8d KK	399	static int __init exynos4_l2x0_cache_init(void)
cc511b8d KK	400	{
e1b1994e IH	401	int ret;
e1b1994e IH	402
6cdeddcc	403	ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
87107d89 AB	404	if (ret)
87107d89 AB	405	return ret;
cc511b8d	406
87107d89 AB	407	l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
87107d89 AB	408	clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
cc511b8d KK	409	return 0;
cc511b8d KK	410	}
cc511b8d	411	early_initcall(exynos4_l2x0_cache_init);
cc511b8d	412
906c789c	413	static int __init exynos_init(void)
cc511b8d KK	414	{
cc511b8d KK	415	printk(KERN_INFO "EXYNOS: Initializing architecture\n");
94c7ca71	416
9ee6af9c	417	return device_register(&exynos4_dev);
cc511b8d	418	}