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347863d4 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
cc511b8d KK |
2 | /* |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com | |
5 | * | |
6 | * Common Header for EXYNOS machines | |
cc511b8d KK |
7 | */ |
8 | ||
9 | #ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H | |
10 | #define __ARCH_ARM_MACH_EXYNOS_COMMON_H | |
11 | ||
712eddf7 | 12 | #include <linux/platform_data/cpuidle-exynos.h> |
6e6aac75 | 13 | |
940bc58d CC |
14 | #define EXYNOS3250_SOC_ID 0xE3472000 |
15 | #define EXYNOS3_SOC_MASK 0xFFFFF000 | |
16 | ||
7cb2ded1 | 17 | #define EXYNOS4210_CPU_ID 0x43210000 |
7cb2ded1 SK |
18 | #define EXYNOS4412_CPU_ID 0xE4412200 |
19 | #define EXYNOS4_CPU_MASK 0xFFFE0000 | |
20 | ||
21 | #define EXYNOS5250_SOC_ID 0x43520000 | |
723c9c7e | 22 | #define EXYNOS5410_SOC_ID 0xE5410000 |
7cb2ded1 | 23 | #define EXYNOS5420_SOC_ID 0xE5420000 |
86c6f148 | 24 | #define EXYNOS5800_SOC_ID 0xE5422000 |
7cb2ded1 SK |
25 | #define EXYNOS5_SOC_MASK 0xFFFFF000 |
26 | ||
27 | extern unsigned long samsung_cpu_id; | |
28 | ||
29 | #define IS_SAMSUNG_CPU(name, id, mask) \ | |
30 | static inline int is_samsung_##name(void) \ | |
31 | { \ | |
32 | return ((samsung_cpu_id & mask) == (id & mask)); \ | |
33 | } | |
34 | ||
940bc58d | 35 | IS_SAMSUNG_CPU(exynos3250, EXYNOS3250_SOC_ID, EXYNOS3_SOC_MASK) |
7cb2ded1 | 36 | IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK) |
7cb2ded1 SK |
37 | IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK) |
38 | IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) | |
723c9c7e | 39 | IS_SAMSUNG_CPU(exynos5410, EXYNOS5410_SOC_ID, EXYNOS5_SOC_MASK) |
7cb2ded1 | 40 | IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK) |
86c6f148 | 41 | IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK) |
7cb2ded1 | 42 | |
940bc58d CC |
43 | #if defined(CONFIG_SOC_EXYNOS3250) |
44 | # define soc_is_exynos3250() is_samsung_exynos3250() | |
45 | #else | |
46 | # define soc_is_exynos3250() 0 | |
47 | #endif | |
48 | ||
7cb2ded1 SK |
49 | #if defined(CONFIG_CPU_EXYNOS4210) |
50 | # define soc_is_exynos4210() is_samsung_exynos4210() | |
51 | #else | |
52 | # define soc_is_exynos4210() 0 | |
53 | #endif | |
54 | ||
7cb2ded1 SK |
55 | #if defined(CONFIG_SOC_EXYNOS4412) |
56 | # define soc_is_exynos4412() is_samsung_exynos4412() | |
57 | #else | |
58 | # define soc_is_exynos4412() 0 | |
59 | #endif | |
60 | ||
61 | #define EXYNOS4210_REV_0 (0x0) | |
62 | #define EXYNOS4210_REV_1_0 (0x10) | |
63 | #define EXYNOS4210_REV_1_1 (0x11) | |
64 | ||
65 | #if defined(CONFIG_SOC_EXYNOS5250) | |
66 | # define soc_is_exynos5250() is_samsung_exynos5250() | |
67 | #else | |
68 | # define soc_is_exynos5250() 0 | |
69 | #endif | |
70 | ||
723c9c7e TD |
71 | #if defined(CONFIG_SOC_EXYNOS5410) |
72 | # define soc_is_exynos5410() is_samsung_exynos5410() | |
73 | #else | |
74 | # define soc_is_exynos5410() 0 | |
75 | #endif | |
76 | ||
7cb2ded1 SK |
77 | #if defined(CONFIG_SOC_EXYNOS5420) |
78 | # define soc_is_exynos5420() is_samsung_exynos5420() | |
79 | #else | |
80 | # define soc_is_exynos5420() 0 | |
81 | #endif | |
82 | ||
86c6f148 AK |
83 | #if defined(CONFIG_SOC_EXYNOS5800) |
84 | # define soc_is_exynos5800() is_samsung_exynos5800() | |
85 | #else | |
86 | # define soc_is_exynos5800() 0 | |
87 | #endif | |
88 | ||
2b9d9c32 TF |
89 | extern u32 cp15_save_diag; |
90 | extern u32 cp15_save_power; | |
91 | ||
b3205dea | 92 | extern void __iomem *sysram_ns_base_addr; |
cd245f59 | 93 | extern void __iomem *sysram_base_addr; |
fce9e5bb | 94 | extern void __iomem *pmu_base_addr; |
1754c42e | 95 | void exynos_sysram_init(void); |
bb13fabc | 96 | |
0b7778a8 BZ |
97 | enum { |
98 | FW_DO_IDLE_SLEEP, | |
99 | FW_DO_IDLE_AFTR, | |
100 | }; | |
101 | ||
bca28f8f TF |
102 | void exynos_firmware_init(void); |
103 | ||
dc1b9448 BZ |
104 | /* CPU BOOT mode flag for Exynos3250 SoC bootloader */ |
105 | #define C2_STATE (1 << 3) | |
054e6aa1 KK |
106 | /* |
107 | * Magic values for bootloader indicating chosen low power mode. | |
108 | * See also Documentation/arm/Samsung/Bootloader-interface.txt | |
109 | */ | |
110 | #define EXYNOS_SLEEP_MAGIC 0x00000bad | |
111 | #define EXYNOS_AFTR_MAGIC 0xfcba0d10 | |
dc1b9448 BZ |
112 | |
113 | void exynos_set_boot_flag(unsigned int cpu, unsigned int mode); | |
114 | void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode); | |
115 | ||
d710aa31 | 116 | extern u32 exynos_get_eint_wake_mask(void); |
d710aa31 | 117 | |
559ba237 TF |
118 | #ifdef CONFIG_PM_SLEEP |
119 | extern void __init exynos_pm_init(void); | |
120 | #else | |
121 | static inline void exynos_pm_init(void) {} | |
122 | #endif | |
123 | ||
d710aa31 | 124 | extern void exynos_cpu_resume(void); |
2b9d9c32 | 125 | extern void exynos_cpu_resume_ns(void); |
d710aa31 | 126 | |
75305275 | 127 | extern const struct smp_operations exynos_smp_ops; |
06853ae4 | 128 | |
d3af6976 LKA |
129 | extern void exynos_cpu_power_down(int cpu); |
130 | extern void exynos_cpu_power_up(int cpu); | |
131 | extern int exynos_cpu_power_state(int cpu); | |
096d21c6 AK |
132 | extern void exynos_cluster_power_down(int cluster); |
133 | extern void exynos_cluster_power_up(int cluster); | |
134 | extern int exynos_cluster_power_state(int cluster); | |
0d713cf1 BZ |
135 | extern void exynos_cpu_save_register(void); |
136 | extern void exynos_cpu_restore_register(void); | |
137 | extern void exynos_pm_central_suspend(void); | |
138 | extern int exynos_pm_central_resume(void); | |
3681bafe | 139 | extern void exynos_enter_aftr(void); |
3c33710b PD |
140 | #ifdef CONFIG_SMP |
141 | extern void exynos_scu_enable(void); | |
142 | #else | |
143 | static inline void exynos_scu_enable(void) { } | |
144 | #endif | |
ccd458c1 | 145 | |
712eddf7 BZ |
146 | extern struct cpuidle_exynos_data cpuidle_coupled_exynos_data; |
147 | ||
6f024978 KK |
148 | extern void exynos_set_delayed_reset_assertion(bool enable); |
149 | ||
7cb2ded1 | 150 | extern unsigned int samsung_rev(void); |
af997114 BZ |
151 | extern void exynos_core_restart(u32 core_id); |
152 | extern int exynos_set_boot_addr(u32 core_id, unsigned long boot_addr); | |
153 | extern int exynos_get_boot_addr(u32 core_id, unsigned long *boot_addr); | |
7cb2ded1 | 154 | |
2e94ac42 PD |
155 | static inline void pmu_raw_writel(u32 val, u32 offset) |
156 | { | |
d0ceee0b | 157 | writel_relaxed(val, pmu_base_addr + offset); |
2e94ac42 PD |
158 | } |
159 | ||
160 | static inline u32 pmu_raw_readl(u32 offset) | |
161 | { | |
d0ceee0b | 162 | return readl_relaxed(pmu_base_addr + offset); |
2e94ac42 PD |
163 | } |
164 | ||
cc511b8d | 165 | #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */ |