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7d30e8b3 KK |
1 | /* linux/arch/arm/mach-exynos4/dma.c |
2 | * | |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com | |
5 | * | |
8b0ae0b7 JB |
6 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. |
7 | * Jaswinder Singh <jassi.brar@samsung.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
22 | */ | |
23 | ||
8b0ae0b7 | 24 | #include <linux/dma-mapping.h> |
bf856fbb BK |
25 | #include <linux/amba/bus.h> |
26 | #include <linux/amba/pl330.h> | |
fca3de6a | 27 | #include <linux/of.h> |
8b0ae0b7 | 28 | |
bf856fbb | 29 | #include <asm/irq.h> |
8b0ae0b7 JB |
30 | #include <plat/devs.h> |
31 | #include <plat/irqs.h> | |
efd9960b | 32 | #include <plat/cpu.h> |
8b0ae0b7 JB |
33 | |
34 | #include <mach/map.h> | |
35 | #include <mach/irqs.h> | |
bf856fbb | 36 | #include <mach/dma.h> |
8b0ae0b7 | 37 | |
efd9960b | 38 | static u8 exynos4210_pdma0_peri[] = { |
e1cd8454 TA |
39 | DMACH_PCM0_RX, |
40 | DMACH_PCM0_TX, | |
41 | DMACH_PCM2_RX, | |
42 | DMACH_PCM2_TX, | |
43 | DMACH_MSM_REQ0, | |
44 | DMACH_MSM_REQ2, | |
45 | DMACH_SPI0_RX, | |
46 | DMACH_SPI0_TX, | |
47 | DMACH_SPI2_RX, | |
48 | DMACH_SPI2_TX, | |
49 | DMACH_I2S0S_TX, | |
50 | DMACH_I2S0_RX, | |
51 | DMACH_I2S0_TX, | |
52 | DMACH_I2S2_RX, | |
53 | DMACH_I2S2_TX, | |
54 | DMACH_UART0_RX, | |
55 | DMACH_UART0_TX, | |
56 | DMACH_UART2_RX, | |
57 | DMACH_UART2_TX, | |
58 | DMACH_UART4_RX, | |
59 | DMACH_UART4_TX, | |
60 | DMACH_SLIMBUS0_RX, | |
61 | DMACH_SLIMBUS0_TX, | |
62 | DMACH_SLIMBUS2_RX, | |
63 | DMACH_SLIMBUS2_TX, | |
64 | DMACH_SLIMBUS4_RX, | |
65 | DMACH_SLIMBUS4_TX, | |
66 | DMACH_AC97_MICIN, | |
67 | DMACH_AC97_PCMIN, | |
68 | DMACH_AC97_PCMOUT, | |
8b0ae0b7 JB |
69 | }; |
70 | ||
efd9960b BK |
71 | static u8 exynos4212_pdma0_peri[] = { |
72 | DMACH_PCM0_RX, | |
73 | DMACH_PCM0_TX, | |
74 | DMACH_PCM2_RX, | |
75 | DMACH_PCM2_TX, | |
76 | DMACH_MIPI_HSI0, | |
77 | DMACH_MIPI_HSI1, | |
78 | DMACH_SPI0_RX, | |
79 | DMACH_SPI0_TX, | |
80 | DMACH_SPI2_RX, | |
81 | DMACH_SPI2_TX, | |
82 | DMACH_I2S0S_TX, | |
83 | DMACH_I2S0_RX, | |
84 | DMACH_I2S0_TX, | |
85 | DMACH_I2S2_RX, | |
86 | DMACH_I2S2_TX, | |
87 | DMACH_UART0_RX, | |
88 | DMACH_UART0_TX, | |
89 | DMACH_UART2_RX, | |
90 | DMACH_UART2_TX, | |
91 | DMACH_UART4_RX, | |
92 | DMACH_UART4_TX, | |
93 | DMACH_SLIMBUS0_RX, | |
94 | DMACH_SLIMBUS0_TX, | |
95 | DMACH_SLIMBUS2_RX, | |
96 | DMACH_SLIMBUS2_TX, | |
97 | DMACH_SLIMBUS4_RX, | |
98 | DMACH_SLIMBUS4_TX, | |
99 | DMACH_AC97_MICIN, | |
100 | DMACH_AC97_PCMIN, | |
101 | DMACH_AC97_PCMOUT, | |
102 | DMACH_MIPI_HSI4, | |
103 | DMACH_MIPI_HSI5, | |
8b0ae0b7 JB |
104 | }; |
105 | ||
20ef9e08 BK |
106 | static u8 exynos5250_pdma0_peri[] = { |
107 | DMACH_PCM0_RX, | |
108 | DMACH_PCM0_TX, | |
109 | DMACH_PCM2_RX, | |
110 | DMACH_PCM2_TX, | |
111 | DMACH_SPI0_RX, | |
112 | DMACH_SPI0_TX, | |
113 | DMACH_SPI2_RX, | |
114 | DMACH_SPI2_TX, | |
115 | DMACH_I2S0S_TX, | |
116 | DMACH_I2S0_RX, | |
117 | DMACH_I2S0_TX, | |
118 | DMACH_I2S2_RX, | |
119 | DMACH_I2S2_TX, | |
120 | DMACH_UART0_RX, | |
121 | DMACH_UART0_TX, | |
122 | DMACH_UART2_RX, | |
123 | DMACH_UART2_TX, | |
124 | DMACH_UART4_RX, | |
125 | DMACH_UART4_TX, | |
126 | DMACH_SLIMBUS0_RX, | |
127 | DMACH_SLIMBUS0_TX, | |
128 | DMACH_SLIMBUS2_RX, | |
129 | DMACH_SLIMBUS2_TX, | |
130 | DMACH_SLIMBUS4_RX, | |
131 | DMACH_SLIMBUS4_TX, | |
132 | DMACH_AC97_MICIN, | |
133 | DMACH_AC97_PCMIN, | |
134 | DMACH_AC97_PCMOUT, | |
135 | DMACH_MIPI_HSI0, | |
136 | DMACH_MIPI_HSI2, | |
137 | DMACH_MIPI_HSI4, | |
138 | DMACH_MIPI_HSI6, | |
139 | }; | |
140 | ||
141 | static struct dma_pl330_platdata exynos_pdma0_pdata; | |
efd9960b | 142 | |
20ef9e08 BK |
143 | static AMBA_AHB_DEVICE(exynos_pdma0, "dma-pl330.0", 0x00041330, |
144 | EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos_pdma0_pdata); | |
8b0ae0b7 | 145 | |
efd9960b | 146 | static u8 exynos4210_pdma1_peri[] = { |
e1cd8454 TA |
147 | DMACH_PCM0_RX, |
148 | DMACH_PCM0_TX, | |
149 | DMACH_PCM1_RX, | |
150 | DMACH_PCM1_TX, | |
151 | DMACH_MSM_REQ1, | |
152 | DMACH_MSM_REQ3, | |
153 | DMACH_SPI1_RX, | |
154 | DMACH_SPI1_TX, | |
155 | DMACH_I2S0S_TX, | |
156 | DMACH_I2S0_RX, | |
157 | DMACH_I2S0_TX, | |
158 | DMACH_I2S1_RX, | |
159 | DMACH_I2S1_TX, | |
160 | DMACH_UART0_RX, | |
161 | DMACH_UART0_TX, | |
162 | DMACH_UART1_RX, | |
163 | DMACH_UART1_TX, | |
164 | DMACH_UART3_RX, | |
165 | DMACH_UART3_TX, | |
166 | DMACH_SLIMBUS1_RX, | |
167 | DMACH_SLIMBUS1_TX, | |
168 | DMACH_SLIMBUS3_RX, | |
169 | DMACH_SLIMBUS3_TX, | |
170 | DMACH_SLIMBUS5_RX, | |
171 | DMACH_SLIMBUS5_TX, | |
8b0ae0b7 JB |
172 | }; |
173 | ||
efd9960b BK |
174 | static u8 exynos4212_pdma1_peri[] = { |
175 | DMACH_PCM0_RX, | |
176 | DMACH_PCM0_TX, | |
177 | DMACH_PCM1_RX, | |
178 | DMACH_PCM1_TX, | |
179 | DMACH_MIPI_HSI2, | |
180 | DMACH_MIPI_HSI3, | |
181 | DMACH_SPI1_RX, | |
182 | DMACH_SPI1_TX, | |
183 | DMACH_I2S0S_TX, | |
184 | DMACH_I2S0_RX, | |
185 | DMACH_I2S0_TX, | |
186 | DMACH_I2S1_RX, | |
187 | DMACH_I2S1_TX, | |
188 | DMACH_UART0_RX, | |
189 | DMACH_UART0_TX, | |
190 | DMACH_UART1_RX, | |
191 | DMACH_UART1_TX, | |
192 | DMACH_UART3_RX, | |
193 | DMACH_UART3_TX, | |
194 | DMACH_SLIMBUS1_RX, | |
195 | DMACH_SLIMBUS1_TX, | |
196 | DMACH_SLIMBUS3_RX, | |
197 | DMACH_SLIMBUS3_TX, | |
198 | DMACH_SLIMBUS5_RX, | |
199 | DMACH_SLIMBUS5_TX, | |
200 | DMACH_SLIMBUS0AUX_RX, | |
201 | DMACH_SLIMBUS0AUX_TX, | |
202 | DMACH_SPDIF, | |
203 | DMACH_MIPI_HSI6, | |
204 | DMACH_MIPI_HSI7, | |
8b0ae0b7 JB |
205 | }; |
206 | ||
20ef9e08 BK |
207 | static u8 exynos5250_pdma1_peri[] = { |
208 | DMACH_PCM0_RX, | |
209 | DMACH_PCM0_TX, | |
210 | DMACH_PCM1_RX, | |
211 | DMACH_PCM1_TX, | |
212 | DMACH_SPI1_RX, | |
213 | DMACH_SPI1_TX, | |
214 | DMACH_PWM, | |
215 | DMACH_SPDIF, | |
216 | DMACH_I2S0S_TX, | |
217 | DMACH_I2S0_RX, | |
218 | DMACH_I2S0_TX, | |
219 | DMACH_I2S1_RX, | |
220 | DMACH_I2S1_TX, | |
221 | DMACH_UART0_RX, | |
222 | DMACH_UART0_TX, | |
223 | DMACH_UART1_RX, | |
224 | DMACH_UART1_TX, | |
225 | DMACH_UART3_RX, | |
226 | DMACH_UART3_TX, | |
227 | DMACH_SLIMBUS1_RX, | |
228 | DMACH_SLIMBUS1_TX, | |
229 | DMACH_SLIMBUS3_RX, | |
230 | DMACH_SLIMBUS3_TX, | |
231 | DMACH_SLIMBUS5_RX, | |
232 | DMACH_SLIMBUS5_TX, | |
233 | DMACH_SLIMBUS0AUX_RX, | |
234 | DMACH_SLIMBUS0AUX_TX, | |
235 | DMACH_DISP1, | |
236 | DMACH_MIPI_HSI1, | |
237 | DMACH_MIPI_HSI3, | |
238 | DMACH_MIPI_HSI5, | |
239 | DMACH_MIPI_HSI7, | |
240 | }; | |
efd9960b | 241 | |
20ef9e08 BK |
242 | static struct dma_pl330_platdata exynos_pdma1_pdata; |
243 | ||
244 | static AMBA_AHB_DEVICE(exynos_pdma1, "dma-pl330.1", 0x00041330, | |
245 | EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos_pdma1_pdata); | |
8b0ae0b7 | 246 | |
9ed76e03 BK |
247 | static u8 mdma_peri[] = { |
248 | DMACH_MTOM_0, | |
249 | DMACH_MTOM_1, | |
250 | DMACH_MTOM_2, | |
251 | DMACH_MTOM_3, | |
252 | DMACH_MTOM_4, | |
253 | DMACH_MTOM_5, | |
254 | DMACH_MTOM_6, | |
255 | DMACH_MTOM_7, | |
256 | }; | |
257 | ||
20ef9e08 | 258 | static struct dma_pl330_platdata exynos_mdma1_pdata = { |
9ed76e03 BK |
259 | .nr_valid_peri = ARRAY_SIZE(mdma_peri), |
260 | .peri_id = mdma_peri, | |
261 | }; | |
262 | ||
20ef9e08 BK |
263 | static AMBA_AHB_DEVICE(exynos_mdma1, "dma-pl330.2", 0x00041330, |
264 | EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos_mdma1_pdata); | |
9ed76e03 | 265 | |
20ef9e08 | 266 | static int __init exynos_dma_init(void) |
8b0ae0b7 | 267 | { |
fca3de6a TA |
268 | if (of_have_populated_dt()) |
269 | return 0; | |
270 | ||
efd9960b | 271 | if (soc_is_exynos4210()) { |
20ef9e08 | 272 | exynos_pdma0_pdata.nr_valid_peri = |
efd9960b | 273 | ARRAY_SIZE(exynos4210_pdma0_peri); |
20ef9e08 BK |
274 | exynos_pdma0_pdata.peri_id = exynos4210_pdma0_peri; |
275 | exynos_pdma1_pdata.nr_valid_peri = | |
efd9960b | 276 | ARRAY_SIZE(exynos4210_pdma1_peri); |
20ef9e08 | 277 | exynos_pdma1_pdata.peri_id = exynos4210_pdma1_peri; |
91280e75 BZ |
278 | |
279 | if (samsung_rev() == EXYNOS4210_REV_0) | |
280 | exynos_mdma1_device.res.start = EXYNOS4_PA_S_MDMA1; | |
efd9960b | 281 | } else if (soc_is_exynos4212() || soc_is_exynos4412()) { |
20ef9e08 | 282 | exynos_pdma0_pdata.nr_valid_peri = |
efd9960b | 283 | ARRAY_SIZE(exynos4212_pdma0_peri); |
20ef9e08 BK |
284 | exynos_pdma0_pdata.peri_id = exynos4212_pdma0_peri; |
285 | exynos_pdma1_pdata.nr_valid_peri = | |
efd9960b | 286 | ARRAY_SIZE(exynos4212_pdma1_peri); |
20ef9e08 BK |
287 | exynos_pdma1_pdata.peri_id = exynos4212_pdma1_peri; |
288 | } else if (soc_is_exynos5250()) { | |
289 | exynos_pdma0_pdata.nr_valid_peri = | |
290 | ARRAY_SIZE(exynos5250_pdma0_peri); | |
291 | exynos_pdma0_pdata.peri_id = exynos5250_pdma0_peri; | |
292 | exynos_pdma1_pdata.nr_valid_peri = | |
293 | ARRAY_SIZE(exynos5250_pdma1_peri); | |
294 | exynos_pdma1_pdata.peri_id = exynos5250_pdma1_peri; | |
295 | ||
296 | exynos_pdma0_device.res.start = EXYNOS5_PA_PDMA0; | |
297 | exynos_pdma0_device.res.end = EXYNOS5_PA_PDMA0 + SZ_4K; | |
298 | exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA0; | |
299 | exynos_pdma1_device.res.start = EXYNOS5_PA_PDMA1; | |
300 | exynos_pdma1_device.res.end = EXYNOS5_PA_PDMA1 + SZ_4K; | |
301 | exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA1; | |
302 | exynos_mdma1_device.res.start = EXYNOS5_PA_MDMA1; | |
303 | exynos_mdma1_device.res.end = EXYNOS5_PA_MDMA1 + SZ_4K; | |
304 | exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_MDMA1; | |
efd9960b BK |
305 | } |
306 | ||
20ef9e08 BK |
307 | dma_cap_set(DMA_SLAVE, exynos_pdma0_pdata.cap_mask); |
308 | dma_cap_set(DMA_CYCLIC, exynos_pdma0_pdata.cap_mask); | |
7fc7bf08 | 309 | dma_cap_set(DMA_PRIVATE, exynos_pdma0_pdata.cap_mask); |
20ef9e08 | 310 | amba_device_register(&exynos_pdma0_device, &iomem_resource); |
e1cd8454 | 311 | |
20ef9e08 BK |
312 | dma_cap_set(DMA_SLAVE, exynos_pdma1_pdata.cap_mask); |
313 | dma_cap_set(DMA_CYCLIC, exynos_pdma1_pdata.cap_mask); | |
7fc7bf08 | 314 | dma_cap_set(DMA_PRIVATE, exynos_pdma1_pdata.cap_mask); |
20ef9e08 | 315 | amba_device_register(&exynos_pdma1_device, &iomem_resource); |
8b0ae0b7 | 316 | |
20ef9e08 BK |
317 | dma_cap_set(DMA_MEMCPY, exynos_mdma1_pdata.cap_mask); |
318 | amba_device_register(&exynos_mdma1_device, &iomem_resource); | |
9ed76e03 | 319 | |
8b0ae0b7 JB |
320 | return 0; |
321 | } | |
20ef9e08 | 322 | arch_initcall(exynos_dma_init); |