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0d713cf1 BZ |
1 | /* |
2 | * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd. | |
3 | * http://www.samsung.com | |
4 | * | |
5 | * EXYNOS - Suspend support | |
6 | * | |
7 | * Based on arch/arm/mach-s3c2410/pm.c | |
8 | * Copyright (c) 2006 Simtec Electronics | |
9 | * Ben Dooks <ben@simtec.co.uk> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #include <linux/init.h> | |
17 | #include <linux/suspend.h> | |
18 | #include <linux/syscore_ops.h> | |
19 | #include <linux/cpu_pm.h> | |
20 | #include <linux/io.h> | |
8b283c02 MZ |
21 | #include <linux/irq.h> |
22 | #include <linux/irqdomain.h> | |
23 | #include <linux/of_address.h> | |
0d713cf1 | 24 | #include <linux/err.h> |
c645a598 | 25 | #include <linux/regulator/machine.h> |
0d713cf1 BZ |
26 | |
27 | #include <asm/cacheflush.h> | |
28 | #include <asm/hardware/cache-l2x0.h> | |
29 | #include <asm/firmware.h> | |
adc548d7 | 30 | #include <asm/mcpm.h> |
0d713cf1 BZ |
31 | #include <asm/smp_scu.h> |
32 | #include <asm/suspend.h> | |
33 | ||
34 | #include <plat/pm-common.h> | |
35 | #include <plat/regs-srom.h> | |
36 | ||
37 | #include "common.h" | |
38 | #include "regs-pmu.h" | |
6b7bfd82 | 39 | #include "exynos-pmu.h" |
0d713cf1 BZ |
40 | |
41 | #define S5P_CHECK_SLEEP 0x00000BAD | |
42 | ||
43 | #define REG_TABLE_END (-1U) | |
44 | ||
0fdf088f VS |
45 | #define EXYNOS5420_CPU_STATE 0x28 |
46 | ||
0d713cf1 | 47 | /** |
8b283c02 MZ |
48 | * struct exynos_wkup_irq - PMU IRQ to mask mapping |
49 | * @hwirq: Hardware IRQ signal of the PMU | |
0d713cf1 BZ |
50 | * @mask: Mask in PMU wake-up mask register |
51 | */ | |
52 | struct exynos_wkup_irq { | |
53 | unsigned int hwirq; | |
54 | u32 mask; | |
55 | }; | |
56 | ||
0d713cf1 BZ |
57 | static struct sleep_save exynos_core_save[] = { |
58 | /* SROM side */ | |
59 | SAVE_ITEM(S5P_SROM_BW), | |
60 | SAVE_ITEM(S5P_SROM_BC0), | |
61 | SAVE_ITEM(S5P_SROM_BC1), | |
62 | SAVE_ITEM(S5P_SROM_BC2), | |
63 | SAVE_ITEM(S5P_SROM_BC3), | |
64 | }; | |
65 | ||
66 | struct exynos_pm_data { | |
67 | const struct exynos_wkup_irq *wkup_irq; | |
0d713cf1 BZ |
68 | unsigned int wake_disable_mask; |
69 | unsigned int *release_ret_regs; | |
70 | ||
71 | void (*pm_prepare)(void); | |
adc548d7 | 72 | void (*pm_resume_prepare)(void); |
0d713cf1 BZ |
73 | void (*pm_resume)(void); |
74 | int (*pm_suspend)(void); | |
75 | int (*cpu_suspend)(unsigned long); | |
76 | }; | |
77 | ||
1cd3de0a | 78 | static const struct exynos_pm_data *pm_data; |
0d713cf1 | 79 | |
0fdf088f VS |
80 | static int exynos5420_cpu_state; |
81 | static unsigned int exynos_pmu_spare3; | |
82 | ||
0d713cf1 BZ |
83 | /* |
84 | * GIC wake-up support | |
85 | */ | |
86 | ||
87 | static u32 exynos_irqwake_intmask = 0xffffffff; | |
88 | ||
a4f582f5 | 89 | static const struct exynos_wkup_irq exynos3250_wkup_irq[] = { |
ace283a0 CC |
90 | { 105, BIT(1) }, /* RTC alarm */ |
91 | { 106, BIT(2) }, /* RTC tick */ | |
a4f582f5 CC |
92 | { /* sentinel */ }, |
93 | }; | |
94 | ||
0d713cf1 | 95 | static const struct exynos_wkup_irq exynos4_wkup_irq[] = { |
8b283c02 MZ |
96 | { 44, BIT(1) }, /* RTC alarm */ |
97 | { 45, BIT(2) }, /* RTC tick */ | |
0d713cf1 BZ |
98 | { /* sentinel */ }, |
99 | }; | |
100 | ||
101 | static const struct exynos_wkup_irq exynos5250_wkup_irq[] = { | |
8b283c02 MZ |
102 | { 43, BIT(1) }, /* RTC alarm */ |
103 | { 44, BIT(2) }, /* RTC tick */ | |
0d713cf1 BZ |
104 | { /* sentinel */ }, |
105 | }; | |
106 | ||
8c8a2511 | 107 | static unsigned int exynos_release_ret_regs[] = { |
0d713cf1 BZ |
108 | S5P_PAD_RET_MAUDIO_OPTION, |
109 | S5P_PAD_RET_GPIO_OPTION, | |
110 | S5P_PAD_RET_UART_OPTION, | |
111 | S5P_PAD_RET_MMCA_OPTION, | |
112 | S5P_PAD_RET_MMCB_OPTION, | |
113 | S5P_PAD_RET_EBIA_OPTION, | |
114 | S5P_PAD_RET_EBIB_OPTION, | |
115 | REG_TABLE_END, | |
116 | }; | |
117 | ||
8c8a2511 | 118 | static unsigned int exynos3250_release_ret_regs[] = { |
a4f582f5 CC |
119 | S5P_PAD_RET_MAUDIO_OPTION, |
120 | S5P_PAD_RET_GPIO_OPTION, | |
121 | S5P_PAD_RET_UART_OPTION, | |
122 | S5P_PAD_RET_MMCA_OPTION, | |
123 | S5P_PAD_RET_MMCB_OPTION, | |
124 | S5P_PAD_RET_EBIA_OPTION, | |
125 | S5P_PAD_RET_EBIB_OPTION, | |
126 | S5P_PAD_RET_MMC2_OPTION, | |
127 | S5P_PAD_RET_SPI_OPTION, | |
128 | REG_TABLE_END, | |
129 | }; | |
130 | ||
8c8a2511 | 131 | static unsigned int exynos5420_release_ret_regs[] = { |
0fdf088f VS |
132 | EXYNOS_PAD_RET_DRAM_OPTION, |
133 | EXYNOS_PAD_RET_MAUDIO_OPTION, | |
134 | EXYNOS_PAD_RET_JTAG_OPTION, | |
135 | EXYNOS5420_PAD_RET_GPIO_OPTION, | |
136 | EXYNOS5420_PAD_RET_UART_OPTION, | |
137 | EXYNOS5420_PAD_RET_MMCA_OPTION, | |
138 | EXYNOS5420_PAD_RET_MMCB_OPTION, | |
139 | EXYNOS5420_PAD_RET_MMCC_OPTION, | |
140 | EXYNOS5420_PAD_RET_HSI_OPTION, | |
141 | EXYNOS_PAD_RET_EBIA_OPTION, | |
142 | EXYNOS_PAD_RET_EBIB_OPTION, | |
143 | EXYNOS5420_PAD_RET_SPI_OPTION, | |
144 | EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION, | |
145 | REG_TABLE_END, | |
146 | }; | |
147 | ||
0d713cf1 BZ |
148 | static int exynos_irq_set_wake(struct irq_data *data, unsigned int state) |
149 | { | |
150 | const struct exynos_wkup_irq *wkup_irq; | |
151 | ||
152 | if (!pm_data->wkup_irq) | |
153 | return -ENOENT; | |
154 | wkup_irq = pm_data->wkup_irq; | |
155 | ||
156 | while (wkup_irq->mask) { | |
157 | if (wkup_irq->hwirq == data->hwirq) { | |
158 | if (!state) | |
159 | exynos_irqwake_intmask |= wkup_irq->mask; | |
160 | else | |
161 | exynos_irqwake_intmask &= ~wkup_irq->mask; | |
162 | return 0; | |
163 | } | |
164 | ++wkup_irq; | |
165 | } | |
166 | ||
167 | return -ENOENT; | |
168 | } | |
169 | ||
8b283c02 MZ |
170 | static struct irq_chip exynos_pmu_chip = { |
171 | .name = "PMU", | |
172 | .irq_eoi = irq_chip_eoi_parent, | |
173 | .irq_mask = irq_chip_mask_parent, | |
174 | .irq_unmask = irq_chip_unmask_parent, | |
175 | .irq_retrigger = irq_chip_retrigger_hierarchy, | |
176 | .irq_set_wake = exynos_irq_set_wake, | |
177 | #ifdef CONFIG_SMP | |
178 | .irq_set_affinity = irq_chip_set_affinity_parent, | |
179 | #endif | |
180 | }; | |
181 | ||
182 | static int exynos_pmu_domain_xlate(struct irq_domain *domain, | |
183 | struct device_node *controller, | |
184 | const u32 *intspec, | |
185 | unsigned int intsize, | |
186 | unsigned long *out_hwirq, | |
187 | unsigned int *out_type) | |
188 | { | |
189 | if (domain->of_node != controller) | |
190 | return -EINVAL; /* Shouldn't happen, really... */ | |
191 | if (intsize != 3) | |
192 | return -EINVAL; /* Not GIC compliant */ | |
193 | if (intspec[0] != 0) | |
194 | return -EINVAL; /* No PPI should point to this domain */ | |
195 | ||
196 | *out_hwirq = intspec[1]; | |
197 | *out_type = intspec[2]; | |
198 | return 0; | |
199 | } | |
200 | ||
201 | static int exynos_pmu_domain_alloc(struct irq_domain *domain, | |
202 | unsigned int virq, | |
203 | unsigned int nr_irqs, void *data) | |
204 | { | |
205 | struct of_phandle_args *args = data; | |
206 | struct of_phandle_args parent_args; | |
207 | irq_hw_number_t hwirq; | |
208 | int i; | |
209 | ||
210 | if (args->args_count != 3) | |
211 | return -EINVAL; /* Not GIC compliant */ | |
212 | if (args->args[0] != 0) | |
213 | return -EINVAL; /* No PPI should point to this domain */ | |
214 | ||
215 | hwirq = args->args[1]; | |
216 | ||
217 | for (i = 0; i < nr_irqs; i++) | |
218 | irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, | |
219 | &exynos_pmu_chip, NULL); | |
220 | ||
221 | parent_args = *args; | |
222 | parent_args.np = domain->parent->of_node; | |
223 | return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &parent_args); | |
224 | } | |
225 | ||
226 | static struct irq_domain_ops exynos_pmu_domain_ops = { | |
227 | .xlate = exynos_pmu_domain_xlate, | |
228 | .alloc = exynos_pmu_domain_alloc, | |
229 | .free = irq_domain_free_irqs_common, | |
230 | }; | |
231 | ||
232 | static int __init exynos_pmu_irq_init(struct device_node *node, | |
233 | struct device_node *parent) | |
234 | { | |
235 | struct irq_domain *parent_domain, *domain; | |
236 | ||
237 | if (!parent) { | |
238 | pr_err("%s: no parent, giving up\n", node->full_name); | |
239 | return -ENODEV; | |
240 | } | |
241 | ||
242 | parent_domain = irq_find_host(parent); | |
243 | if (!parent_domain) { | |
244 | pr_err("%s: unable to obtain parent domain\n", node->full_name); | |
245 | return -ENXIO; | |
246 | } | |
247 | ||
248 | pmu_base_addr = of_iomap(node, 0); | |
249 | ||
250 | if (!pmu_base_addr) { | |
251 | pr_err("%s: failed to find exynos pmu register\n", | |
252 | node->full_name); | |
253 | return -ENOMEM; | |
254 | } | |
255 | ||
256 | domain = irq_domain_add_hierarchy(parent_domain, 0, 0, | |
257 | node, &exynos_pmu_domain_ops, | |
258 | NULL); | |
259 | if (!domain) { | |
260 | iounmap(pmu_base_addr); | |
261 | return -ENOMEM; | |
262 | } | |
263 | ||
264 | return 0; | |
265 | } | |
266 | ||
267 | #define EXYNOS_PMU_IRQ(symbol, name) OF_DECLARE_2(irqchip, symbol, name, exynos_pmu_irq_init) | |
268 | ||
269 | EXYNOS_PMU_IRQ(exynos3250_pmu_irq, "samsung,exynos3250-pmu"); | |
270 | EXYNOS_PMU_IRQ(exynos4210_pmu_irq, "samsung,exynos4210-pmu"); | |
271 | EXYNOS_PMU_IRQ(exynos4212_pmu_irq, "samsung,exynos4212-pmu"); | |
272 | EXYNOS_PMU_IRQ(exynos4412_pmu_irq, "samsung,exynos4412-pmu"); | |
273 | EXYNOS_PMU_IRQ(exynos4415_pmu_irq, "samsung,exynos4415-pmu"); | |
274 | EXYNOS_PMU_IRQ(exynos5250_pmu_irq, "samsung,exynos5250-pmu"); | |
275 | EXYNOS_PMU_IRQ(exynos5420_pmu_irq, "samsung,exynos5420-pmu"); | |
276 | ||
0d713cf1 BZ |
277 | static int exynos_cpu_do_idle(void) |
278 | { | |
279 | /* issue the standby signal into the pm unit. */ | |
280 | cpu_do_idle(); | |
281 | ||
282 | pr_info("Failed to suspend the system\n"); | |
283 | return 1; /* Aborting suspend */ | |
284 | } | |
0fdf088f | 285 | static void exynos_flush_cache_all(void) |
0d713cf1 BZ |
286 | { |
287 | flush_cache_all(); | |
288 | outer_flush_all(); | |
0fdf088f VS |
289 | } |
290 | ||
291 | static int exynos_cpu_suspend(unsigned long arg) | |
292 | { | |
293 | exynos_flush_cache_all(); | |
294 | return exynos_cpu_do_idle(); | |
295 | } | |
296 | ||
a4f582f5 CC |
297 | static int exynos3250_cpu_suspend(unsigned long arg) |
298 | { | |
299 | flush_cache_all(); | |
300 | return exynos_cpu_do_idle(); | |
301 | } | |
302 | ||
0fdf088f VS |
303 | static int exynos5420_cpu_suspend(unsigned long arg) |
304 | { | |
adc548d7 AK |
305 | /* MCPM works with HW CPU identifiers */ |
306 | unsigned int mpidr = read_cpuid_mpidr(); | |
307 | unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); | |
308 | unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); | |
309 | ||
0fdf088f | 310 | __raw_writel(0x0, sysram_base_addr + EXYNOS5420_CPU_STATE); |
adc548d7 AK |
311 | |
312 | if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) { | |
313 | mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume); | |
314 | ||
315 | /* | |
316 | * Residency value passed to mcpm_cpu_suspend back-end | |
317 | * has to be given clear semantics. Set to 0 as a | |
318 | * temporary value. | |
319 | */ | |
320 | mcpm_cpu_suspend(0); | |
321 | } | |
322 | ||
323 | pr_info("Failed to suspend the system\n"); | |
324 | ||
325 | /* return value != 0 means failure */ | |
326 | return 1; | |
0d713cf1 BZ |
327 | } |
328 | ||
329 | static void exynos_pm_set_wakeup_mask(void) | |
330 | { | |
331 | /* Set wake-up mask registers */ | |
332 | pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK); | |
333 | pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK); | |
334 | } | |
335 | ||
336 | static void exynos_pm_enter_sleep_mode(void) | |
337 | { | |
338 | /* Set value of power down register for sleep mode */ | |
339 | exynos_sys_powerdown_conf(SYS_SLEEP); | |
340 | pmu_raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1); | |
0d713cf1 BZ |
341 | } |
342 | ||
343 | static void exynos_pm_prepare(void) | |
344 | { | |
345 | /* Set wake-up mask registers */ | |
346 | exynos_pm_set_wakeup_mask(); | |
347 | ||
348 | s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save)); | |
349 | ||
0d713cf1 | 350 | exynos_pm_enter_sleep_mode(); |
adc548d7 AK |
351 | |
352 | /* ensure at least INFORM0 has the resume address */ | |
353 | pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0); | |
0d713cf1 BZ |
354 | } |
355 | ||
a4f582f5 CC |
356 | static void exynos3250_pm_prepare(void) |
357 | { | |
358 | unsigned int tmp; | |
359 | ||
360 | /* Set wake-up mask registers */ | |
361 | exynos_pm_set_wakeup_mask(); | |
362 | ||
363 | tmp = pmu_raw_readl(EXYNOS3_ARM_L2_OPTION); | |
364 | tmp &= ~EXYNOS5_OPTION_USE_RETENTION; | |
365 | pmu_raw_writel(tmp, EXYNOS3_ARM_L2_OPTION); | |
366 | ||
367 | exynos_pm_enter_sleep_mode(); | |
368 | ||
369 | /* ensure at least INFORM0 has the resume address */ | |
370 | pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0); | |
371 | } | |
372 | ||
0fdf088f VS |
373 | static void exynos5420_pm_prepare(void) |
374 | { | |
375 | unsigned int tmp; | |
376 | ||
377 | /* Set wake-up mask registers */ | |
378 | exynos_pm_set_wakeup_mask(); | |
379 | ||
380 | s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save)); | |
381 | ||
382 | exynos_pmu_spare3 = pmu_raw_readl(S5P_PMU_SPARE3); | |
383 | /* | |
384 | * The cpu state needs to be saved and restored so that the | |
385 | * secondary CPUs will enter low power start. Though the U-Boot | |
386 | * is setting the cpu state with low power flag, the kernel | |
387 | * needs to restore it back in case, the primary cpu fails to | |
388 | * suspend for any reason. | |
389 | */ | |
390 | exynos5420_cpu_state = __raw_readl(sysram_base_addr + | |
391 | EXYNOS5420_CPU_STATE); | |
392 | ||
393 | exynos_pm_enter_sleep_mode(); | |
394 | ||
adc548d7 AK |
395 | /* ensure at least INFORM0 has the resume address */ |
396 | if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) | |
397 | pmu_raw_writel(virt_to_phys(mcpm_entry_point), S5P_INFORM0); | |
398 | ||
0fdf088f VS |
399 | tmp = pmu_raw_readl(EXYNOS5_ARM_L2_OPTION); |
400 | tmp &= ~EXYNOS5_USE_RETENTION; | |
401 | pmu_raw_writel(tmp, EXYNOS5_ARM_L2_OPTION); | |
402 | ||
403 | tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1); | |
404 | tmp |= EXYNOS5420_UFS; | |
405 | pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1); | |
406 | ||
407 | tmp = pmu_raw_readl(EXYNOS5420_ARM_COMMON_OPTION); | |
408 | tmp &= ~EXYNOS5420_L2RSTDISABLE_VALUE; | |
409 | pmu_raw_writel(tmp, EXYNOS5420_ARM_COMMON_OPTION); | |
410 | ||
411 | tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION); | |
412 | tmp |= EXYNOS5420_EMULATION; | |
413 | pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION); | |
414 | ||
415 | tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION); | |
416 | tmp |= EXYNOS5420_EMULATION; | |
417 | pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION); | |
418 | } | |
419 | ||
420 | ||
0d713cf1 BZ |
421 | static int exynos_pm_suspend(void) |
422 | { | |
423 | exynos_pm_central_suspend(); | |
424 | ||
865e8b76 BZ |
425 | /* Setting SEQ_OPTION register */ |
426 | pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0, | |
427 | S5P_CENTRAL_SEQ_OPTION); | |
428 | ||
0d713cf1 BZ |
429 | if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) |
430 | exynos_cpu_save_register(); | |
431 | ||
432 | return 0; | |
433 | } | |
434 | ||
0fdf088f VS |
435 | static int exynos5420_pm_suspend(void) |
436 | { | |
437 | u32 this_cluster; | |
438 | ||
439 | exynos_pm_central_suspend(); | |
440 | ||
441 | /* Setting SEQ_OPTION register */ | |
442 | ||
443 | this_cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1); | |
444 | if (!this_cluster) | |
445 | pmu_raw_writel(EXYNOS5420_ARM_USE_STANDBY_WFI0, | |
446 | S5P_CENTRAL_SEQ_OPTION); | |
447 | else | |
448 | pmu_raw_writel(EXYNOS5420_KFC_USE_STANDBY_WFI0, | |
449 | S5P_CENTRAL_SEQ_OPTION); | |
450 | return 0; | |
451 | } | |
452 | ||
0d713cf1 BZ |
453 | static void exynos_pm_release_retention(void) |
454 | { | |
455 | unsigned int i; | |
456 | ||
457 | for (i = 0; (pm_data->release_ret_regs[i] != REG_TABLE_END); i++) | |
458 | pmu_raw_writel(EXYNOS_WAKEUP_FROM_LOWPWR, | |
459 | pm_data->release_ret_regs[i]); | |
460 | } | |
461 | ||
462 | static void exynos_pm_resume(void) | |
463 | { | |
464 | u32 cpuid = read_cpuid_part(); | |
465 | ||
466 | if (exynos_pm_central_resume()) | |
467 | goto early_wakeup; | |
468 | ||
469 | /* For release retention */ | |
470 | exynos_pm_release_retention(); | |
471 | ||
0d713cf1 BZ |
472 | s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save)); |
473 | ||
474 | if (cpuid == ARM_CPU_PART_CORTEX_A9) | |
475 | scu_enable(S5P_VA_SCU); | |
476 | ||
477 | if (call_firmware_op(resume) == -ENOSYS | |
478 | && cpuid == ARM_CPU_PART_CORTEX_A9) | |
479 | exynos_cpu_restore_register(); | |
480 | ||
481 | early_wakeup: | |
482 | ||
483 | /* Clear SLEEP mode set in INFORM1 */ | |
484 | pmu_raw_writel(0x0, S5P_INFORM1); | |
485 | } | |
486 | ||
a4f582f5 CC |
487 | static void exynos3250_pm_resume(void) |
488 | { | |
489 | u32 cpuid = read_cpuid_part(); | |
490 | ||
491 | if (exynos_pm_central_resume()) | |
492 | goto early_wakeup; | |
493 | ||
494 | /* For release retention */ | |
495 | exynos_pm_release_retention(); | |
496 | ||
497 | pmu_raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION); | |
498 | ||
499 | if (call_firmware_op(resume) == -ENOSYS | |
500 | && cpuid == ARM_CPU_PART_CORTEX_A9) | |
501 | exynos_cpu_restore_register(); | |
502 | ||
503 | early_wakeup: | |
504 | ||
505 | /* Clear SLEEP mode set in INFORM1 */ | |
506 | pmu_raw_writel(0x0, S5P_INFORM1); | |
507 | } | |
508 | ||
adc548d7 AK |
509 | static void exynos5420_prepare_pm_resume(void) |
510 | { | |
511 | if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) | |
512 | WARN_ON(mcpm_cpu_powered_up()); | |
513 | } | |
514 | ||
0fdf088f VS |
515 | static void exynos5420_pm_resume(void) |
516 | { | |
517 | unsigned long tmp; | |
518 | ||
adc548d7 AK |
519 | /* Restore the CPU0 low power state register */ |
520 | tmp = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG); | |
521 | pmu_raw_writel(tmp | S5P_CORE_LOCAL_PWR_EN, | |
522 | EXYNOS5_ARM_CORE0_SYS_PWR_REG); | |
523 | ||
0fdf088f VS |
524 | /* Restore the sysram cpu state register */ |
525 | __raw_writel(exynos5420_cpu_state, | |
526 | sysram_base_addr + EXYNOS5420_CPU_STATE); | |
527 | ||
528 | pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL, | |
529 | S5P_CENTRAL_SEQ_OPTION); | |
530 | ||
531 | if (exynos_pm_central_resume()) | |
532 | goto early_wakeup; | |
533 | ||
534 | /* For release retention */ | |
535 | exynos_pm_release_retention(); | |
536 | ||
537 | pmu_raw_writel(exynos_pmu_spare3, S5P_PMU_SPARE3); | |
538 | ||
539 | s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save)); | |
540 | ||
541 | early_wakeup: | |
542 | ||
543 | tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1); | |
544 | tmp &= ~EXYNOS5420_UFS; | |
545 | pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1); | |
546 | ||
547 | tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION); | |
548 | tmp &= ~EXYNOS5420_EMULATION; | |
549 | pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION); | |
550 | ||
551 | tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION); | |
552 | tmp &= ~EXYNOS5420_EMULATION; | |
553 | pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION); | |
554 | ||
555 | /* Clear SLEEP mode set in INFORM1 */ | |
556 | pmu_raw_writel(0x0, S5P_INFORM1); | |
557 | } | |
558 | ||
0d713cf1 BZ |
559 | /* |
560 | * Suspend Ops | |
561 | */ | |
562 | ||
563 | static int exynos_suspend_enter(suspend_state_t state) | |
564 | { | |
565 | int ret; | |
566 | ||
567 | s3c_pm_debug_init(); | |
568 | ||
569 | S3C_PMDBG("%s: suspending the system...\n", __func__); | |
570 | ||
571 | S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__, | |
572 | exynos_irqwake_intmask, exynos_get_eint_wake_mask()); | |
573 | ||
574 | if (exynos_irqwake_intmask == -1U | |
575 | && exynos_get_eint_wake_mask() == -1U) { | |
576 | pr_err("%s: No wake-up sources!\n", __func__); | |
577 | pr_err("%s: Aborting sleep\n", __func__); | |
578 | return -EINVAL; | |
579 | } | |
580 | ||
581 | s3c_pm_save_uarts(); | |
582 | if (pm_data->pm_prepare) | |
583 | pm_data->pm_prepare(); | |
584 | flush_cache_all(); | |
585 | s3c_pm_check_store(); | |
586 | ||
587 | ret = call_firmware_op(suspend); | |
588 | if (ret == -ENOSYS) | |
589 | ret = cpu_suspend(0, pm_data->cpu_suspend); | |
590 | if (ret) | |
591 | return ret; | |
592 | ||
adc548d7 AK |
593 | if (pm_data->pm_resume_prepare) |
594 | pm_data->pm_resume_prepare(); | |
0d713cf1 BZ |
595 | s3c_pm_restore_uarts(); |
596 | ||
597 | S3C_PMDBG("%s: wakeup stat: %08x\n", __func__, | |
598 | pmu_raw_readl(S5P_WAKEUP_STAT)); | |
599 | ||
600 | s3c_pm_check_restore(); | |
601 | ||
602 | S3C_PMDBG("%s: resuming the system...\n", __func__); | |
603 | ||
604 | return 0; | |
605 | } | |
606 | ||
607 | static int exynos_suspend_prepare(void) | |
608 | { | |
c645a598 JMC |
609 | int ret; |
610 | ||
611 | /* | |
612 | * REVISIT: It would be better if struct platform_suspend_ops | |
613 | * .prepare handler get the suspend_state_t as a parameter to | |
614 | * avoid hard-coding the suspend to mem state. It's safe to do | |
615 | * it now only because the suspend_valid_only_mem function is | |
616 | * used as the .valid callback used to check if a given state | |
617 | * is supported by the platform anyways. | |
618 | */ | |
619 | ret = regulator_suspend_prepare(PM_SUSPEND_MEM); | |
620 | if (ret) { | |
621 | pr_err("Failed to prepare regulators for suspend (%d)\n", ret); | |
622 | return ret; | |
623 | } | |
624 | ||
0d713cf1 BZ |
625 | s3c_pm_check_prepare(); |
626 | ||
627 | return 0; | |
628 | } | |
629 | ||
630 | static void exynos_suspend_finish(void) | |
631 | { | |
c645a598 JMC |
632 | int ret; |
633 | ||
0d713cf1 | 634 | s3c_pm_check_cleanup(); |
c645a598 JMC |
635 | |
636 | ret = regulator_suspend_finish(); | |
637 | if (ret) | |
638 | pr_warn("Failed to resume regulators from suspend (%d)\n", ret); | |
0d713cf1 BZ |
639 | } |
640 | ||
641 | static const struct platform_suspend_ops exynos_suspend_ops = { | |
642 | .enter = exynos_suspend_enter, | |
643 | .prepare = exynos_suspend_prepare, | |
644 | .finish = exynos_suspend_finish, | |
645 | .valid = suspend_valid_only_mem, | |
646 | }; | |
647 | ||
a4f582f5 CC |
648 | static const struct exynos_pm_data exynos3250_pm_data = { |
649 | .wkup_irq = exynos3250_wkup_irq, | |
650 | .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), | |
651 | .release_ret_regs = exynos3250_release_ret_regs, | |
652 | .pm_suspend = exynos_pm_suspend, | |
653 | .pm_resume = exynos3250_pm_resume, | |
654 | .pm_prepare = exynos3250_pm_prepare, | |
655 | .cpu_suspend = exynos3250_cpu_suspend, | |
656 | }; | |
657 | ||
0d713cf1 BZ |
658 | static const struct exynos_pm_data exynos4_pm_data = { |
659 | .wkup_irq = exynos4_wkup_irq, | |
660 | .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), | |
661 | .release_ret_regs = exynos_release_ret_regs, | |
662 | .pm_suspend = exynos_pm_suspend, | |
663 | .pm_resume = exynos_pm_resume, | |
664 | .pm_prepare = exynos_pm_prepare, | |
665 | .cpu_suspend = exynos_cpu_suspend, | |
666 | }; | |
667 | ||
668 | static const struct exynos_pm_data exynos5250_pm_data = { | |
669 | .wkup_irq = exynos5250_wkup_irq, | |
670 | .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), | |
671 | .release_ret_regs = exynos_release_ret_regs, | |
0d713cf1 BZ |
672 | .pm_suspend = exynos_pm_suspend, |
673 | .pm_resume = exynos_pm_resume, | |
674 | .pm_prepare = exynos_pm_prepare, | |
675 | .cpu_suspend = exynos_cpu_suspend, | |
676 | }; | |
677 | ||
73838337 | 678 | static const struct exynos_pm_data exynos5420_pm_data = { |
0fdf088f VS |
679 | .wkup_irq = exynos5250_wkup_irq, |
680 | .wake_disable_mask = (0x7F << 7) | (0x1F << 1), | |
681 | .release_ret_regs = exynos5420_release_ret_regs, | |
adc548d7 | 682 | .pm_resume_prepare = exynos5420_prepare_pm_resume, |
0fdf088f VS |
683 | .pm_resume = exynos5420_pm_resume, |
684 | .pm_suspend = exynos5420_pm_suspend, | |
685 | .pm_prepare = exynos5420_pm_prepare, | |
686 | .cpu_suspend = exynos5420_cpu_suspend, | |
687 | }; | |
688 | ||
444d2d33 | 689 | static const struct of_device_id exynos_pmu_of_device_ids[] __initconst = { |
0d713cf1 | 690 | { |
a4f582f5 CC |
691 | .compatible = "samsung,exynos3250-pmu", |
692 | .data = &exynos3250_pm_data, | |
693 | }, { | |
0d713cf1 BZ |
694 | .compatible = "samsung,exynos4210-pmu", |
695 | .data = &exynos4_pm_data, | |
696 | }, { | |
697 | .compatible = "samsung,exynos4212-pmu", | |
698 | .data = &exynos4_pm_data, | |
699 | }, { | |
700 | .compatible = "samsung,exynos4412-pmu", | |
701 | .data = &exynos4_pm_data, | |
702 | }, { | |
703 | .compatible = "samsung,exynos5250-pmu", | |
704 | .data = &exynos5250_pm_data, | |
0fdf088f VS |
705 | }, { |
706 | .compatible = "samsung,exynos5420-pmu", | |
707 | .data = &exynos5420_pm_data, | |
0d713cf1 BZ |
708 | }, |
709 | { /*sentinel*/ }, | |
710 | }; | |
711 | ||
712 | static struct syscore_ops exynos_pm_syscore_ops; | |
713 | ||
714 | void __init exynos_pm_init(void) | |
715 | { | |
716 | const struct of_device_id *match; | |
8b283c02 | 717 | struct device_node *np; |
0d713cf1 BZ |
718 | u32 tmp; |
719 | ||
8b283c02 MZ |
720 | np = of_find_matching_node_and_match(NULL, exynos_pmu_of_device_ids, &match); |
721 | if (!np) { | |
0d713cf1 BZ |
722 | pr_err("Failed to find PMU node\n"); |
723 | return; | |
724 | } | |
0d713cf1 | 725 | |
e5cbec61 | 726 | if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) { |
8b283c02 | 727 | pr_warn("Outdated DT detected, suspend/resume will NOT work\n"); |
e5cbec61 JG |
728 | return; |
729 | } | |
8b283c02 | 730 | |
e6c81cce | 731 | pm_data = (const struct exynos_pm_data *) match->data; |
0d713cf1 BZ |
732 | |
733 | /* All wakeup disable */ | |
734 | tmp = pmu_raw_readl(S5P_WAKEUP_MASK); | |
735 | tmp |= pm_data->wake_disable_mask; | |
736 | pmu_raw_writel(tmp, S5P_WAKEUP_MASK); | |
737 | ||
738 | exynos_pm_syscore_ops.suspend = pm_data->pm_suspend; | |
739 | exynos_pm_syscore_ops.resume = pm_data->pm_resume; | |
740 | ||
741 | register_syscore_ops(&exynos_pm_syscore_ops); | |
742 | suspend_set_ops(&exynos_suspend_ops); | |
743 | } |