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7d30e8b3 KK |
1 | /* linux/arch/arm/mach-exynos4/dma.c |
2 | * | |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com | |
5 | * | |
8b0ae0b7 JB |
6 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. |
7 | * Jaswinder Singh <jassi.brar@samsung.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
22 | */ | |
23 | ||
24 | #include <linux/platform_device.h> | |
25 | #include <linux/dma-mapping.h> | |
26 | ||
27 | #include <plat/devs.h> | |
28 | #include <plat/irqs.h> | |
29 | ||
30 | #include <mach/map.h> | |
31 | #include <mach/irqs.h> | |
32 | ||
33 | #include <plat/s3c-pl330-pdata.h> | |
34 | ||
35 | static u64 dma_dmamask = DMA_BIT_MASK(32); | |
36 | ||
7d30e8b3 | 37 | static struct resource exynos4_pdma0_resource[] = { |
8b0ae0b7 | 38 | [0] = { |
7d30e8b3 KK |
39 | .start = EXYNOS4_PA_PDMA0, |
40 | .end = EXYNOS4_PA_PDMA0 + SZ_4K, | |
8b0ae0b7 JB |
41 | .flags = IORESOURCE_MEM, |
42 | }, | |
43 | [1] = { | |
44 | .start = IRQ_PDMA0, | |
45 | .end = IRQ_PDMA0, | |
46 | .flags = IORESOURCE_IRQ, | |
47 | }, | |
48 | }; | |
49 | ||
7d30e8b3 | 50 | static struct s3c_pl330_platdata exynos4_pdma0_pdata = { |
8b0ae0b7 JB |
51 | .peri = { |
52 | [0] = DMACH_PCM0_RX, | |
53 | [1] = DMACH_PCM0_TX, | |
54 | [2] = DMACH_PCM2_RX, | |
55 | [3] = DMACH_PCM2_TX, | |
56 | [4] = DMACH_MSM_REQ0, | |
57 | [5] = DMACH_MSM_REQ2, | |
58 | [6] = DMACH_SPI0_RX, | |
59 | [7] = DMACH_SPI0_TX, | |
60 | [8] = DMACH_SPI2_RX, | |
61 | [9] = DMACH_SPI2_TX, | |
62 | [10] = DMACH_I2S0S_TX, | |
63 | [11] = DMACH_I2S0_RX, | |
64 | [12] = DMACH_I2S0_TX, | |
65 | [13] = DMACH_I2S2_RX, | |
66 | [14] = DMACH_I2S2_TX, | |
67 | [15] = DMACH_UART0_RX, | |
68 | [16] = DMACH_UART0_TX, | |
69 | [17] = DMACH_UART2_RX, | |
70 | [18] = DMACH_UART2_TX, | |
71 | [19] = DMACH_UART4_RX, | |
72 | [20] = DMACH_UART4_TX, | |
73 | [21] = DMACH_SLIMBUS0_RX, | |
74 | [22] = DMACH_SLIMBUS0_TX, | |
75 | [23] = DMACH_SLIMBUS2_RX, | |
76 | [24] = DMACH_SLIMBUS2_TX, | |
77 | [25] = DMACH_SLIMBUS4_RX, | |
78 | [26] = DMACH_SLIMBUS4_TX, | |
79 | [27] = DMACH_AC97_MICIN, | |
80 | [28] = DMACH_AC97_PCMIN, | |
81 | [29] = DMACH_AC97_PCMOUT, | |
82 | [30] = DMACH_MAX, | |
83 | [31] = DMACH_MAX, | |
84 | }, | |
85 | }; | |
86 | ||
7d30e8b3 | 87 | static struct platform_device exynos4_device_pdma0 = { |
8b0ae0b7 JB |
88 | .name = "s3c-pl330", |
89 | .id = 0, | |
7d30e8b3 KK |
90 | .num_resources = ARRAY_SIZE(exynos4_pdma0_resource), |
91 | .resource = exynos4_pdma0_resource, | |
8b0ae0b7 JB |
92 | .dev = { |
93 | .dma_mask = &dma_dmamask, | |
94 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
7d30e8b3 | 95 | .platform_data = &exynos4_pdma0_pdata, |
8b0ae0b7 JB |
96 | }, |
97 | }; | |
98 | ||
7d30e8b3 | 99 | static struct resource exynos4_pdma1_resource[] = { |
8b0ae0b7 | 100 | [0] = { |
7d30e8b3 KK |
101 | .start = EXYNOS4_PA_PDMA1, |
102 | .end = EXYNOS4_PA_PDMA1 + SZ_4K, | |
8b0ae0b7 JB |
103 | .flags = IORESOURCE_MEM, |
104 | }, | |
105 | [1] = { | |
106 | .start = IRQ_PDMA1, | |
107 | .end = IRQ_PDMA1, | |
108 | .flags = IORESOURCE_IRQ, | |
109 | }, | |
110 | }; | |
111 | ||
7d30e8b3 | 112 | static struct s3c_pl330_platdata exynos4_pdma1_pdata = { |
8b0ae0b7 JB |
113 | .peri = { |
114 | [0] = DMACH_PCM0_RX, | |
115 | [1] = DMACH_PCM0_TX, | |
116 | [2] = DMACH_PCM1_RX, | |
117 | [3] = DMACH_PCM1_TX, | |
118 | [4] = DMACH_MSM_REQ1, | |
119 | [5] = DMACH_MSM_REQ3, | |
120 | [6] = DMACH_SPI1_RX, | |
121 | [7] = DMACH_SPI1_TX, | |
122 | [8] = DMACH_I2S0S_TX, | |
123 | [9] = DMACH_I2S0_RX, | |
124 | [10] = DMACH_I2S0_TX, | |
125 | [11] = DMACH_I2S1_RX, | |
126 | [12] = DMACH_I2S1_TX, | |
127 | [13] = DMACH_UART0_RX, | |
128 | [14] = DMACH_UART0_TX, | |
129 | [15] = DMACH_UART1_RX, | |
130 | [16] = DMACH_UART1_TX, | |
131 | [17] = DMACH_UART3_RX, | |
132 | [18] = DMACH_UART3_TX, | |
133 | [19] = DMACH_SLIMBUS1_RX, | |
134 | [20] = DMACH_SLIMBUS1_TX, | |
135 | [21] = DMACH_SLIMBUS3_RX, | |
136 | [22] = DMACH_SLIMBUS3_TX, | |
137 | [23] = DMACH_SLIMBUS5_RX, | |
138 | [24] = DMACH_SLIMBUS5_TX, | |
139 | [25] = DMACH_SLIMBUS0AUX_RX, | |
140 | [26] = DMACH_SLIMBUS0AUX_TX, | |
141 | [27] = DMACH_SPDIF, | |
142 | [28] = DMACH_MAX, | |
143 | [29] = DMACH_MAX, | |
144 | [30] = DMACH_MAX, | |
145 | [31] = DMACH_MAX, | |
146 | }, | |
147 | }; | |
148 | ||
7d30e8b3 | 149 | static struct platform_device exynos4_device_pdma1 = { |
8b0ae0b7 JB |
150 | .name = "s3c-pl330", |
151 | .id = 1, | |
7d30e8b3 KK |
152 | .num_resources = ARRAY_SIZE(exynos4_pdma1_resource), |
153 | .resource = exynos4_pdma1_resource, | |
8b0ae0b7 JB |
154 | .dev = { |
155 | .dma_mask = &dma_dmamask, | |
156 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
7d30e8b3 | 157 | .platform_data = &exynos4_pdma1_pdata, |
8b0ae0b7 JB |
158 | }, |
159 | }; | |
160 | ||
7d30e8b3 KK |
161 | static struct platform_device *exynos4_dmacs[] __initdata = { |
162 | &exynos4_device_pdma0, | |
163 | &exynos4_device_pdma1, | |
8b0ae0b7 JB |
164 | }; |
165 | ||
7d30e8b3 | 166 | static int __init exynos4_dma_init(void) |
8b0ae0b7 | 167 | { |
7d30e8b3 | 168 | platform_add_devices(exynos4_dmacs, ARRAY_SIZE(exynos4_dmacs)); |
8b0ae0b7 JB |
169 | |
170 | return 0; | |
171 | } | |
7d30e8b3 | 172 | arch_initcall(exynos4_dma_init); |