[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-exynos4 / mach-smdkc210.c

/* linux/arch/arm/mach-exynos4/mach-smdkc210.c
 *
 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/serial_core.h>
#include <linux/gpio.h>
#include <linux/mmc/host.h>
#include <linux/platform_device.h>
#include <linux/smsc911x.h>
#include <linux/io.h>
#include <linux/i2c.h>

#include <asm/mach/arch.h>
#include <asm/mach-types.h>

#include <plat/regs-serial.h>
#include <plat/regs-srom.h>
#include <plat/exynos4.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/sdhci.h>
#include <plat/iic.h>
#include <plat/pd.h>

#include <mach/map.h>

/* Following are default values for UCON, ULCON and UFCON UART registers */
#define SMDKC210_UCON_DEFAULT	(S3C2410_UCON_TXILEVEL |	\
				 S3C2410_UCON_RXILEVEL |	\
				 S3C2410_UCON_TXIRQMODE |	\
				 S3C2410_UCON_RXIRQMODE |	\
				 S3C2410_UCON_RXFIFO_TOI |	\
				 S3C2443_UCON_RXERR_IRQEN)

#define SMDKC210_ULCON_DEFAULT	S3C2410_LCON_CS8

#define SMDKC210_UFCON_DEFAULT	(S3C2410_UFCON_FIFOMODE |	\
				 S5PV210_UFCON_TXTRIG4 |	\
				 S5PV210_UFCON_RXTRIG4)

static struct s3c2410_uartcfg smdkc210_uartcfgs[] __initdata = {
	[0] = {
		.hwport		= 0,
		.flags		= 0,
		.ucon		= SMDKC210_UCON_DEFAULT,
		.ulcon		= SMDKC210_ULCON_DEFAULT,
		.ufcon		= SMDKC210_UFCON_DEFAULT,
	},
	[1] = {
		.hwport		= 1,
		.flags		= 0,
		.ucon		= SMDKC210_UCON_DEFAULT,
		.ulcon		= SMDKC210_ULCON_DEFAULT,
		.ufcon		= SMDKC210_UFCON_DEFAULT,
	},
	[2] = {
		.hwport		= 2,
		.flags		= 0,
		.ucon		= SMDKC210_UCON_DEFAULT,
		.ulcon		= SMDKC210_ULCON_DEFAULT,
		.ufcon		= SMDKC210_UFCON_DEFAULT,
	},
	[3] = {
		.hwport		= 3,
		.flags		= 0,
		.ucon		= SMDKC210_UCON_DEFAULT,
		.ulcon		= SMDKC210_ULCON_DEFAULT,
		.ufcon		= SMDKC210_UFCON_DEFAULT,
	},
};

static struct s3c_sdhci_platdata smdkc210_hsmmc0_pdata __initdata = {
	.cd_type		= S3C_SDHCI_CD_GPIO,
	.ext_cd_gpio		= EXYNOS4_GPK0(2),
	.ext_cd_gpio_invert	= 1,
	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
	.max_width		= 8,
	.host_caps		= MMC_CAP_8_BIT_DATA,
#endif
};

static struct s3c_sdhci_platdata smdkc210_hsmmc1_pdata __initdata = {
	.cd_type		= S3C_SDHCI_CD_GPIO,
	.ext_cd_gpio		= EXYNOS4_GPK0(2),
	.ext_cd_gpio_invert	= 1,
	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
};

static struct s3c_sdhci_platdata smdkc210_hsmmc2_pdata __initdata = {
	.cd_type		= S3C_SDHCI_CD_GPIO,
	.ext_cd_gpio		= EXYNOS4_GPK2(2),
	.ext_cd_gpio_invert	= 1,
	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
	.max_width		= 8,
	.host_caps		= MMC_CAP_8_BIT_DATA,
#endif
};

static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata __initdata = {
	.cd_type		= S3C_SDHCI_CD_GPIO,
	.ext_cd_gpio		= EXYNOS4_GPK2(2),
	.ext_cd_gpio_invert	= 1,
	.clk_type		= S3C_SDHCI_CLK_DIV_EXTERNAL,
};

static struct resource smdkc210_smsc911x_resources[] = {
	[0] = {
		.start	= EXYNOS4_PA_SROM_BANK(1),
		.end	= EXYNOS4_PA_SROM_BANK(1) + SZ_64K - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= IRQ_EINT(5),
		.end	= IRQ_EINT(5),
		.flags	= IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
	},
};

static struct smsc911x_platform_config smsc9215_config = {
	.irq_polarity	= SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
	.irq_type	= SMSC911X_IRQ_TYPE_PUSH_PULL,
	.flags		= SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
	.phy_interface	= PHY_INTERFACE_MODE_MII,
	.mac		= {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
};

static struct platform_device smdkc210_smsc911x = {
	.name		= "smsc911x",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(smdkc210_smsc911x_resources),
	.resource	= smdkc210_smsc911x_resources,
	.dev		= {
		.platform_data	= &smsc9215_config,
	},
};

static struct i2c_board_info i2c_devs1[] __initdata = {
	{I2C_BOARD_INFO("wm8994", 0x1a),},
};

static struct platform_device *smdkc210_devices[] __initdata = {
	&s3c_device_hsmmc0,
	&s3c_device_hsmmc1,
	&s3c_device_hsmmc2,
	&s3c_device_hsmmc3,
	&s3c_device_i2c1,
	&s3c_device_rtc,
	&s3c_device_wdt,
	&exynos4_device_ac97,
	&exynos4_device_i2s0,
	&exynos4_device_pd[PD_MFC],
	&exynos4_device_pd[PD_G3D],
	&exynos4_device_pd[PD_LCD0],
	&exynos4_device_pd[PD_LCD1],
	&exynos4_device_pd[PD_CAM],
	&exynos4_device_pd[PD_TV],
	&exynos4_device_pd[PD_GPS],
	&exynos4_device_sysmmu,
	&samsung_asoc_dma,
	&smdkc210_smsc911x,
};

static void __init smdkc210_smsc911x_init(void)
{
	u32 cs1;

	/* configure nCS1 width to 16 bits */
	cs1 = __raw_readl(S5P_SROM_BW) &
		~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
	cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
		(1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
		(1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
		S5P_SROM_BW__NCS1__SHIFT;
	__raw_writel(cs1, S5P_SROM_BW);

	/* set timing for nCS1 suitable for ethernet chip */
	__raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
		     (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
		     (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
		     (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
		     (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
		     (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
		     (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
}

static void __init smdkc210_map_io(void)
{
	s5p_init_io(NULL, 0, S5P_VA_CHIPID);
	s3c24xx_init_clocks(24000000);
	s3c24xx_init_uarts(smdkc210_uartcfgs, ARRAY_SIZE(smdkc210_uartcfgs));
}

static void __init smdkc210_machine_init(void)
{
	s3c_i2c1_set_platdata(NULL);
	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));

	smdkc210_smsc911x_init();

	s3c_sdhci0_set_platdata(&smdkc210_hsmmc0_pdata);
	s3c_sdhci1_set_platdata(&smdkc210_hsmmc1_pdata);
	s3c_sdhci2_set_platdata(&smdkc210_hsmmc2_pdata);
	s3c_sdhci3_set_platdata(&smdkc210_hsmmc3_pdata);

	platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices));
}

MACHINE_START(SMDKC210, "SMDKC210")
	/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
	.boot_params	= S5P_PA_SDRAM + 0x100,
	.init_irq	= exynos4_init_irq,
	.map_io		= smdkc210_map_io,
	.init_machine	= smdkc210_machine_init,
	.timer		= &exynos4_timer,
MACHINE_END
Commit	Line	Data
d11135ca	1	/* linux/arch/arm/mach-exynos4/mach-smdkc210.c
c05b48af	2	*
d11135ca KK	3	* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
d11135ca KK	4	* http://www.samsung.com
c05b48af KK	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	#include <linux/serial_core.h>
2b11148a HL	12	#include <linux/gpio.h>
	13	#include <linux/mmc/host.h>
	14	#include <linux/platform_device.h>
cbff3eb3 DM	15	#include <linux/smsc911x.h>
cbff3eb3 DM	16	#include <linux/io.h>
d8a2d39d	17	#include <linux/i2c.h>
c05b48af KK	18
	19	#include <asm/mach/arch.h>
	20	#include <asm/mach-types.h>
c05b48af KK	21
c05b48af KK	22	#include <plat/regs-serial.h>
8cf460a5	23	#include <plat/regs-srom.h>
d11135ca	24	#include <plat/exynos4.h>
c05b48af	25	#include <plat/cpu.h>
cdff6e6f	26	#include <plat/devs.h>
2b11148a	27	#include <plat/sdhci.h>
d8a2d39d	28	#include <plat/iic.h>
d6d8b481	29	#include <plat/pd.h>
c05b48af KK	30
	31	#include <mach/map.h>
	32
	33	/* Following are default values for UCON, ULCON and UFCON UART registers */
	34	#define SMDKC210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL \| \
	35	S3C2410_UCON_RXILEVEL \| \
	36	S3C2410_UCON_TXIRQMODE \| \
	37	S3C2410_UCON_RXIRQMODE \| \
	38	S3C2410_UCON_RXFIFO_TOI \| \
	39	S3C2443_UCON_RXERR_IRQEN)
	40
	41	#define SMDKC210_ULCON_DEFAULT S3C2410_LCON_CS8
	42
	43	#define SMDKC210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE \| \
	44	S5PV210_UFCON_TXTRIG4 \| \
	45	S5PV210_UFCON_RXTRIG4)
	46
	47	static struct s3c2410_uartcfg smdkc210_uartcfgs[] __initdata = {
	48	[0] = {
	49	.hwport = 0,
	50	.flags = 0,
	51	.ucon = SMDKC210_UCON_DEFAULT,
	52	.ulcon = SMDKC210_ULCON_DEFAULT,
	53	.ufcon = SMDKC210_UFCON_DEFAULT,
	54	},
	55	[1] = {
	56	.hwport = 1,
	57	.flags = 0,
	58	.ucon = SMDKC210_UCON_DEFAULT,
	59	.ulcon = SMDKC210_ULCON_DEFAULT,
	60	.ufcon = SMDKC210_UFCON_DEFAULT,
	61	},
	62	[2] = {
	63	.hwport = 2,
	64	.flags = 0,
	65	.ucon = SMDKC210_UCON_DEFAULT,
	66	.ulcon = SMDKC210_ULCON_DEFAULT,
	67	.ufcon = SMDKC210_UFCON_DEFAULT,
	68	},
	69	[3] = {
	70	.hwport = 3,
	71	.flags = 0,
	72	.ucon = SMDKC210_UCON_DEFAULT,
	73	.ulcon = SMDKC210_ULCON_DEFAULT,
	74	.ufcon = SMDKC210_UFCON_DEFAULT,
	75	},
	76	};
	77
2b11148a HL	78	static struct s3c_sdhci_platdata smdkc210_hsmmc0_pdata __initdata = {
2b11148a HL	79	.cd_type = S3C_SDHCI_CD_GPIO,
d11135ca	80	.ext_cd_gpio = EXYNOS4_GPK0(2),
2b11148a	81	.ext_cd_gpio_invert = 1,
28c80aa7	82	.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
d11135ca	83	#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
2b11148a HL	84	.max_width = 8,
	85	.host_caps = MMC_CAP_8_BIT_DATA,
	86	#endif
	87	};
	88
	89	static struct s3c_sdhci_platdata smdkc210_hsmmc1_pdata __initdata = {
	90	.cd_type = S3C_SDHCI_CD_GPIO,
d11135ca	91	.ext_cd_gpio = EXYNOS4_GPK0(2),
2b11148a	92	.ext_cd_gpio_invert = 1,
28c80aa7	93	.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
2b11148a HL	94	};
	95
	96	static struct s3c_sdhci_platdata smdkc210_hsmmc2_pdata __initdata = {
	97	.cd_type = S3C_SDHCI_CD_GPIO,
d11135ca	98	.ext_cd_gpio = EXYNOS4_GPK2(2),
2b11148a	99	.ext_cd_gpio_invert = 1,
28c80aa7	100	.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
d11135ca	101	#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
2b11148a HL	102	.max_width = 8,
	103	.host_caps = MMC_CAP_8_BIT_DATA,
	104	#endif
	105	};
	106
	107	static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata __initdata = {
	108	.cd_type = S3C_SDHCI_CD_GPIO,
d11135ca	109	.ext_cd_gpio = EXYNOS4_GPK2(2),
2b11148a	110	.ext_cd_gpio_invert = 1,
28c80aa7	111	.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
2b11148a HL	112	};
2b11148a HL	113
cbff3eb3 DM	114	static struct resource smdkc210_smsc911x_resources[] = {
cbff3eb3 DM	115	[0] = {
d11135ca KK	116	.start = EXYNOS4_PA_SROM_BANK(1),
d11135ca KK	117	.end = EXYNOS4_PA_SROM_BANK(1) + SZ_64K - 1,
cbff3eb3 DM	118	.flags = IORESOURCE_MEM,
	119	},
	120	[1] = {
	121	.start = IRQ_EINT(5),
	122	.end = IRQ_EINT(5),
	123	.flags = IORESOURCE_IRQ \| IRQF_TRIGGER_LOW,
	124	},
	125	};
	126
	127	static struct smsc911x_platform_config smsc9215_config = {
1af3c672	128	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
cbff3eb3 DM	129	.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
	130	.flags = SMSC911X_USE_16BIT \| SMSC911X_FORCE_INTERNAL_PHY,
	131	.phy_interface = PHY_INTERFACE_MODE_MII,
	132	.mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
	133	};
	134
	135	static struct platform_device smdkc210_smsc911x = {
	136	.name = "smsc911x",
	137	.id = -1,
	138	.num_resources = ARRAY_SIZE(smdkc210_smsc911x_resources),
	139	.resource = smdkc210_smsc911x_resources,
	140	.dev = {
	141	.platform_data = &smsc9215_config,
	142	},
	143	};
	144
d8a2d39d JB	145	static struct i2c_board_info i2c_devs1[] __initdata = {
	146	{I2C_BOARD_INFO("wm8994", 0x1a),},
	147	};
	148
cdff6e6f	149	static struct platform_device *smdkc210_devices[] __initdata = {
2b11148a HL	150	&s3c_device_hsmmc0,
	151	&s3c_device_hsmmc1,
	152	&s3c_device_hsmmc2,
	153	&s3c_device_hsmmc3,
285dee7f	154	&s3c_device_i2c1,
cdff6e6f	155	&s3c_device_rtc,
8d75c912	156	&s3c_device_wdt,
d11135ca KK	157	&exynos4_device_ac97,
	158	&exynos4_device_i2s0,
	159	&exynos4_device_pd[PD_MFC],
	160	&exynos4_device_pd[PD_G3D],
	161	&exynos4_device_pd[PD_LCD0],
	162	&exynos4_device_pd[PD_LCD1],
	163	&exynos4_device_pd[PD_CAM],
	164	&exynos4_device_pd[PD_TV],
	165	&exynos4_device_pd[PD_GPS],
	166	&exynos4_device_sysmmu,
fbcb44de JB	167	&samsung_asoc_dma,
fbcb44de JB	168	&smdkc210_smsc911x,
cdff6e6f CY	169	};
cdff6e6f CY	170
cbff3eb3 DM	171	static void __init smdkc210_smsc911x_init(void)
	172	{
	173	u32 cs1;
	174
	175	/* configure nCS1 width to 16 bits */
8cf460a5 KK	176	cs1 = __raw_readl(S5P_SROM_BW) &
	177	~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
	178	cs1 \|= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) \|
	179	(1 << S5P_SROM_BW__WAITENABLE__SHIFT) \|
	180	(1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
	181	S5P_SROM_BW__NCS1__SHIFT;
	182	__raw_writel(cs1, S5P_SROM_BW);
cbff3eb3 DM	183
cbff3eb3 DM	184	/* set timing for nCS1 suitable for ethernet chip */
8cf460a5 KK	185	__raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) \|
	186	(0x9 << S5P_SROM_BCX__TACP__SHIFT) \|
	187	(0xc << S5P_SROM_BCX__TCAH__SHIFT) \|
	188	(0x1 << S5P_SROM_BCX__TCOH__SHIFT) \|
	189	(0x6 << S5P_SROM_BCX__TACC__SHIFT) \|
	190	(0x1 << S5P_SROM_BCX__TCOS__SHIFT) \|
	191	(0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
cbff3eb3 DM	192	}
cbff3eb3 DM	193
c05b48af KK	194	static void __init smdkc210_map_io(void)
	195	{
	196	s5p_init_io(NULL, 0, S5P_VA_CHIPID);
	197	s3c24xx_init_clocks(24000000);
	198	s3c24xx_init_uarts(smdkc210_uartcfgs, ARRAY_SIZE(smdkc210_uartcfgs));
	199	}
	200
	201	static void __init smdkc210_machine_init(void)
	202	{
d8a2d39d JB	203	s3c_i2c1_set_platdata(NULL);
	204	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
	205
cbff3eb3 DM	206	smdkc210_smsc911x_init();
cbff3eb3 DM	207
2b11148a HL	208	s3c_sdhci0_set_platdata(&smdkc210_hsmmc0_pdata);
	209	s3c_sdhci1_set_platdata(&smdkc210_hsmmc1_pdata);
	210	s3c_sdhci2_set_platdata(&smdkc210_hsmmc2_pdata);
	211	s3c_sdhci3_set_platdata(&smdkc210_hsmmc3_pdata);
	212
cdff6e6f	213	platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices));
c05b48af KK	214	}
	215
	216	MACHINE_START(SMDKC210, "SMDKC210")
	217	/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
	218	.boot_params = S5P_PA_SDRAM + 0x100,
d11135ca	219	.init_irq = exynos4_init_irq,
c05b48af KK	220	.map_io = smdkc210_map_io,
c05b48af KK	221	.init_machine = smdkc210_machine_init,
d11135ca	222	.timer = &exynos4_timer,
c05b48af	223	MACHINE_END