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d11135ca | 1 | /* linux/arch/arm/mach-exynos4/mach-universal_c210.c |
516607d6 KP |
2 | * |
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | */ | |
9 | ||
34d79315 | 10 | #include <linux/platform_device.h> |
516607d6 | 11 | #include <linux/serial_core.h> |
34d79315 | 12 | #include <linux/input.h> |
3b7998f5 | 13 | #include <linux/i2c.h> |
34d79315 KP |
14 | #include <linux/gpio_keys.h> |
15 | #include <linux/gpio.h> | |
4d838ec0 | 16 | #include <linux/mfd/max8998.h> |
a8928ce7 KP |
17 | #include <linux/regulator/machine.h> |
18 | #include <linux/regulator/fixed.h> | |
4d838ec0 | 19 | #include <linux/regulator/max8952.h> |
a8928ce7 | 20 | #include <linux/mmc/host.h> |
516607d6 KP |
21 | |
22 | #include <asm/mach/arch.h> | |
23 | #include <asm/mach-types.h> | |
516607d6 KP |
24 | |
25 | #include <plat/regs-serial.h> | |
d11135ca | 26 | #include <plat/exynos4.h> |
516607d6 | 27 | #include <plat/cpu.h> |
acf5eda9 | 28 | #include <plat/devs.h> |
4d838ec0 | 29 | #include <plat/iic.h> |
a8928ce7 | 30 | #include <plat/sdhci.h> |
516607d6 KP |
31 | |
32 | #include <mach/map.h> | |
33 | ||
34 | /* Following are default values for UCON, ULCON and UFCON UART registers */ | |
35 | #define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ | |
36 | S3C2410_UCON_RXILEVEL | \ | |
37 | S3C2410_UCON_TXIRQMODE | \ | |
38 | S3C2410_UCON_RXIRQMODE | \ | |
39 | S3C2410_UCON_RXFIFO_TOI | \ | |
40 | S3C2443_UCON_RXERR_IRQEN) | |
41 | ||
42 | #define UNIVERSAL_ULCON_DEFAULT S3C2410_LCON_CS8 | |
43 | ||
44 | #define UNIVERSAL_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ | |
45 | S5PV210_UFCON_TXTRIG256 | \ | |
46 | S5PV210_UFCON_RXTRIG256) | |
47 | ||
48 | static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = { | |
49 | [0] = { | |
50 | .hwport = 0, | |
51 | .ucon = UNIVERSAL_UCON_DEFAULT, | |
52 | .ulcon = UNIVERSAL_ULCON_DEFAULT, | |
53 | .ufcon = UNIVERSAL_UFCON_DEFAULT, | |
54 | }, | |
55 | [1] = { | |
56 | .hwport = 1, | |
57 | .ucon = UNIVERSAL_UCON_DEFAULT, | |
58 | .ulcon = UNIVERSAL_ULCON_DEFAULT, | |
59 | .ufcon = UNIVERSAL_UFCON_DEFAULT, | |
60 | }, | |
61 | [2] = { | |
62 | .hwport = 2, | |
63 | .ucon = UNIVERSAL_UCON_DEFAULT, | |
64 | .ulcon = UNIVERSAL_ULCON_DEFAULT, | |
65 | .ufcon = UNIVERSAL_UFCON_DEFAULT, | |
66 | }, | |
67 | [3] = { | |
68 | .hwport = 3, | |
69 | .ucon = UNIVERSAL_UCON_DEFAULT, | |
70 | .ulcon = UNIVERSAL_ULCON_DEFAULT, | |
71 | .ufcon = UNIVERSAL_UFCON_DEFAULT, | |
72 | }, | |
73 | }; | |
74 | ||
4d838ec0 MS |
75 | static struct regulator_consumer_supply max8952_consumer = |
76 | REGULATOR_SUPPLY("vddarm", NULL); | |
77 | ||
78 | static struct max8952_platform_data universal_max8952_pdata __initdata = { | |
79 | .gpio_vid0 = EXYNOS4_GPX0(3), | |
80 | .gpio_vid1 = EXYNOS4_GPX0(4), | |
81 | .gpio_en = -1, /* Not controllable, set "Always High" */ | |
82 | .default_mode = 0, /* vid0 = 0, vid1 = 0 */ | |
83 | .dvs_mode = { 48, 32, 28, 18 }, /* 1.25, 1.20, 1.05, 0.95V */ | |
84 | .sync_freq = 0, /* default: fastest */ | |
85 | .ramp_speed = 0, /* default: fastest */ | |
86 | ||
87 | .reg_data = { | |
88 | .constraints = { | |
89 | .name = "VARM_1.2V", | |
90 | .min_uV = 770000, | |
91 | .max_uV = 1400000, | |
92 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, | |
93 | .always_on = 1, | |
94 | .boot_on = 1, | |
95 | }, | |
96 | .num_consumer_supplies = 1, | |
97 | .consumer_supplies = &max8952_consumer, | |
98 | }, | |
99 | }; | |
100 | ||
101 | static struct regulator_consumer_supply lp3974_buck1_consumer = | |
102 | REGULATOR_SUPPLY("vddint", NULL); | |
103 | ||
104 | static struct regulator_consumer_supply lp3974_buck2_consumer = | |
105 | REGULATOR_SUPPLY("vddg3d", NULL); | |
106 | ||
107 | static struct regulator_init_data lp3974_buck1_data = { | |
108 | .constraints = { | |
109 | .name = "VINT_1.1V", | |
110 | .min_uV = 750000, | |
111 | .max_uV = 1500000, | |
112 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | | |
113 | REGULATOR_CHANGE_STATUS, | |
114 | .boot_on = 1, | |
115 | .state_mem = { | |
116 | .disabled = 1, | |
117 | }, | |
118 | }, | |
119 | .num_consumer_supplies = 1, | |
120 | .consumer_supplies = &lp3974_buck1_consumer, | |
121 | }; | |
122 | ||
123 | static struct regulator_init_data lp3974_buck2_data = { | |
124 | .constraints = { | |
125 | .name = "VG3D_1.1V", | |
126 | .min_uV = 750000, | |
127 | .max_uV = 1500000, | |
128 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | | |
129 | REGULATOR_CHANGE_STATUS, | |
130 | .boot_on = 1, | |
131 | .state_mem = { | |
132 | .disabled = 1, | |
133 | }, | |
134 | }, | |
135 | .num_consumer_supplies = 1, | |
136 | .consumer_supplies = &lp3974_buck2_consumer, | |
137 | }; | |
138 | ||
139 | static struct regulator_init_data lp3974_buck3_data = { | |
140 | .constraints = { | |
141 | .name = "VCC_1.8V", | |
142 | .min_uV = 1800000, | |
143 | .max_uV = 1800000, | |
144 | .apply_uV = 1, | |
145 | .always_on = 1, | |
146 | .state_mem = { | |
147 | .enabled = 1, | |
148 | }, | |
149 | }, | |
150 | }; | |
151 | ||
152 | static struct regulator_init_data lp3974_buck4_data = { | |
153 | .constraints = { | |
154 | .name = "VMEM_1.2V", | |
155 | .min_uV = 1200000, | |
156 | .max_uV = 1200000, | |
157 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
158 | .apply_uV = 1, | |
159 | .state_mem = { | |
160 | .disabled = 1, | |
161 | }, | |
162 | }, | |
163 | }; | |
164 | ||
165 | static struct regulator_init_data lp3974_ldo2_data = { | |
166 | .constraints = { | |
167 | .name = "VALIVE_1.2V", | |
168 | .min_uV = 1200000, | |
169 | .max_uV = 1200000, | |
170 | .apply_uV = 1, | |
171 | .always_on = 1, | |
172 | .state_mem = { | |
173 | .enabled = 1, | |
174 | }, | |
175 | }, | |
176 | }; | |
177 | ||
178 | static struct regulator_init_data lp3974_ldo3_data = { | |
179 | .constraints = { | |
180 | .name = "VUSB+MIPI_1.1V", | |
181 | .min_uV = 1100000, | |
182 | .max_uV = 1100000, | |
183 | .apply_uV = 1, | |
184 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
185 | .state_mem = { | |
186 | .disabled = 1, | |
187 | }, | |
188 | }, | |
189 | }; | |
190 | ||
191 | static struct regulator_init_data lp3974_ldo4_data = { | |
192 | .constraints = { | |
193 | .name = "VADC_3.3V", | |
194 | .min_uV = 3300000, | |
195 | .max_uV = 3300000, | |
196 | .apply_uV = 1, | |
197 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
198 | .state_mem = { | |
199 | .disabled = 1, | |
200 | }, | |
201 | }, | |
202 | }; | |
203 | ||
204 | static struct regulator_init_data lp3974_ldo5_data = { | |
205 | .constraints = { | |
206 | .name = "VTF_2.8V", | |
207 | .min_uV = 2800000, | |
208 | .max_uV = 2800000, | |
209 | .apply_uV = 1, | |
210 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
211 | .state_mem = { | |
212 | .disabled = 1, | |
213 | }, | |
214 | }, | |
215 | }; | |
216 | ||
217 | static struct regulator_init_data lp3974_ldo6_data = { | |
218 | .constraints = { | |
219 | .name = "LDO6", | |
220 | .min_uV = 2000000, | |
221 | .max_uV = 2000000, | |
222 | .apply_uV = 1, | |
223 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
224 | .state_mem = { | |
225 | .disabled = 1, | |
226 | }, | |
227 | }, | |
228 | }; | |
229 | ||
230 | static struct regulator_init_data lp3974_ldo7_data = { | |
231 | .constraints = { | |
232 | .name = "VLCD+VMIPI_1.8V", | |
233 | .min_uV = 1800000, | |
234 | .max_uV = 1800000, | |
235 | .apply_uV = 1, | |
236 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
237 | .state_mem = { | |
238 | .disabled = 1, | |
239 | }, | |
240 | }, | |
241 | }; | |
242 | ||
243 | static struct regulator_init_data lp3974_ldo8_data = { | |
244 | .constraints = { | |
245 | .name = "VUSB+VDAC_3.3V", | |
246 | .min_uV = 3300000, | |
247 | .max_uV = 3300000, | |
248 | .apply_uV = 1, | |
249 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
250 | .state_mem = { | |
251 | .disabled = 1, | |
252 | }, | |
253 | }, | |
254 | }; | |
255 | ||
256 | static struct regulator_init_data lp3974_ldo9_data = { | |
257 | .constraints = { | |
258 | .name = "VCC_2.8V", | |
259 | .min_uV = 2800000, | |
260 | .max_uV = 2800000, | |
261 | .apply_uV = 1, | |
262 | .always_on = 1, | |
263 | .state_mem = { | |
264 | .enabled = 1, | |
265 | }, | |
266 | }, | |
267 | }; | |
268 | ||
269 | static struct regulator_init_data lp3974_ldo10_data = { | |
270 | .constraints = { | |
271 | .name = "VPLL_1.1V", | |
272 | .min_uV = 1100000, | |
273 | .max_uV = 1100000, | |
274 | .boot_on = 1, | |
275 | .apply_uV = 1, | |
276 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
277 | .state_mem = { | |
278 | .disabled = 1, | |
279 | }, | |
280 | }, | |
281 | }; | |
282 | ||
283 | static struct regulator_init_data lp3974_ldo11_data = { | |
284 | .constraints = { | |
285 | .name = "CAM_AF_3.3V", | |
286 | .min_uV = 3300000, | |
287 | .max_uV = 3300000, | |
288 | .apply_uV = 1, | |
289 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
290 | .state_mem = { | |
291 | .disabled = 1, | |
292 | }, | |
293 | }, | |
294 | }; | |
295 | ||
296 | static struct regulator_init_data lp3974_ldo12_data = { | |
297 | .constraints = { | |
298 | .name = "PS_2.8V", | |
299 | .min_uV = 2800000, | |
300 | .max_uV = 2800000, | |
301 | .apply_uV = 1, | |
302 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
303 | .state_mem = { | |
304 | .disabled = 1, | |
305 | }, | |
306 | }, | |
307 | }; | |
308 | ||
309 | static struct regulator_init_data lp3974_ldo13_data = { | |
310 | .constraints = { | |
311 | .name = "VHIC_1.2V", | |
312 | .min_uV = 1200000, | |
313 | .max_uV = 1200000, | |
314 | .apply_uV = 1, | |
315 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
316 | .state_mem = { | |
317 | .disabled = 1, | |
318 | }, | |
319 | }, | |
320 | }; | |
321 | ||
322 | static struct regulator_init_data lp3974_ldo14_data = { | |
323 | .constraints = { | |
324 | .name = "CAM_I_HOST_1.8V", | |
325 | .min_uV = 1800000, | |
326 | .max_uV = 1800000, | |
327 | .apply_uV = 1, | |
328 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
329 | .state_mem = { | |
330 | .disabled = 1, | |
331 | }, | |
332 | }, | |
333 | }; | |
334 | ||
335 | static struct regulator_init_data lp3974_ldo15_data = { | |
336 | .constraints = { | |
337 | .name = "CAM_S_DIG+FM33_CORE_1.2V", | |
338 | .min_uV = 1200000, | |
339 | .max_uV = 1200000, | |
340 | .apply_uV = 1, | |
341 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
342 | .state_mem = { | |
343 | .disabled = 1, | |
344 | }, | |
345 | }, | |
346 | }; | |
347 | ||
348 | static struct regulator_init_data lp3974_ldo16_data = { | |
349 | .constraints = { | |
350 | .name = "CAM_S_ANA_2.8V", | |
351 | .min_uV = 2800000, | |
352 | .max_uV = 2800000, | |
353 | .apply_uV = 1, | |
354 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
355 | .state_mem = { | |
356 | .disabled = 1, | |
357 | }, | |
358 | }, | |
359 | }; | |
360 | ||
361 | static struct regulator_init_data lp3974_ldo17_data = { | |
362 | .constraints = { | |
363 | .name = "VCC_3.0V_LCD", | |
364 | .min_uV = 3000000, | |
365 | .max_uV = 3000000, | |
366 | .apply_uV = 1, | |
367 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
368 | .boot_on = 1, | |
369 | .state_mem = { | |
370 | .disabled = 1, | |
371 | }, | |
372 | }, | |
373 | }; | |
374 | ||
375 | static struct regulator_init_data lp3974_32khz_ap_data = { | |
376 | .constraints = { | |
377 | .name = "32KHz AP", | |
378 | .always_on = 1, | |
379 | .state_mem = { | |
380 | .enabled = 1, | |
381 | }, | |
382 | }, | |
383 | }; | |
384 | ||
385 | static struct regulator_init_data lp3974_32khz_cp_data = { | |
386 | .constraints = { | |
387 | .name = "32KHz CP", | |
388 | .state_mem = { | |
389 | .disabled = 1, | |
390 | }, | |
391 | }, | |
392 | }; | |
393 | ||
394 | static struct regulator_init_data lp3974_vichg_data = { | |
395 | .constraints = { | |
396 | .name = "VICHG", | |
397 | .state_mem = { | |
398 | .disabled = 1, | |
399 | }, | |
400 | }, | |
401 | }; | |
402 | ||
403 | static struct regulator_init_data lp3974_esafeout1_data = { | |
404 | .constraints = { | |
405 | .name = "SAFEOUT1", | |
406 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
407 | .state_mem = { | |
408 | .enabled = 1, | |
409 | }, | |
410 | }, | |
411 | }; | |
412 | ||
413 | static struct regulator_init_data lp3974_esafeout2_data = { | |
414 | .constraints = { | |
415 | .name = "SAFEOUT2", | |
416 | .boot_on = 1, | |
417 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
418 | .state_mem = { | |
419 | .enabled = 1, | |
420 | }, | |
421 | }, | |
422 | }; | |
423 | ||
424 | static struct max8998_regulator_data lp3974_regulators[] = { | |
425 | { MAX8998_LDO2, &lp3974_ldo2_data }, | |
426 | { MAX8998_LDO3, &lp3974_ldo3_data }, | |
427 | { MAX8998_LDO4, &lp3974_ldo4_data }, | |
428 | { MAX8998_LDO5, &lp3974_ldo5_data }, | |
429 | { MAX8998_LDO6, &lp3974_ldo6_data }, | |
430 | { MAX8998_LDO7, &lp3974_ldo7_data }, | |
431 | { MAX8998_LDO8, &lp3974_ldo8_data }, | |
432 | { MAX8998_LDO9, &lp3974_ldo9_data }, | |
433 | { MAX8998_LDO10, &lp3974_ldo10_data }, | |
434 | { MAX8998_LDO11, &lp3974_ldo11_data }, | |
435 | { MAX8998_LDO12, &lp3974_ldo12_data }, | |
436 | { MAX8998_LDO13, &lp3974_ldo13_data }, | |
437 | { MAX8998_LDO14, &lp3974_ldo14_data }, | |
438 | { MAX8998_LDO15, &lp3974_ldo15_data }, | |
439 | { MAX8998_LDO16, &lp3974_ldo16_data }, | |
440 | { MAX8998_LDO17, &lp3974_ldo17_data }, | |
441 | { MAX8998_BUCK1, &lp3974_buck1_data }, | |
442 | { MAX8998_BUCK2, &lp3974_buck2_data }, | |
443 | { MAX8998_BUCK3, &lp3974_buck3_data }, | |
444 | { MAX8998_BUCK4, &lp3974_buck4_data }, | |
445 | { MAX8998_EN32KHZ_AP, &lp3974_32khz_ap_data }, | |
446 | { MAX8998_EN32KHZ_CP, &lp3974_32khz_cp_data }, | |
447 | { MAX8998_ENVICHG, &lp3974_vichg_data }, | |
448 | { MAX8998_ESAFEOUT1, &lp3974_esafeout1_data }, | |
449 | { MAX8998_ESAFEOUT2, &lp3974_esafeout2_data }, | |
450 | }; | |
451 | ||
452 | static struct max8998_platform_data universal_lp3974_pdata = { | |
453 | .num_regulators = ARRAY_SIZE(lp3974_regulators), | |
454 | .regulators = lp3974_regulators, | |
455 | .buck1_voltage1 = 1100000, /* INT */ | |
456 | .buck1_voltage2 = 1000000, | |
457 | .buck1_voltage3 = 1100000, | |
458 | .buck1_voltage4 = 1000000, | |
459 | .buck1_set1 = EXYNOS4_GPX0(5), | |
460 | .buck1_set2 = EXYNOS4_GPX0(6), | |
461 | .buck2_voltage1 = 1200000, /* G3D */ | |
462 | .buck2_voltage2 = 1100000, | |
463 | .buck1_default_idx = 0, | |
464 | .buck2_set3 = EXYNOS4_GPE2(0), | |
465 | .buck2_default_idx = 0, | |
466 | .wakeup = true, | |
467 | }; | |
468 | ||
469 | /* GPIO I2C 5 (PMIC) */ | |
470 | static struct i2c_board_info i2c5_devs[] __initdata = { | |
471 | { | |
472 | I2C_BOARD_INFO("max8952", 0xC0 >> 1), | |
473 | .platform_data = &universal_max8952_pdata, | |
474 | }, { | |
475 | I2C_BOARD_INFO("lp3974", 0xCC >> 1), | |
476 | .platform_data = &universal_lp3974_pdata, | |
477 | }, | |
478 | }; | |
479 | ||
480 | /* GPIO KEYS */ | |
34d79315 KP |
481 | static struct gpio_keys_button universal_gpio_keys_tables[] = { |
482 | { | |
483 | .code = KEY_VOLUMEUP, | |
d11135ca | 484 | .gpio = EXYNOS4_GPX2(0), /* XEINT16 */ |
34d79315 KP |
485 | .desc = "gpio-keys: KEY_VOLUMEUP", |
486 | .type = EV_KEY, | |
487 | .active_low = 1, | |
488 | .debounce_interval = 1, | |
489 | }, { | |
490 | .code = KEY_VOLUMEDOWN, | |
d11135ca | 491 | .gpio = EXYNOS4_GPX2(1), /* XEINT17 */ |
34d79315 KP |
492 | .desc = "gpio-keys: KEY_VOLUMEDOWN", |
493 | .type = EV_KEY, | |
494 | .active_low = 1, | |
495 | .debounce_interval = 1, | |
496 | }, { | |
497 | .code = KEY_CONFIG, | |
d11135ca | 498 | .gpio = EXYNOS4_GPX2(2), /* XEINT18 */ |
34d79315 KP |
499 | .desc = "gpio-keys: KEY_CONFIG", |
500 | .type = EV_KEY, | |
501 | .active_low = 1, | |
502 | .debounce_interval = 1, | |
503 | }, { | |
504 | .code = KEY_CAMERA, | |
d11135ca | 505 | .gpio = EXYNOS4_GPX2(3), /* XEINT19 */ |
34d79315 KP |
506 | .desc = "gpio-keys: KEY_CAMERA", |
507 | .type = EV_KEY, | |
508 | .active_low = 1, | |
509 | .debounce_interval = 1, | |
510 | }, { | |
511 | .code = KEY_OK, | |
d11135ca | 512 | .gpio = EXYNOS4_GPX3(5), /* XEINT29 */ |
34d79315 KP |
513 | .desc = "gpio-keys: KEY_OK", |
514 | .type = EV_KEY, | |
515 | .active_low = 1, | |
516 | .debounce_interval = 1, | |
517 | }, | |
518 | }; | |
519 | ||
520 | static struct gpio_keys_platform_data universal_gpio_keys_data = { | |
521 | .buttons = universal_gpio_keys_tables, | |
522 | .nbuttons = ARRAY_SIZE(universal_gpio_keys_tables), | |
523 | }; | |
524 | ||
525 | static struct platform_device universal_gpio_keys = { | |
526 | .name = "gpio-keys", | |
527 | .dev = { | |
528 | .platform_data = &universal_gpio_keys_data, | |
529 | }, | |
530 | }; | |
531 | ||
a8928ce7 KP |
532 | /* eMMC */ |
533 | static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = { | |
534 | .max_width = 8, | |
535 | .host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA | | |
536 | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | | |
537 | MMC_CAP_DISABLE), | |
538 | .cd_type = S3C_SDHCI_CD_PERMANENT, | |
539 | .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, | |
540 | }; | |
541 | ||
542 | static struct regulator_consumer_supply mmc0_supplies[] = { | |
543 | REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"), | |
544 | }; | |
545 | ||
546 | static struct regulator_init_data mmc0_fixed_voltage_init_data = { | |
547 | .constraints = { | |
548 | .name = "VMEM_VDD_2.8V", | |
549 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
550 | }, | |
551 | .num_consumer_supplies = ARRAY_SIZE(mmc0_supplies), | |
552 | .consumer_supplies = mmc0_supplies, | |
553 | }; | |
554 | ||
555 | static struct fixed_voltage_config mmc0_fixed_voltage_config = { | |
556 | .supply_name = "MASSMEMORY_EN", | |
557 | .microvolts = 2800000, | |
d11135ca | 558 | .gpio = EXYNOS4_GPE1(3), |
a8928ce7 KP |
559 | .enable_high = true, |
560 | .init_data = &mmc0_fixed_voltage_init_data, | |
561 | }; | |
562 | ||
563 | static struct platform_device mmc0_fixed_voltage = { | |
564 | .name = "reg-fixed-voltage", | |
565 | .id = 0, | |
566 | .dev = { | |
567 | .platform_data = &mmc0_fixed_voltage_config, | |
568 | }, | |
569 | }; | |
570 | ||
571 | /* SD */ | |
572 | static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = { | |
573 | .max_width = 4, | |
574 | .host_caps = MMC_CAP_4_BIT_DATA | | |
575 | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | | |
576 | MMC_CAP_DISABLE, | |
d11135ca | 577 | .ext_cd_gpio = EXYNOS4_GPX3(4), /* XEINT_28 */ |
a8928ce7 KP |
578 | .ext_cd_gpio_invert = 1, |
579 | .cd_type = S3C_SDHCI_CD_GPIO, | |
580 | .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, | |
581 | }; | |
582 | ||
583 | /* WiFi */ | |
584 | static struct s3c_sdhci_platdata universal_hsmmc3_data __initdata = { | |
585 | .max_width = 4, | |
586 | .host_caps = MMC_CAP_4_BIT_DATA | | |
587 | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | | |
588 | MMC_CAP_DISABLE, | |
589 | .cd_type = S3C_SDHCI_CD_EXTERNAL, | |
590 | }; | |
591 | ||
592 | static void __init universal_sdhci_init(void) | |
593 | { | |
594 | s3c_sdhci0_set_platdata(&universal_hsmmc0_data); | |
595 | s3c_sdhci2_set_platdata(&universal_hsmmc2_data); | |
596 | s3c_sdhci3_set_platdata(&universal_hsmmc3_data); | |
597 | } | |
598 | ||
3b7998f5 KP |
599 | /* I2C0 */ |
600 | static struct i2c_board_info i2c0_devs[] __initdata = { | |
601 | /* Camera, To be updated */ | |
602 | }; | |
603 | ||
604 | /* I2C1 */ | |
605 | static struct i2c_board_info i2c1_devs[] __initdata = { | |
606 | /* Gyro, To be updated */ | |
607 | }; | |
608 | ||
34d79315 | 609 | static struct platform_device *universal_devices[] __initdata = { |
a8928ce7 KP |
610 | /* Samsung Platform Devices */ |
611 | &mmc0_fixed_voltage, | |
612 | &s3c_device_hsmmc0, | |
613 | &s3c_device_hsmmc2, | |
614 | &s3c_device_hsmmc3, | |
4d838ec0 | 615 | &s3c_device_i2c5, |
a8928ce7 KP |
616 | |
617 | /* Universal Devices */ | |
34d79315 | 618 | &universal_gpio_keys, |
acf5eda9 | 619 | &s5p_device_onenand, |
34d79315 KP |
620 | }; |
621 | ||
516607d6 KP |
622 | static void __init universal_map_io(void) |
623 | { | |
624 | s5p_init_io(NULL, 0, S5P_VA_CHIPID); | |
625 | s3c24xx_init_clocks(24000000); | |
626 | s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs)); | |
627 | } | |
628 | ||
629 | static void __init universal_machine_init(void) | |
630 | { | |
a8928ce7 KP |
631 | universal_sdhci_init(); |
632 | ||
3b7998f5 KP |
633 | i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs)); |
634 | i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs)); | |
635 | ||
4d838ec0 MS |
636 | s3c_i2c5_set_platdata(NULL); |
637 | i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs)); | |
638 | ||
34d79315 KP |
639 | /* Last */ |
640 | platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices)); | |
516607d6 KP |
641 | } |
642 | ||
643 | MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210") | |
644 | /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */ | |
516607d6 | 645 | .boot_params = S5P_PA_SDRAM + 0x100, |
d11135ca | 646 | .init_irq = exynos4_init_irq, |
516607d6 KP |
647 | .map_io = universal_map_io, |
648 | .init_machine = universal_machine_init, | |
d11135ca | 649 | .timer = &exynos4_timer, |
516607d6 | 650 | MACHINE_END |