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30d8bead CY |
1 | /* linux/arch/arm/mach-exynos4/mct.c |
2 | * | |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com | |
5 | * | |
6 | * EXYNOS4 MCT(Multi-Core Timer) support | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/sched.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/irq.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/clk.h> | |
18 | #include <linux/clockchips.h> | |
19 | #include <linux/platform_device.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/percpu.h> | |
22 | ||
3a062281 CY |
23 | #include <asm/hardware/gic.h> |
24 | ||
25 | #include <plat/cpu.h> | |
26 | ||
30d8bead | 27 | #include <mach/map.h> |
3a062281 | 28 | #include <mach/irqs.h> |
30d8bead CY |
29 | #include <mach/regs-mct.h> |
30 | #include <asm/mach/time.h> | |
31 | ||
3a062281 CY |
32 | enum { |
33 | MCT_INT_SPI, | |
34 | MCT_INT_PPI | |
35 | }; | |
36 | ||
30d8bead CY |
37 | static unsigned long clk_cnt_per_tick; |
38 | static unsigned long clk_rate; | |
3a062281 | 39 | static unsigned int mct_int_type; |
30d8bead CY |
40 | |
41 | struct mct_clock_event_device { | |
42 | struct clock_event_device *evt; | |
43 | void __iomem *base; | |
44 | }; | |
45 | ||
46 | struct mct_clock_event_device mct_tick[2]; | |
47 | ||
48 | static void exynos4_mct_write(unsigned int value, void *addr) | |
49 | { | |
50 | void __iomem *stat_addr; | |
51 | u32 mask; | |
52 | u32 i; | |
53 | ||
54 | __raw_writel(value, addr); | |
55 | ||
56 | switch ((u32) addr) { | |
57 | case (u32) EXYNOS4_MCT_G_TCON: | |
58 | stat_addr = EXYNOS4_MCT_G_WSTAT; | |
59 | mask = 1 << 16; /* G_TCON write status */ | |
60 | break; | |
61 | case (u32) EXYNOS4_MCT_G_COMP0_L: | |
62 | stat_addr = EXYNOS4_MCT_G_WSTAT; | |
63 | mask = 1 << 0; /* G_COMP0_L write status */ | |
64 | break; | |
65 | case (u32) EXYNOS4_MCT_G_COMP0_U: | |
66 | stat_addr = EXYNOS4_MCT_G_WSTAT; | |
67 | mask = 1 << 1; /* G_COMP0_U write status */ | |
68 | break; | |
69 | case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR: | |
70 | stat_addr = EXYNOS4_MCT_G_WSTAT; | |
71 | mask = 1 << 2; /* G_COMP0_ADD_INCR write status */ | |
72 | break; | |
73 | case (u32) EXYNOS4_MCT_G_CNT_L: | |
74 | stat_addr = EXYNOS4_MCT_G_CNT_WSTAT; | |
75 | mask = 1 << 0; /* G_CNT_L write status */ | |
76 | break; | |
77 | case (u32) EXYNOS4_MCT_G_CNT_U: | |
78 | stat_addr = EXYNOS4_MCT_G_CNT_WSTAT; | |
79 | mask = 1 << 1; /* G_CNT_U write status */ | |
80 | break; | |
81 | case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_TCON_OFFSET): | |
82 | stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET; | |
83 | mask = 1 << 3; /* L0_TCON write status */ | |
84 | break; | |
85 | case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_TCON_OFFSET): | |
86 | stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET; | |
87 | mask = 1 << 3; /* L1_TCON write status */ | |
88 | break; | |
89 | case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_TCNTB_OFFSET): | |
90 | stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET; | |
91 | mask = 1 << 0; /* L0_TCNTB write status */ | |
92 | break; | |
93 | case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_TCNTB_OFFSET): | |
94 | stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET; | |
95 | mask = 1 << 0; /* L1_TCNTB write status */ | |
96 | break; | |
97 | case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_ICNTB_OFFSET): | |
98 | stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET; | |
99 | mask = 1 << 1; /* L0_ICNTB write status */ | |
100 | break; | |
101 | case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_ICNTB_OFFSET): | |
102 | stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET; | |
103 | mask = 1 << 1; /* L1_ICNTB write status */ | |
104 | break; | |
105 | default: | |
106 | return; | |
107 | } | |
108 | ||
109 | /* Wait maximum 1 ms until written values are applied */ | |
110 | for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++) | |
111 | if (__raw_readl(stat_addr) & mask) { | |
112 | __raw_writel(mask, stat_addr); | |
113 | return; | |
114 | } | |
115 | ||
116 | panic("MCT hangs after writing %d (addr:0x%08x)\n", value, (u32)addr); | |
117 | } | |
118 | ||
119 | /* Clocksource handling */ | |
120 | static void exynos4_mct_frc_start(u32 hi, u32 lo) | |
121 | { | |
122 | u32 reg; | |
123 | ||
124 | exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L); | |
125 | exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U); | |
126 | ||
127 | reg = __raw_readl(EXYNOS4_MCT_G_TCON); | |
128 | reg |= MCT_G_TCON_START; | |
129 | exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON); | |
130 | } | |
131 | ||
132 | static cycle_t exynos4_frc_read(struct clocksource *cs) | |
133 | { | |
134 | unsigned int lo, hi; | |
135 | u32 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U); | |
136 | ||
137 | do { | |
138 | hi = hi2; | |
139 | lo = __raw_readl(EXYNOS4_MCT_G_CNT_L); | |
140 | hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U); | |
141 | } while (hi != hi2); | |
142 | ||
143 | return ((cycle_t)hi << 32) | lo; | |
144 | } | |
145 | ||
aa421c13 CY |
146 | static void exynos4_frc_resume(struct clocksource *cs) |
147 | { | |
148 | exynos4_mct_frc_start(0, 0); | |
149 | } | |
150 | ||
30d8bead CY |
151 | struct clocksource mct_frc = { |
152 | .name = "mct-frc", | |
153 | .rating = 400, | |
154 | .read = exynos4_frc_read, | |
155 | .mask = CLOCKSOURCE_MASK(64), | |
156 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
aa421c13 | 157 | .resume = exynos4_frc_resume, |
30d8bead CY |
158 | }; |
159 | ||
160 | static void __init exynos4_clocksource_init(void) | |
161 | { | |
162 | exynos4_mct_frc_start(0, 0); | |
163 | ||
164 | if (clocksource_register_hz(&mct_frc, clk_rate)) | |
165 | panic("%s: can't register clocksource\n", mct_frc.name); | |
166 | } | |
167 | ||
168 | static void exynos4_mct_comp0_stop(void) | |
169 | { | |
170 | unsigned int tcon; | |
171 | ||
172 | tcon = __raw_readl(EXYNOS4_MCT_G_TCON); | |
173 | tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC); | |
174 | ||
175 | exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON); | |
176 | exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB); | |
177 | } | |
178 | ||
179 | static void exynos4_mct_comp0_start(enum clock_event_mode mode, | |
180 | unsigned long cycles) | |
181 | { | |
182 | unsigned int tcon; | |
183 | cycle_t comp_cycle; | |
184 | ||
185 | tcon = __raw_readl(EXYNOS4_MCT_G_TCON); | |
186 | ||
187 | if (mode == CLOCK_EVT_MODE_PERIODIC) { | |
188 | tcon |= MCT_G_TCON_COMP0_AUTO_INC; | |
189 | exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR); | |
190 | } | |
191 | ||
192 | comp_cycle = exynos4_frc_read(&mct_frc) + cycles; | |
193 | exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L); | |
194 | exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U); | |
195 | ||
196 | exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB); | |
197 | ||
198 | tcon |= MCT_G_TCON_COMP0_ENABLE; | |
199 | exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON); | |
200 | } | |
201 | ||
202 | static int exynos4_comp_set_next_event(unsigned long cycles, | |
203 | struct clock_event_device *evt) | |
204 | { | |
205 | exynos4_mct_comp0_start(evt->mode, cycles); | |
206 | ||
207 | return 0; | |
208 | } | |
209 | ||
210 | static void exynos4_comp_set_mode(enum clock_event_mode mode, | |
211 | struct clock_event_device *evt) | |
212 | { | |
213 | exynos4_mct_comp0_stop(); | |
214 | ||
215 | switch (mode) { | |
216 | case CLOCK_EVT_MODE_PERIODIC: | |
217 | exynos4_mct_comp0_start(mode, clk_cnt_per_tick); | |
218 | break; | |
219 | ||
220 | case CLOCK_EVT_MODE_ONESHOT: | |
221 | case CLOCK_EVT_MODE_UNUSED: | |
222 | case CLOCK_EVT_MODE_SHUTDOWN: | |
223 | case CLOCK_EVT_MODE_RESUME: | |
224 | break; | |
225 | } | |
226 | } | |
227 | ||
228 | static struct clock_event_device mct_comp_device = { | |
229 | .name = "mct-comp", | |
230 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
231 | .rating = 250, | |
232 | .set_next_event = exynos4_comp_set_next_event, | |
233 | .set_mode = exynos4_comp_set_mode, | |
234 | }; | |
235 | ||
236 | static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id) | |
237 | { | |
238 | struct clock_event_device *evt = dev_id; | |
239 | ||
240 | exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT); | |
241 | ||
242 | evt->event_handler(evt); | |
243 | ||
244 | return IRQ_HANDLED; | |
245 | } | |
246 | ||
247 | static struct irqaction mct_comp_event_irq = { | |
248 | .name = "mct_comp_irq", | |
249 | .flags = IRQF_TIMER | IRQF_IRQPOLL, | |
250 | .handler = exynos4_mct_comp_isr, | |
251 | .dev_id = &mct_comp_device, | |
252 | }; | |
253 | ||
254 | static void exynos4_clockevent_init(void) | |
255 | { | |
256 | clk_cnt_per_tick = clk_rate / 2 / HZ; | |
257 | ||
258 | clockevents_calc_mult_shift(&mct_comp_device, clk_rate / 2, 5); | |
259 | mct_comp_device.max_delta_ns = | |
260 | clockevent_delta2ns(0xffffffff, &mct_comp_device); | |
261 | mct_comp_device.min_delta_ns = | |
262 | clockevent_delta2ns(0xf, &mct_comp_device); | |
263 | mct_comp_device.cpumask = cpumask_of(0); | |
264 | clockevents_register_device(&mct_comp_device); | |
265 | ||
266 | setup_irq(IRQ_MCT_G0, &mct_comp_event_irq); | |
267 | } | |
268 | ||
269 | #ifdef CONFIG_LOCAL_TIMERS | |
270 | /* Clock event handling */ | |
271 | static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt) | |
272 | { | |
273 | unsigned long tmp; | |
274 | unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START; | |
275 | void __iomem *addr = mevt->base + MCT_L_TCON_OFFSET; | |
276 | ||
277 | tmp = __raw_readl(addr); | |
278 | if (tmp & mask) { | |
279 | tmp &= ~mask; | |
280 | exynos4_mct_write(tmp, addr); | |
281 | } | |
282 | } | |
283 | ||
284 | static void exynos4_mct_tick_start(unsigned long cycles, | |
285 | struct mct_clock_event_device *mevt) | |
286 | { | |
287 | unsigned long tmp; | |
288 | ||
289 | exynos4_mct_tick_stop(mevt); | |
290 | ||
291 | tmp = (1 << 31) | cycles; /* MCT_L_UPDATE_ICNTB */ | |
292 | ||
293 | /* update interrupt count buffer */ | |
294 | exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET); | |
295 | ||
25985edc | 296 | /* enable MCT tick interrupt */ |
30d8bead CY |
297 | exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET); |
298 | ||
299 | tmp = __raw_readl(mevt->base + MCT_L_TCON_OFFSET); | |
300 | tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START | | |
301 | MCT_L_TCON_INTERVAL_MODE; | |
302 | exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET); | |
303 | } | |
304 | ||
305 | static int exynos4_tick_set_next_event(unsigned long cycles, | |
306 | struct clock_event_device *evt) | |
307 | { | |
308 | struct mct_clock_event_device *mevt = &mct_tick[smp_processor_id()]; | |
309 | ||
310 | exynos4_mct_tick_start(cycles, mevt); | |
311 | ||
312 | return 0; | |
313 | } | |
314 | ||
315 | static inline void exynos4_tick_set_mode(enum clock_event_mode mode, | |
316 | struct clock_event_device *evt) | |
317 | { | |
318 | struct mct_clock_event_device *mevt = &mct_tick[smp_processor_id()]; | |
319 | ||
320 | exynos4_mct_tick_stop(mevt); | |
321 | ||
322 | switch (mode) { | |
323 | case CLOCK_EVT_MODE_PERIODIC: | |
324 | exynos4_mct_tick_start(clk_cnt_per_tick, mevt); | |
325 | break; | |
326 | ||
327 | case CLOCK_EVT_MODE_ONESHOT: | |
328 | case CLOCK_EVT_MODE_UNUSED: | |
329 | case CLOCK_EVT_MODE_SHUTDOWN: | |
330 | case CLOCK_EVT_MODE_RESUME: | |
331 | break; | |
332 | } | |
333 | } | |
334 | ||
3a062281 | 335 | static inline int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt) |
30d8bead | 336 | { |
30d8bead CY |
337 | struct clock_event_device *evt = mevt->evt; |
338 | ||
339 | /* | |
340 | * This is for supporting oneshot mode. | |
341 | * Mct would generate interrupt periodically | |
342 | * without explicit stopping. | |
343 | */ | |
344 | if (evt->mode != CLOCK_EVT_MODE_PERIODIC) | |
345 | exynos4_mct_tick_stop(mevt); | |
346 | ||
347 | /* Clear the MCT tick interrupt */ | |
3a062281 CY |
348 | if (__raw_readl(mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) { |
349 | exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET); | |
350 | return 1; | |
351 | } else { | |
352 | return 0; | |
353 | } | |
354 | } | |
355 | ||
356 | static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id) | |
357 | { | |
358 | struct mct_clock_event_device *mevt = dev_id; | |
359 | struct clock_event_device *evt = mevt->evt; | |
360 | ||
361 | exynos4_mct_tick_clear(mevt); | |
30d8bead CY |
362 | |
363 | evt->event_handler(evt); | |
364 | ||
365 | return IRQ_HANDLED; | |
366 | } | |
367 | ||
368 | static struct irqaction mct_tick0_event_irq = { | |
369 | .name = "mct_tick0_irq", | |
370 | .flags = IRQF_TIMER | IRQF_NOBALANCING, | |
371 | .handler = exynos4_mct_tick_isr, | |
372 | }; | |
373 | ||
374 | static struct irqaction mct_tick1_event_irq = { | |
375 | .name = "mct_tick1_irq", | |
376 | .flags = IRQF_TIMER | IRQF_NOBALANCING, | |
377 | .handler = exynos4_mct_tick_isr, | |
378 | }; | |
379 | ||
380 | static void exynos4_mct_tick_init(struct clock_event_device *evt) | |
381 | { | |
382 | unsigned int cpu = smp_processor_id(); | |
383 | ||
384 | mct_tick[cpu].evt = evt; | |
385 | ||
386 | if (cpu == 0) { | |
387 | mct_tick[cpu].base = EXYNOS4_MCT_L0_BASE; | |
388 | evt->name = "mct_tick0"; | |
389 | } else { | |
390 | mct_tick[cpu].base = EXYNOS4_MCT_L1_BASE; | |
391 | evt->name = "mct_tick1"; | |
392 | } | |
393 | ||
394 | evt->cpumask = cpumask_of(cpu); | |
395 | evt->set_next_event = exynos4_tick_set_next_event; | |
396 | evt->set_mode = exynos4_tick_set_mode; | |
397 | evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; | |
398 | evt->rating = 450; | |
399 | ||
400 | clockevents_calc_mult_shift(evt, clk_rate / 2, 5); | |
401 | evt->max_delta_ns = | |
402 | clockevent_delta2ns(0x7fffffff, evt); | |
403 | evt->min_delta_ns = | |
404 | clockevent_delta2ns(0xf, evt); | |
405 | ||
406 | clockevents_register_device(evt); | |
407 | ||
408 | exynos4_mct_write(0x1, mct_tick[cpu].base + MCT_L_TCNTB_OFFSET); | |
409 | ||
3a062281 CY |
410 | if (mct_int_type == MCT_INT_SPI) { |
411 | if (cpu == 0) { | |
412 | mct_tick0_event_irq.dev_id = &mct_tick[cpu]; | |
413 | setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq); | |
414 | } else { | |
415 | mct_tick1_event_irq.dev_id = &mct_tick[cpu]; | |
416 | setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq); | |
417 | irq_set_affinity(IRQ_MCT_L1, cpumask_of(1)); | |
418 | } | |
30d8bead | 419 | } else { |
3a062281 | 420 | gic_enable_ppi(IRQ_MCT_LOCALTIMER); |
30d8bead CY |
421 | } |
422 | } | |
423 | ||
424 | /* Setup the local clock events for a CPU */ | |
4d487d7e | 425 | int __cpuinit local_timer_setup(struct clock_event_device *evt) |
30d8bead CY |
426 | { |
427 | exynos4_mct_tick_init(evt); | |
4d487d7e KK |
428 | |
429 | return 0; | |
30d8bead CY |
430 | } |
431 | ||
432 | int local_timer_ack(void) | |
433 | { | |
3a062281 CY |
434 | unsigned int cpu = smp_processor_id(); |
435 | struct mct_clock_event_device *mevt = &mct_tick[cpu]; | |
436 | ||
437 | return exynos4_mct_tick_clear(mevt); | |
30d8bead CY |
438 | } |
439 | ||
440 | #endif /* CONFIG_LOCAL_TIMERS */ | |
441 | ||
442 | static void __init exynos4_timer_resources(void) | |
443 | { | |
444 | struct clk *mct_clk; | |
445 | mct_clk = clk_get(NULL, "xtal"); | |
446 | ||
447 | clk_rate = clk_get_rate(mct_clk); | |
448 | } | |
449 | ||
450 | static void __init exynos4_timer_init(void) | |
451 | { | |
3a062281 CY |
452 | if (soc_is_exynos4210()) |
453 | mct_int_type = MCT_INT_SPI; | |
454 | else | |
455 | mct_int_type = MCT_INT_PPI; | |
456 | ||
30d8bead CY |
457 | exynos4_timer_resources(); |
458 | exynos4_clocksource_init(); | |
459 | exynos4_clockevent_init(); | |
460 | } | |
461 | ||
462 | struct sys_timer exynos4_timer = { | |
463 | .init = exynos4_timer_init, | |
464 | }; |