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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mach-footbridge/common.c | |
3 | * | |
4 | * Copyright (C) 1998-2000 Russell King, Dave Gilbert. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
1da177e4 LT |
10 | #include <linux/module.h> |
11 | #include <linux/types.h> | |
12 | #include <linux/mm.h> | |
13 | #include <linux/ioport.h> | |
14 | #include <linux/list.h> | |
15 | #include <linux/init.h> | |
fced80c7 | 16 | #include <linux/io.h> |
70d13e08 | 17 | #include <linux/spinlock.h> |
8ef6e620 | 18 | |
1da177e4 LT |
19 | #include <asm/pgtable.h> |
20 | #include <asm/page.h> | |
21 | #include <asm/irq.h> | |
1da177e4 LT |
22 | #include <asm/mach-types.h> |
23 | #include <asm/setup.h> | |
9f97da78 | 24 | #include <asm/system_misc.h> |
1da177e4 LT |
25 | #include <asm/hardware/dec21285.h> |
26 | ||
27 | #include <asm/mach/irq.h> | |
28 | #include <asm/mach/map.h> | |
8ef6e620 | 29 | #include <asm/mach/pci.h> |
1da177e4 LT |
30 | |
31 | #include "common.h" | |
32 | ||
1da177e4 LT |
33 | unsigned int mem_fclk_21285 = 50000000; |
34 | ||
35 | EXPORT_SYMBOL(mem_fclk_21285); | |
36 | ||
2b0d8c25 | 37 | static int __init early_fclk(char *arg) |
613e09b4 | 38 | { |
2b0d8c25 JK |
39 | mem_fclk_21285 = simple_strtoul(arg, NULL, 0); |
40 | return 0; | |
613e09b4 RK |
41 | } |
42 | ||
2b0d8c25 | 43 | early_param("mem_fclk_21285", early_fclk); |
613e09b4 | 44 | |
1da177e4 LT |
45 | static int __init parse_tag_memclk(const struct tag *tag) |
46 | { | |
47 | mem_fclk_21285 = tag->u.memclk.fmemclk; | |
48 | return 0; | |
49 | } | |
50 | ||
51 | __tagtable(ATAG_MEMCLK, parse_tag_memclk); | |
52 | ||
53 | /* | |
54 | * Footbridge IRQ translation table | |
55 | * Converts from our IRQ numbers into FootBridge masks | |
56 | */ | |
57 | static const int fb_irq_mask[] = { | |
58 | IRQ_MASK_UART_RX, /* 0 */ | |
59 | IRQ_MASK_UART_TX, /* 1 */ | |
60 | IRQ_MASK_TIMER1, /* 2 */ | |
61 | IRQ_MASK_TIMER2, /* 3 */ | |
62 | IRQ_MASK_TIMER3, /* 4 */ | |
63 | IRQ_MASK_IN0, /* 5 */ | |
64 | IRQ_MASK_IN1, /* 6 */ | |
65 | IRQ_MASK_IN2, /* 7 */ | |
66 | IRQ_MASK_IN3, /* 8 */ | |
67 | IRQ_MASK_DOORBELLHOST, /* 9 */ | |
68 | IRQ_MASK_DMA1, /* 10 */ | |
69 | IRQ_MASK_DMA2, /* 11 */ | |
70 | IRQ_MASK_PCI, /* 12 */ | |
71 | IRQ_MASK_SDRAMPARITY, /* 13 */ | |
72 | IRQ_MASK_I2OINPOST, /* 14 */ | |
73 | IRQ_MASK_PCI_ABORT, /* 15 */ | |
74 | IRQ_MASK_PCI_SERR, /* 16 */ | |
75 | IRQ_MASK_DISCARD_TIMER, /* 17 */ | |
76 | IRQ_MASK_PCI_DPERR, /* 18 */ | |
77 | IRQ_MASK_PCI_PERR, /* 19 */ | |
78 | }; | |
79 | ||
dc2caf6c | 80 | static void fb_mask_irq(struct irq_data *d) |
1da177e4 | 81 | { |
dc2caf6c | 82 | *CSR_IRQ_DISABLE = fb_irq_mask[_DC21285_INR(d->irq)]; |
1da177e4 LT |
83 | } |
84 | ||
dc2caf6c | 85 | static void fb_unmask_irq(struct irq_data *d) |
1da177e4 | 86 | { |
dc2caf6c | 87 | *CSR_IRQ_ENABLE = fb_irq_mask[_DC21285_INR(d->irq)]; |
1da177e4 LT |
88 | } |
89 | ||
10dd5ce2 | 90 | static struct irq_chip fb_chip = { |
dc2caf6c LB |
91 | .irq_ack = fb_mask_irq, |
92 | .irq_mask = fb_mask_irq, | |
93 | .irq_unmask = fb_unmask_irq, | |
1da177e4 LT |
94 | }; |
95 | ||
96 | static void __init __fb_init_irq(void) | |
97 | { | |
98 | unsigned int irq; | |
99 | ||
100 | /* | |
101 | * setup DC21285 IRQs | |
102 | */ | |
103 | *CSR_IRQ_DISABLE = -1; | |
104 | *CSR_FIQ_DISABLE = -1; | |
105 | ||
106 | for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) { | |
f38c02f3 | 107 | irq_set_chip_and_handler(irq, &fb_chip, handle_level_irq); |
1da177e4 LT |
108 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
109 | } | |
110 | } | |
111 | ||
112 | void __init footbridge_init_irq(void) | |
113 | { | |
114 | __fb_init_irq(); | |
115 | ||
116 | if (!footbridge_cfn_mode()) | |
117 | return; | |
118 | ||
119 | if (machine_is_ebsa285()) | |
120 | /* The following is dependent on which slot | |
121 | * you plug the Southbridge card into. We | |
122 | * currently assume that you plug it into | |
123 | * the right-hand most slot. | |
124 | */ | |
125 | isa_init_irq(IRQ_PCI); | |
126 | ||
127 | if (machine_is_cats()) | |
128 | isa_init_irq(IRQ_IN2); | |
129 | ||
130 | if (machine_is_netwinder()) | |
131 | isa_init_irq(IRQ_IN3); | |
132 | } | |
133 | ||
134 | /* | |
135 | * Common mapping for all systems. Note that the outbound write flush is | |
136 | * commented out since there is a "No Fix" problem with it. Not mapping | |
137 | * it means that we have extra bullet protection on our feet. | |
138 | */ | |
139 | static struct map_desc fb_common_io_desc[] __initdata = { | |
a427ceef DS |
140 | { |
141 | .virtual = ARMCSR_BASE, | |
865052fd | 142 | .pfn = __phys_to_pfn(DC21285_ARMCSR_BASE), |
a427ceef | 143 | .length = ARMCSR_SIZE, |
6460177f | 144 | .type = MT_DEVICE, |
a427ceef DS |
145 | }, { |
146 | .virtual = XBUS_BASE, | |
147 | .pfn = __phys_to_pfn(0x40000000), | |
148 | .length = XBUS_SIZE, | |
6460177f | 149 | .type = MT_DEVICE, |
a427ceef | 150 | } |
1da177e4 LT |
151 | }; |
152 | ||
153 | /* | |
154 | * The mapping when the footbridge is in host mode. We don't map any of | |
155 | * this when we are in add-in mode. | |
156 | */ | |
157 | static struct map_desc ebsa285_host_io_desc[] __initdata = { | |
158 | #if defined(CONFIG_ARCH_FOOTBRIDGE) && defined(CONFIG_FOOTBRIDGE_HOST) | |
a427ceef DS |
159 | { |
160 | .virtual = PCIMEM_BASE, | |
161 | .pfn = __phys_to_pfn(DC21285_PCI_MEM), | |
162 | .length = PCIMEM_SIZE, | |
6460177f | 163 | .type = MT_DEVICE, |
a427ceef DS |
164 | }, { |
165 | .virtual = PCICFG0_BASE, | |
166 | .pfn = __phys_to_pfn(DC21285_PCI_TYPE_0_CONFIG), | |
167 | .length = PCICFG0_SIZE, | |
6460177f | 168 | .type = MT_DEVICE, |
a427ceef DS |
169 | }, { |
170 | .virtual = PCICFG1_BASE, | |
171 | .pfn = __phys_to_pfn(DC21285_PCI_TYPE_1_CONFIG), | |
172 | .length = PCICFG1_SIZE, | |
6460177f | 173 | .type = MT_DEVICE, |
a427ceef DS |
174 | }, { |
175 | .virtual = PCIIACK_BASE, | |
176 | .pfn = __phys_to_pfn(DC21285_PCI_IACK), | |
177 | .length = PCIIACK_SIZE, | |
6460177f | 178 | .type = MT_DEVICE, |
6460177f | 179 | }, |
1da177e4 LT |
180 | #endif |
181 | }; | |
182 | ||
1da177e4 LT |
183 | void __init footbridge_map_io(void) |
184 | { | |
185 | /* | |
186 | * Set up the common mapping first; we need this to | |
187 | * determine whether we're in host mode or not. | |
188 | */ | |
189 | iotable_init(fb_common_io_desc, ARRAY_SIZE(fb_common_io_desc)); | |
190 | ||
191 | /* | |
192 | * Now, work out what we've got to map in addition on this | |
193 | * platform. | |
194 | */ | |
8ef6e620 | 195 | if (footbridge_cfn_mode()) { |
1da177e4 | 196 | iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc)); |
8ef6e620 RH |
197 | pci_map_io_early(__phys_to_pfn(DC21285_PCI_IO)); |
198 | } | |
1da177e4 LT |
199 | } |
200 | ||
7b6d864b | 201 | void footbridge_restart(enum reboot_mode mode, const char *cmd) |
6fca1e17 | 202 | { |
7b6d864b | 203 | if (mode == REBOOT_SOFT) { |
6fca1e17 RK |
204 | /* Jump into the ROM */ |
205 | soft_restart(0x41000000); | |
206 | } else { | |
207 | /* | |
208 | * Force the watchdog to do a CPU reset. | |
209 | * | |
210 | * After making sure that the watchdog is disabled | |
211 | * (so we can change the timer registers) we first | |
212 | * enable the timer to autoreload itself. Next, the | |
213 | * timer interval is set really short and any | |
214 | * current interrupt request is cleared (so we can | |
215 | * see an edge transition). Finally, TIMER4 is | |
216 | * enabled as the watchdog. | |
217 | */ | |
218 | *CSR_SA110_CNTL &= ~(1 << 13); | |
219 | *CSR_TIMER4_CNTL = TIMER_CNTL_ENABLE | | |
220 | TIMER_CNTL_AUTORELOAD | | |
221 | TIMER_CNTL_DIV16; | |
222 | *CSR_TIMER4_LOAD = 0x2; | |
223 | *CSR_TIMER4_CLR = 0; | |
224 | *CSR_SA110_CNTL |= (1 << 13); | |
225 | } | |
226 | } | |
227 | ||
1da177e4 LT |
228 | #ifdef CONFIG_FOOTBRIDGE_ADDIN |
229 | ||
c7baab5d RK |
230 | static inline unsigned long fb_bus_sdram_offset(void) |
231 | { | |
232 | return *CSR_PCISDRAMBASE & 0xfffffff0; | |
233 | } | |
234 | ||
1da177e4 LT |
235 | /* |
236 | * These two functions convert virtual addresses to PCI addresses and PCI | |
237 | * addresses to virtual addresses. Note that it is only legal to use these | |
238 | * on memory obtained via get_zeroed_page or kmalloc. | |
239 | */ | |
240 | unsigned long __virt_to_bus(unsigned long res) | |
241 | { | |
242 | WARN_ON(res < PAGE_OFFSET || res >= (unsigned long)high_memory); | |
243 | ||
c7baab5d | 244 | return res + (fb_bus_sdram_offset() - PAGE_OFFSET); |
1da177e4 LT |
245 | } |
246 | EXPORT_SYMBOL(__virt_to_bus); | |
247 | ||
248 | unsigned long __bus_to_virt(unsigned long res) | |
249 | { | |
c7baab5d | 250 | res = res - (fb_bus_sdram_offset() - PAGE_OFFSET); |
1da177e4 LT |
251 | |
252 | WARN_ON(res < PAGE_OFFSET || res >= (unsigned long)high_memory); | |
253 | ||
254 | return res; | |
255 | } | |
256 | EXPORT_SYMBOL(__bus_to_virt); | |
257 | ||
c7baab5d RK |
258 | unsigned long __pfn_to_bus(unsigned long pfn) |
259 | { | |
64dd3b74 | 260 | return __pfn_to_phys(pfn) + (fb_bus_sdram_offset() - PHYS_OFFSET); |
c7baab5d RK |
261 | } |
262 | EXPORT_SYMBOL(__pfn_to_bus); | |
263 | ||
264 | unsigned long __bus_to_pfn(unsigned long bus) | |
265 | { | |
266 | return __phys_to_pfn(bus - (fb_bus_sdram_offset() - PHYS_OFFSET)); | |
267 | } | |
268 | EXPORT_SYMBOL(__bus_to_pfn); | |
269 | ||
1da177e4 | 270 | #endif |