[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-footbridge / dc21285-timer.c

/*
 *  linux/arch/arm/mach-footbridge/dc21285-timer.c
 *
 *  Copyright (C) 1998 Russell King.
 *  Copyright (C) 1998 Phil Blundell
 */
#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/sched_clock.h>

#include <asm/irq.h>

#include <asm/hardware/dec21285.h>
#include <asm/mach/time.h>
#include <asm/system_info.h>

#include "common.h"

static cycle_t cksrc_dc21285_read(struct clocksource *cs)
{
	return cs->mask - *CSR_TIMER2_VALUE;
}

static int cksrc_dc21285_enable(struct clocksource *cs)
{
	*CSR_TIMER2_LOAD = cs->mask;
	*CSR_TIMER2_CLR = 0;
	*CSR_TIMER2_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16;
	return 0;
}

static void cksrc_dc21285_disable(struct clocksource *cs)
{
	*CSR_TIMER2_CNTL = 0;
}

static struct clocksource cksrc_dc21285 = {
	.name		= "dc21285_timer2",
	.rating		= 200,
	.read		= cksrc_dc21285_read,
	.enable		= cksrc_dc21285_enable,
	.disable	= cksrc_dc21285_disable,
	.mask		= CLOCKSOURCE_MASK(24),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};

static int ckevt_dc21285_set_next_event(unsigned long delta,
	struct clock_event_device *c)
{
	*CSR_TIMER1_CLR = 0;
	*CSR_TIMER1_LOAD = delta;
	*CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16;

	return 0;
}

static void ckevt_dc21285_set_mode(enum clock_event_mode mode,
	struct clock_event_device *c)
{
	switch (mode) {
	case CLOCK_EVT_MODE_RESUME:
	case CLOCK_EVT_MODE_PERIODIC:
		*CSR_TIMER1_CLR = 0;
		*CSR_TIMER1_LOAD = (mem_fclk_21285 + 8 * HZ) / (16 * HZ);
		*CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_AUTORELOAD |
				   TIMER_CNTL_DIV16;
		break;

	case CLOCK_EVT_MODE_ONESHOT:
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		*CSR_TIMER1_CNTL = 0;
		break;
	}
}

static struct clock_event_device ckevt_dc21285 = {
	.name		= "dc21285_timer1",
	.features	= CLOCK_EVT_FEAT_PERIODIC |
			  CLOCK_EVT_FEAT_ONESHOT,
	.rating		= 200,
	.irq		= IRQ_TIMER1,
	.set_next_event	= ckevt_dc21285_set_next_event,
	.set_mode	= ckevt_dc21285_set_mode,
};

static irqreturn_t timer1_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *ce = dev_id;

	*CSR_TIMER1_CLR = 0;

	/* Stop the timer if in one-shot mode */
	if (ce->mode == CLOCK_EVT_MODE_ONESHOT)
		*CSR_TIMER1_CNTL = 0;

	ce->event_handler(ce);

	return IRQ_HANDLED;
}

static struct irqaction footbridge_timer_irq = {
	.name		= "dc21285_timer1",
	.handler	= timer1_interrupt,
	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
	.dev_id		= &ckevt_dc21285,
};

/*
 * Set up timer interrupt.
 */
void __init footbridge_timer_init(void)
{
	struct clock_event_device *ce = &ckevt_dc21285;
	unsigned rate = DIV_ROUND_CLOSEST(mem_fclk_21285, 16);

	clocksource_register_hz(&cksrc_dc21285, rate);

	setup_irq(ce->irq, &footbridge_timer_irq);

	ce->cpumask = cpumask_of(smp_processor_id());
	clockevents_config_and_register(ce, rate, 0x4, 0xffffff);
}

static u64 notrace footbridge_read_sched_clock(void)
{
	return ~*CSR_TIMER3_VALUE;
}

void __init footbridge_sched_clock(void)
{
	unsigned rate = DIV_ROUND_CLOSEST(mem_fclk_21285, 16);

	*CSR_TIMER3_LOAD = 0;
	*CSR_TIMER3_CLR = 0;
	*CSR_TIMER3_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16;

	sched_clock_register(footbridge_read_sched_clock, 24, rate);
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-footbridge/dc21285-timer.c
	3	*
	4	* Copyright (C) 1998 Russell King.
	5	* Copyright (C) 1998 Phil Blundell
	6	*/
4e8d7637 RK	7	#include <linux/clockchips.h>
4e8d7637 RK	8	#include <linux/clocksource.h>
1da177e4 LT	9	#include <linux/init.h>
1da177e4 LT	10	#include <linux/interrupt.h>
55e86989	11	#include <linux/irq.h>
6cefe92f	12	#include <linux/sched_clock.h>
1da177e4 LT	13
	14	#include <asm/irq.h>
	15
	16	#include <asm/hardware/dec21285.h>
	17	#include <asm/mach/time.h>
9f97da78	18	#include <asm/system_info.h>
1da177e4 LT	19
	20	#include "common.h"
	21
4e8d7637 RK	22	static cycle_t cksrc_dc21285_read(struct clocksource *cs)
	23	{
	24	return cs->mask - *CSR_TIMER2_VALUE;
	25	}
1da177e4	26
4e8d7637	27	static int cksrc_dc21285_enable(struct clocksource *cs)
1da177e4	28	{
4e8d7637 RK	29	*CSR_TIMER2_LOAD = cs->mask;
	30	*CSR_TIMER2_CLR = 0;
	31	*CSR_TIMER2_CNTL = TIMER_CNTL_ENABLE \| TIMER_CNTL_DIV16;
	32	return 0;
	33	}
1da177e4	34
f2e0bf21	35	static void cksrc_dc21285_disable(struct clocksource *cs)
4e8d7637 RK	36	{
4e8d7637 RK	37	*CSR_TIMER2_CNTL = 0;
1da177e4 LT	38	}
1da177e4 LT	39
4e8d7637 RK	40	static struct clocksource cksrc_dc21285 = {
	41	.name = "dc21285_timer2",
	42	.rating = 200,
	43	.read = cksrc_dc21285_read,
	44	.enable = cksrc_dc21285_enable,
	45	.disable = cksrc_dc21285_disable,
	46	.mask = CLOCKSOURCE_MASK(24),
	47	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	48	};
	49
4808972a RK	50	static int ckevt_dc21285_set_next_event(unsigned long delta,
	51	struct clock_event_device *c)
	52	{
	53	*CSR_TIMER1_CLR = 0;
	54	*CSR_TIMER1_LOAD = delta;
	55	*CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE \| TIMER_CNTL_DIV16;
	56
	57	return 0;
	58	}
	59
4e8d7637 RK	60	static void ckevt_dc21285_set_mode(enum clock_event_mode mode,
4e8d7637 RK	61	struct clock_event_device *c)
1da177e4	62	{
4e8d7637 RK	63	switch (mode) {
	64	case CLOCK_EVT_MODE_RESUME:
	65	case CLOCK_EVT_MODE_PERIODIC:
	66	*CSR_TIMER1_CLR = 0;
	67	CSR_TIMER1_LOAD = (mem_fclk_21285 + 8 HZ) / (16 * HZ);
	68	*CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE \| TIMER_CNTL_AUTORELOAD \|
	69	TIMER_CNTL_DIV16;
	70	break;
	71
4808972a RK	72	case CLOCK_EVT_MODE_ONESHOT:
	73	case CLOCK_EVT_MODE_UNUSED:
	74	case CLOCK_EVT_MODE_SHUTDOWN:
4e8d7637 RK	75	*CSR_TIMER1_CNTL = 0;
	76	break;
	77	}
	78	}
	79
	80	static struct clock_event_device ckevt_dc21285 = {
	81	.name = "dc21285_timer1",
4808972a RK	82	.features = CLOCK_EVT_FEAT_PERIODIC \|
4808972a RK	83	CLOCK_EVT_FEAT_ONESHOT,
4e8d7637 RK	84	.rating = 200,
4e8d7637 RK	85	.irq = IRQ_TIMER1,
4808972a	86	.set_next_event = ckevt_dc21285_set_next_event,
4e8d7637 RK	87	.set_mode = ckevt_dc21285_set_mode,
	88	};
	89
	90	static irqreturn_t timer1_interrupt(int irq, void *dev_id)
	91	{
	92	struct clock_event_device *ce = dev_id;
	93
1da177e4 LT	94	*CSR_TIMER1_CLR = 0;
1da177e4 LT	95
4808972a RK	96	/* Stop the timer if in one-shot mode */
	97	if (ce->mode == CLOCK_EVT_MODE_ONESHOT)
	98	*CSR_TIMER1_CNTL = 0;
	99
4e8d7637	100	ce->event_handler(ce);
1da177e4	101
1da177e4 LT	102	return IRQ_HANDLED;
	103	}
	104
	105	static struct irqaction footbridge_timer_irq = {
4e8d7637	106	.name = "dc21285_timer1",
1da177e4	107	.handler = timer1_interrupt,
26632bec	108	.flags = IRQF_TIMER \| IRQF_IRQPOLL,
4e8d7637	109	.dev_id = &ckevt_dc21285,
1da177e4 LT	110	};
	111
	112	/*
	113	* Set up timer interrupt.
	114	*/
6bb27d73	115	void __init footbridge_timer_init(void)
1da177e4	116	{
4e8d7637	117	struct clock_event_device *ce = &ckevt_dc21285;
4ff859fe	118	unsigned rate = DIV_ROUND_CLOSEST(mem_fclk_21285, 16);
4e8d7637	119
4ff859fe	120	clocksource_register_hz(&cksrc_dc21285, rate);
4e8d7637 RK	121
4e8d7637 RK	122	setup_irq(ce->irq, &footbridge_timer_irq);
1da177e4	123
7d7975a0	124	ce->cpumask = cpumask_of(smp_processor_id());
4ff859fe	125	clockevents_config_and_register(ce, rate, 0x4, 0xffffff);
1da177e4	126	}
6cefe92f	127
889f172d	128	static u64 notrace footbridge_read_sched_clock(void)
6cefe92f RK	129	{
	130	return ~*CSR_TIMER3_VALUE;
	131	}
	132
	133	void __init footbridge_sched_clock(void)
	134	{
	135	unsigned rate = DIV_ROUND_CLOSEST(mem_fclk_21285, 16);
	136
	137	*CSR_TIMER3_LOAD = 0;
	138	*CSR_TIMER3_CLR = 0;
	139	*CSR_TIMER3_CNTL = TIMER_CNTL_ENABLE \| TIMER_CNTL_DIV16;
	140
889f172d	141	sched_clock_register(footbridge_read_sched_clock, 24, rate);
1da177e4	142	}