[mirror_ubuntu-bionic-kernel.git] / arch / arm / mach-footbridge / dc21285-timer.c

// SPDX-License-Identifier: GPL-2.0
/*
 *  linux/arch/arm/mach-footbridge/dc21285-timer.c
 *
 *  Copyright (C) 1998 Russell King.
 *  Copyright (C) 1998 Phil Blundell
 */
#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/sched_clock.h>

#include <asm/irq.h>

#include <asm/hardware/dec21285.h>
#include <asm/mach/time.h>
#include <asm/system_info.h>

#include "common.h"

static u64 cksrc_dc21285_read(struct clocksource *cs)
{
	return cs->mask - *CSR_TIMER2_VALUE;
}

static int cksrc_dc21285_enable(struct clocksource *cs)
{
	*CSR_TIMER2_LOAD = cs->mask;
	*CSR_TIMER2_CLR = 0;
	*CSR_TIMER2_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16;
	return 0;
}

static void cksrc_dc21285_disable(struct clocksource *cs)
{
	*CSR_TIMER2_CNTL = 0;
}

static struct clocksource cksrc_dc21285 = {
	.name		= "dc21285_timer2",
	.rating		= 200,
	.read		= cksrc_dc21285_read,
	.enable		= cksrc_dc21285_enable,
	.disable	= cksrc_dc21285_disable,
	.mask		= CLOCKSOURCE_MASK(24),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};

static int ckevt_dc21285_set_next_event(unsigned long delta,
	struct clock_event_device *c)
{
	*CSR_TIMER1_CLR = 0;
	*CSR_TIMER1_LOAD = delta;
	*CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16;

	return 0;
}

static int ckevt_dc21285_shutdown(struct clock_event_device *c)
{
	*CSR_TIMER1_CNTL = 0;
	return 0;
}

static int ckevt_dc21285_set_periodic(struct clock_event_device *c)
{
	*CSR_TIMER1_CLR = 0;
	*CSR_TIMER1_LOAD = (mem_fclk_21285 + 8 * HZ) / (16 * HZ);
	*CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_AUTORELOAD |
			   TIMER_CNTL_DIV16;
	return 0;
}

static struct clock_event_device ckevt_dc21285 = {
	.name			= "dc21285_timer1",
	.features		= CLOCK_EVT_FEAT_PERIODIC |
				  CLOCK_EVT_FEAT_ONESHOT,
	.rating			= 200,
	.irq			= IRQ_TIMER1,
	.set_next_event		= ckevt_dc21285_set_next_event,
	.set_state_shutdown	= ckevt_dc21285_shutdown,
	.set_state_periodic	= ckevt_dc21285_set_periodic,
	.set_state_oneshot	= ckevt_dc21285_shutdown,
	.tick_resume		= ckevt_dc21285_set_periodic,
};

static irqreturn_t timer1_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *ce = dev_id;

	*CSR_TIMER1_CLR = 0;

	/* Stop the timer if in one-shot mode */
	if (clockevent_state_oneshot(ce))
		*CSR_TIMER1_CNTL = 0;

	ce->event_handler(ce);

	return IRQ_HANDLED;
}

static struct irqaction footbridge_timer_irq = {
	.name		= "dc21285_timer1",
	.handler	= timer1_interrupt,
	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
	.dev_id		= &ckevt_dc21285,
};

/*
 * Set up timer interrupt.
 */
void __init footbridge_timer_init(void)
{
	struct clock_event_device *ce = &ckevt_dc21285;
	unsigned rate = DIV_ROUND_CLOSEST(mem_fclk_21285, 16);

	clocksource_register_hz(&cksrc_dc21285, rate);

	setup_irq(ce->irq, &footbridge_timer_irq);

	ce->cpumask = cpumask_of(smp_processor_id());
	clockevents_config_and_register(ce, rate, 0x4, 0xffffff);
}

static u64 notrace footbridge_read_sched_clock(void)
{
	return ~*CSR_TIMER3_VALUE;
}

void __init footbridge_sched_clock(void)
{
	unsigned rate = DIV_ROUND_CLOSEST(mem_fclk_21285, 16);

	*CSR_TIMER3_LOAD = 0;
	*CSR_TIMER3_CLR = 0;
	*CSR_TIMER3_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16;

	sched_clock_register(footbridge_read_sched_clock, 24, rate);
}
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
1da177e4 LT	2	/*
	3	* linux/arch/arm/mach-footbridge/dc21285-timer.c
	4	*
	5	* Copyright (C) 1998 Russell King.
	6	* Copyright (C) 1998 Phil Blundell
	7	*/
4e8d7637 RK	8	#include <linux/clockchips.h>
4e8d7637 RK	9	#include <linux/clocksource.h>
1da177e4 LT	10	#include <linux/init.h>
1da177e4 LT	11	#include <linux/interrupt.h>
55e86989	12	#include <linux/irq.h>
6cefe92f	13	#include <linux/sched_clock.h>
1da177e4 LT	14
	15	#include <asm/irq.h>
	16
	17	#include <asm/hardware/dec21285.h>
	18	#include <asm/mach/time.h>
9f97da78	19	#include <asm/system_info.h>
1da177e4 LT	20
	21	#include "common.h"
	22
a5a1d1c2	23	static u64 cksrc_dc21285_read(struct clocksource *cs)
4e8d7637 RK	24	{
	25	return cs->mask - *CSR_TIMER2_VALUE;
	26	}
1da177e4	27
4e8d7637	28	static int cksrc_dc21285_enable(struct clocksource *cs)
1da177e4	29	{
4e8d7637 RK	30	*CSR_TIMER2_LOAD = cs->mask;
	31	*CSR_TIMER2_CLR = 0;
	32	*CSR_TIMER2_CNTL = TIMER_CNTL_ENABLE \| TIMER_CNTL_DIV16;
	33	return 0;
	34	}
1da177e4	35
f2e0bf21	36	static void cksrc_dc21285_disable(struct clocksource *cs)
4e8d7637 RK	37	{
4e8d7637 RK	38	*CSR_TIMER2_CNTL = 0;
1da177e4 LT	39	}
1da177e4 LT	40
4e8d7637 RK	41	static struct clocksource cksrc_dc21285 = {
	42	.name = "dc21285_timer2",
	43	.rating = 200,
	44	.read = cksrc_dc21285_read,
	45	.enable = cksrc_dc21285_enable,
	46	.disable = cksrc_dc21285_disable,
	47	.mask = CLOCKSOURCE_MASK(24),
	48	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	49	};
	50
4808972a RK	51	static int ckevt_dc21285_set_next_event(unsigned long delta,
	52	struct clock_event_device *c)
	53	{
	54	*CSR_TIMER1_CLR = 0;
	55	*CSR_TIMER1_LOAD = delta;
	56	*CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE \| TIMER_CNTL_DIV16;
	57
	58	return 0;
	59	}
	60
947d9cf5	61	static int ckevt_dc21285_shutdown(struct clock_event_device *c)
1da177e4	62	{
947d9cf5 VK	63	*CSR_TIMER1_CNTL = 0;
	64	return 0;
	65	}
	66
	67	static int ckevt_dc21285_set_periodic(struct clock_event_device *c)
	68	{
	69	*CSR_TIMER1_CLR = 0;
	70	CSR_TIMER1_LOAD = (mem_fclk_21285 + 8 HZ) / (16 * HZ);
	71	*CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE \| TIMER_CNTL_AUTORELOAD \|
	72	TIMER_CNTL_DIV16;
	73	return 0;
4e8d7637 RK	74	}
	75
	76	static struct clock_event_device ckevt_dc21285 = {
947d9cf5 VK	77	.name = "dc21285_timer1",
	78	.features = CLOCK_EVT_FEAT_PERIODIC \|
	79	CLOCK_EVT_FEAT_ONESHOT,
	80	.rating = 200,
	81	.irq = IRQ_TIMER1,
	82	.set_next_event = ckevt_dc21285_set_next_event,
	83	.set_state_shutdown = ckevt_dc21285_shutdown,
	84	.set_state_periodic = ckevt_dc21285_set_periodic,
	85	.set_state_oneshot = ckevt_dc21285_shutdown,
	86	.tick_resume = ckevt_dc21285_set_periodic,
4e8d7637 RK	87	};
	88
	89	static irqreturn_t timer1_interrupt(int irq, void *dev_id)
	90	{
	91	struct clock_event_device *ce = dev_id;
	92
1da177e4 LT	93	*CSR_TIMER1_CLR = 0;
1da177e4 LT	94
4808972a	95	/* Stop the timer if in one-shot mode */
947d9cf5	96	if (clockevent_state_oneshot(ce))
4808972a RK	97	*CSR_TIMER1_CNTL = 0;
4808972a RK	98
4e8d7637	99	ce->event_handler(ce);
1da177e4	100
1da177e4 LT	101	return IRQ_HANDLED;
	102	}
	103
	104	static struct irqaction footbridge_timer_irq = {
4e8d7637	105	.name = "dc21285_timer1",
1da177e4	106	.handler = timer1_interrupt,
26632bec	107	.flags = IRQF_TIMER \| IRQF_IRQPOLL,
4e8d7637	108	.dev_id = &ckevt_dc21285,
1da177e4 LT	109	};
	110
	111	/*
	112	* Set up timer interrupt.
	113	*/
6bb27d73	114	void __init footbridge_timer_init(void)
1da177e4	115	{
4e8d7637	116	struct clock_event_device *ce = &ckevt_dc21285;
4ff859fe	117	unsigned rate = DIV_ROUND_CLOSEST(mem_fclk_21285, 16);
4e8d7637	118
4ff859fe	119	clocksource_register_hz(&cksrc_dc21285, rate);
4e8d7637 RK	120
4e8d7637 RK	121	setup_irq(ce->irq, &footbridge_timer_irq);
1da177e4	122
7d7975a0	123	ce->cpumask = cpumask_of(smp_processor_id());
4ff859fe	124	clockevents_config_and_register(ce, rate, 0x4, 0xffffff);
1da177e4	125	}
6cefe92f	126
889f172d	127	static u64 notrace footbridge_read_sched_clock(void)
6cefe92f RK	128	{
	129	return ~*CSR_TIMER3_VALUE;
	130	}
	131
	132	void __init footbridge_sched_clock(void)
	133	{
	134	unsigned rate = DIV_ROUND_CLOSEST(mem_fclk_21285, 16);
	135
	136	*CSR_TIMER3_LOAD = 0;
	137	*CSR_TIMER3_CLR = 0;
	138	*CSR_TIMER3_CNTL = TIMER_CNTL_ENABLE \| TIMER_CNTL_DIV16;
	139
889f172d	140	sched_clock_register(footbridge_read_sched_clock, 24, rate);
1da177e4	141	}