[mirror_ubuntu-focal-kernel.git] / arch / arm / mach-h720x / cpu-h7202.c

/*
 * linux/arch/arm/mach-h720x/cpu-h7202.c
 *
 * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
 *               2003 Robert Schwebel <r.schwebel@pengutronix.de>
 *               2004 Sascha Hauer    <s.hauer@pengutronix.de>
 *
 * processor specific stuff for the Hynix h7202
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <asm/types.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <mach/irqs.h>
#include <asm/mach/irq.h>
#include <asm/mach/time.h>
#include <linux/device.h>
#include <linux/serial_8250.h>
#include "common.h"

static struct resource h7202ps2_resources[] = {
	[0] = {
		.start	= 0x8002c000,
		.end	= 0x8002c040,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= IRQ_PS2,
		.end	= IRQ_PS2,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device h7202ps2_device = {
	.name		= "h7202ps2",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(h7202ps2_resources),
	.resource	= h7202ps2_resources,
};

static struct plat_serial8250_port serial_platform_data[] = {
	{
		.membase	= (void*)SERIAL0_VIRT,
		.mapbase	= SERIAL0_BASE,
		.irq		= IRQ_UART0,
		.uartclk	= 2*1843200,
		.regshift	= 2,
		.iotype		= UPIO_MEM,
		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
	},
	{
		.membase	= (void*)SERIAL1_VIRT,
		.mapbase	= SERIAL1_BASE,
		.irq		= IRQ_UART1,
		.uartclk	= 2*1843200,
		.regshift	= 2,
		.iotype		= UPIO_MEM,
		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
	},
#ifdef CONFIG_H7202_SERIAL23
	{
		.membase	= (void*)SERIAL2_VIRT,
		.mapbase	= SERIAL2_BASE,
		.irq		= IRQ_UART2,
		.uartclk	= 2*1843200,
		.regshift	= 2,
		.iotype		= UPIO_MEM,
		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
	},
	{
		.membase	= (void*)SERIAL3_VIRT,
		.mapbase	= SERIAL3_BASE,
		.irq		= IRQ_UART3,
		.uartclk	= 2*1843200,
		.regshift	= 2,
		.iotype		= UPIO_MEM,
		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
	},
#endif
	{ },
};

static struct platform_device serial_device = {
	.name			= "serial8250",
	.id			= PLAT8250_DEV_PLATFORM,
	.dev			= {
		.platform_data	= serial_platform_data,
	},
};

static struct platform_device *devices[] __initdata = {
	&h7202ps2_device,
	&serial_device,
};

/* Although we have two interrupt lines for the timers, we only have one
 * status register which clears all pending timer interrupts on reading. So
 * we have to handle all timer interrupts in one place.
 */
static void
h7202_timerx_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
{
	unsigned int mask, irq;

	mask = CPU_REG (TIMER_VIRT, TIMER_TOPSTAT);

	if ( mask & TSTAT_T0INT ) {
		timer_tick();
		if( mask == TSTAT_T0INT )
			return;
	}

	mask >>= 1;
	irq = IRQ_TIMER1;
	desc = irq_desc + irq;
	while (mask) {
		if (mask & 1)
			desc_handle_irq(irq, desc);
		irq++;
		desc++;
		mask >>= 1;
	}
}

/*
 * Timer interrupt handler
 */
static irqreturn_t
h7202_timer_interrupt(int irq, void *dev_id)
{
	h7202_timerx_demux_handler(0, NULL);
	return IRQ_HANDLED;
}

/*
 * mask multiplexed timer IRQs
 */
static void inline mask_timerx_irq (u32 irq)
{
	unsigned int bit;
	bit = 2 << ((irq == IRQ_TIMER64B) ? 4 : (irq - IRQ_TIMER1));
	CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) &= ~bit;
}

/*
 * unmask multiplexed timer IRQs
 */
static void inline unmask_timerx_irq (u32 irq)
{
	unsigned int bit;
	bit = 2 << ((irq == IRQ_TIMER64B) ? 4 : (irq - IRQ_TIMER1));
	CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) |= bit;
}

static struct irq_chip h7202_timerx_chip = {
	.ack = mask_timerx_irq,
	.mask = mask_timerx_irq,
	.unmask = unmask_timerx_irq,
};

static struct irqaction h7202_timer_irq = {
	.name		= "h7202 Timer Tick",
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= h7202_timer_interrupt,
};

/*
 * Setup TIMER0 as system timer
 */
void __init h7202_init_time(void)
{
	CPU_REG (TIMER_VIRT, TM0_PERIOD) = LATCH;
	CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_RESET;
	CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_REPEAT | TM_START;
	CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) = ENABLE_TM0_INTR | TIMER_ENABLE_BIT;

	setup_irq(IRQ_TIMER0, &h7202_timer_irq);
}

struct sys_timer h7202_timer = {
	.init		= h7202_init_time,
	.offset		= h720x_gettimeoffset,
};

void __init h7202_init_irq (void)
{
	int 	irq;

	CPU_REG (GPIO_E_VIRT, GPIO_MASK) = 0x0;

	for (irq = IRQ_TIMER1;
	                  irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) {
		mask_timerx_irq(irq);
		set_irq_chip(irq, &h7202_timerx_chip);
		set_irq_handler(irq, handle_edge_irq);
		set_irq_flags(irq, IRQF_VALID );
	}
	set_irq_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler);

	h720x_init_irq();
}

void __init init_hw_h7202(void)
{
	/* Enable clocks */
	CPU_REG (PMU_BASE, PMU_PLL_CTRL) |= PLL_2_EN | PLL_1_EN | PLL_3_MUTE;

	CPU_REG (SERIAL0_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
	CPU_REG (SERIAL1_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
#ifdef CONFIG_H7202_SERIAL23
	CPU_REG (SERIAL2_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
	CPU_REG (SERIAL3_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
	CPU_IO (GPIO_AMULSEL) = AMULSEL_USIN2 | AMULSEL_USOUT2 |
	                        AMULSEL_USIN3 | AMULSEL_USOUT3;
#endif
	(void) platform_add_devices(devices, ARRAY_SIZE(devices));
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-h720x/cpu-h7202.c
	3	*
	4	* Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
	5	* 2003 Robert Schwebel <r.schwebel@pengutronix.de>
	6	* 2004 Sascha Hauer <s.hauer@pengutronix.de>
	7	*
	8	* processor specific stuff for the Hynix h7202
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*
	14	*/
	15
	16	#include <linux/init.h>
	17	#include <linux/interrupt.h>
	18	#include <linux/module.h>
	19	#include <asm/types.h>
a09e64fb	20	#include <mach/hardware.h>
1da177e4	21	#include <asm/irq.h>
a09e64fb	22	#include <mach/irqs.h>
1da177e4 LT	23	#include <asm/mach/irq.h>
	24	#include <asm/mach/time.h>
	25	#include <linux/device.h>
	26	#include <linux/serial_8250.h>
	27	#include "common.h"
	28
	29	static struct resource h7202ps2_resources[] = {
	30	[0] = {
	31	.start = 0x8002c000,
	32	.end = 0x8002c040,
	33	.flags = IORESOURCE_MEM,
	34	},
	35	[1] = {
	36	.start = IRQ_PS2,
	37	.end = IRQ_PS2,
	38	.flags = IORESOURCE_IRQ,
	39	},
	40	};
	41
	42	static struct platform_device h7202ps2_device = {
	43	.name = "h7202ps2",
	44	.id = -1,
	45	.num_resources = ARRAY_SIZE(h7202ps2_resources),
	46	.resource = h7202ps2_resources,
	47	};
	48
	49	static struct plat_serial8250_port serial_platform_data[] = {
	50	{
	51	.membase = (void*)SERIAL0_VIRT,
	52	.mapbase = SERIAL0_BASE,
	53	.irq = IRQ_UART0,
	54	.uartclk = 2*1843200,
	55	.regshift = 2,
	56	.iotype = UPIO_MEM,
	57	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST,
	58	},
	59	{
	60	.membase = (void*)SERIAL1_VIRT,
	61	.mapbase = SERIAL1_BASE,
	62	.irq = IRQ_UART1,
	63	.uartclk = 2*1843200,
	64	.regshift = 2,
	65	.iotype = UPIO_MEM,
	66	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST,
	67	},
	68	#ifdef CONFIG_H7202_SERIAL23
	69	{
	70	.membase = (void*)SERIAL2_VIRT,
	71	.mapbase = SERIAL2_BASE,
	72	.irq = IRQ_UART2,
	73	.uartclk = 2*1843200,
	74	.regshift = 2,
	75	.iotype = UPIO_MEM,
	76	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST,
	77	},
	78	{
	79	.membase = (void*)SERIAL3_VIRT,
	80	.mapbase = SERIAL3_BASE,
	81	.irq = IRQ_UART3,
	82	.uartclk = 2*1843200,
	83	.regshift = 2,
	84	.iotype = UPIO_MEM,
	85	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST,
	86	},
87	#endif
88	{ },
89	};
90
91	static struct platform_device serial_device = {
92	.name = "serial8250",
6df29deb	93	.id = PLAT8250_DEV_PLATFORM,
1da177e4 LT	94	.dev = {
	95	.platform_data = serial_platform_data,
	96	},
	97	};
	98
	99	static struct platform_device *devices[] __initdata = {
	100	&h7202ps2_device,
	101	&serial_device,
	102	};
	103
	104	/* Although we have two interrupt lines for the timers, we only have one
	105	* status register which clears all pending timer interrupts on reading. So
	106	* we have to handle all timer interrupts in one place.
	107	*/
	108	static void
10dd5ce2	109	h7202_timerx_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
1da177e4 LT	110	{
	111	unsigned int mask, irq;
	112
	113	mask = CPU_REG (TIMER_VIRT, TIMER_TOPSTAT);
	114
	115	if ( mask & TSTAT_T0INT ) {
0cd61b68	116	timer_tick();
1da177e4 LT	117	if( mask == TSTAT_T0INT )
	118	return;
	119	}
	120
	121	mask >>= 1;
	122	irq = IRQ_TIMER1;
	123	desc = irq_desc + irq;
	124	while (mask) {
	125	if (mask & 1)
0cd61b68	126	desc_handle_irq(irq, desc);
1da177e4 LT	127	irq++;
	128	desc++;
	129	mask >>= 1;
	130	}
	131	}
	132
	133	/*
	134	* Timer interrupt handler
	135	*/
	136	static irqreturn_t
0cd61b68	137	h7202_timer_interrupt(int irq, void *dev_id)
1da177e4	138	{
0cd61b68	139	h7202_timerx_demux_handler(0, NULL);
1da177e4 LT	140	return IRQ_HANDLED;
	141	}
	142
	143	/*
6cbdc8c5	144	* mask multiplexed timer IRQs
1da177e4 LT	145	*/
	146	static void inline mask_timerx_irq (u32 irq)
	147	{
	148	unsigned int bit;
	149	bit = 2 << ((irq == IRQ_TIMER64B) ? 4 : (irq - IRQ_TIMER1));
	150	CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) &= ~bit;
	151	}
	152
	153	/*
6cbdc8c5	154	* unmask multiplexed timer IRQs
1da177e4 LT	155	*/
	156	static void inline unmask_timerx_irq (u32 irq)
	157	{
	158	unsigned int bit;
	159	bit = 2 << ((irq == IRQ_TIMER64B) ? 4 : (irq - IRQ_TIMER1));
	160	CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) \|= bit;
	161	}
	162
10dd5ce2	163	static struct irq_chip h7202_timerx_chip = {
1da177e4 LT	164	.ack = mask_timerx_irq,
	165	.mask = mask_timerx_irq,
	166	.unmask = unmask_timerx_irq,
	167	};
	168
	169	static struct irqaction h7202_timer_irq = {
	170	.name = "h7202 Timer Tick",
b30fabad	171	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
09b8b5f8	172	.handler = h7202_timer_interrupt,
1da177e4 LT	173	};
	174
	175	/*
	176	* Setup TIMER0 as system timer
	177	*/
	178	void __init h7202_init_time(void)
	179	{
	180	CPU_REG (TIMER_VIRT, TM0_PERIOD) = LATCH;
	181	CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_RESET;
	182	CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_REPEAT \| TM_START;
	183	CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) = ENABLE_TM0_INTR \| TIMER_ENABLE_BIT;
	184
	185	setup_irq(IRQ_TIMER0, &h7202_timer_irq);
	186	}
	187
	188	struct sys_timer h7202_timer = {
	189	.init = h7202_init_time,
	190	.offset = h720x_gettimeoffset,
	191	};
	192
	193	void __init h7202_init_irq (void)
	194	{
	195	int irq;
	196
	197	CPU_REG (GPIO_E_VIRT, GPIO_MASK) = 0x0;
	198
	199	for (irq = IRQ_TIMER1;
	200	irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) {
	201	mask_timerx_irq(irq);
	202	set_irq_chip(irq, &h7202_timerx_chip);
10dd5ce2	203	set_irq_handler(irq, handle_edge_irq);
1da177e4 LT	204	set_irq_flags(irq, IRQF_VALID );
	205	}
	206	set_irq_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler);
	207
	208	h720x_init_irq();
	209	}
	210
	211	void __init init_hw_h7202(void)
	212	{
	213	/* Enable clocks */
	214	CPU_REG (PMU_BASE, PMU_PLL_CTRL) \|= PLL_2_EN \| PLL_1_EN \| PLL_3_MUTE;
	215
	216	CPU_REG (SERIAL0_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
	217	CPU_REG (SERIAL1_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
	218	#ifdef CONFIG_H7202_SERIAL23
	219	CPU_REG (SERIAL2_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
	220	CPU_REG (SERIAL3_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
	221	CPU_IO (GPIO_AMULSEL) = AMULSEL_USIN2 \| AMULSEL_USOUT2 \|
	222	AMULSEL_USIN3 \| AMULSEL_USOUT3;
	223	#endif
	224	(void) platform_add_devices(devices, ARRAY_SIZE(devices));
	225	}