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e95dddb3 AH |
1 | /* |
2 | * Copyright (C) 2013 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * The code contained herein is licensed under the GNU General Public | |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
10 | */ | |
11 | ||
12 | #include <linux/err.h> | |
13 | #include <linux/io.h> | |
14 | #include <linux/of.h> | |
15 | #include <linux/of_address.h> | |
16 | #include <linux/mfd/syscon.h> | |
17 | #include <linux/regmap.h> | |
fcc4f9fc | 18 | #include "common.h" |
f1c6f314 | 19 | #include "hardware.h" |
e95dddb3 AH |
20 | |
21 | #define REG_SET 0x4 | |
22 | #define REG_CLR 0x8 | |
23 | ||
263475d4 | 24 | #define ANADIG_REG_2P5 0x130 |
e95dddb3 | 25 | #define ANADIG_REG_CORE 0x140 |
263475d4 | 26 | #define ANADIG_ANA_MISC0 0x150 |
e95dddb3 AH |
27 | #define ANADIG_USB1_CHRG_DETECT 0x1b0 |
28 | #define ANADIG_USB2_CHRG_DETECT 0x210 | |
29 | #define ANADIG_DIGPROG 0x260 | |
d8ce823f | 30 | #define ANADIG_DIGPROG_IMX6SL 0x280 |
e95dddb3 | 31 | |
263475d4 | 32 | #define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x40000 |
bc4abc3e | 33 | #define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN 0x8 |
e95dddb3 | 34 | #define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000 |
263475d4 | 35 | #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG 0x1000 |
bc4abc3e AH |
36 | /* Below MISC0_DISCON_HIGH_SNVS is only for i.MX6SL */ |
37 | #define BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS 0x2000 | |
e95dddb3 AH |
38 | #define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B 0x80000 |
39 | #define BM_ANADIG_USB_CHRG_DETECT_EN_B 0x100000 | |
40 | ||
41 | static struct regmap *anatop; | |
42 | ||
263475d4 AH |
43 | static void imx_anatop_enable_weak2p5(bool enable) |
44 | { | |
45 | u32 reg, val; | |
46 | ||
47 | regmap_read(anatop, ANADIG_ANA_MISC0, &val); | |
48 | ||
49 | /* can only be enabled when stop_mode_config is clear. */ | |
50 | reg = ANADIG_REG_2P5; | |
51 | reg += (enable && (val & BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG) == 0) ? | |
52 | REG_SET : REG_CLR; | |
53 | regmap_write(anatop, reg, BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG); | |
54 | } | |
55 | ||
e95dddb3 AH |
56 | static void imx_anatop_enable_fet_odrive(bool enable) |
57 | { | |
58 | regmap_write(anatop, ANADIG_REG_CORE + (enable ? REG_SET : REG_CLR), | |
59 | BM_ANADIG_REG_CORE_FET_ODRIVE); | |
60 | } | |
61 | ||
bc4abc3e AH |
62 | static inline void imx_anatop_enable_2p5_pulldown(bool enable) |
63 | { | |
64 | regmap_write(anatop, ANADIG_REG_2P5 + (enable ? REG_SET : REG_CLR), | |
65 | BM_ANADIG_REG_2P5_ENABLE_PULLDOWN); | |
66 | } | |
67 | ||
68 | static inline void imx_anatop_disconnect_high_snvs(bool enable) | |
69 | { | |
70 | regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR), | |
71 | BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS); | |
72 | } | |
73 | ||
e95dddb3 AH |
74 | void imx_anatop_pre_suspend(void) |
75 | { | |
bc4abc3e AH |
76 | if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2) |
77 | imx_anatop_enable_2p5_pulldown(true); | |
78 | else | |
79 | imx_anatop_enable_weak2p5(true); | |
80 | ||
e95dddb3 | 81 | imx_anatop_enable_fet_odrive(true); |
bc4abc3e AH |
82 | |
83 | if (cpu_is_imx6sl()) | |
84 | imx_anatop_disconnect_high_snvs(true); | |
e95dddb3 AH |
85 | } |
86 | ||
87 | void imx_anatop_post_resume(void) | |
88 | { | |
bc4abc3e AH |
89 | if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2) |
90 | imx_anatop_enable_2p5_pulldown(false); | |
91 | else | |
92 | imx_anatop_enable_weak2p5(false); | |
93 | ||
e95dddb3 | 94 | imx_anatop_enable_fet_odrive(false); |
bc4abc3e AH |
95 | |
96 | if (cpu_is_imx6sl()) | |
97 | imx_anatop_disconnect_high_snvs(false); | |
98 | ||
e95dddb3 AH |
99 | } |
100 | ||
ddcb9aa6 | 101 | static void imx_anatop_usb_chrg_detect_disable(void) |
e95dddb3 AH |
102 | { |
103 | regmap_write(anatop, ANADIG_USB1_CHRG_DETECT, | |
104 | BM_ANADIG_USB_CHRG_DETECT_EN_B | |
105 | | BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B); | |
106 | regmap_write(anatop, ANADIG_USB2_CHRG_DETECT, | |
107 | BM_ANADIG_USB_CHRG_DETECT_EN_B | | |
108 | BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B); | |
109 | } | |
110 | ||
f1c6f314 | 111 | void __init imx_init_revision_from_anatop(void) |
e95dddb3 | 112 | { |
7006ba24 SG |
113 | struct device_node *np; |
114 | void __iomem *anatop_base; | |
f1c6f314 SG |
115 | unsigned int revision; |
116 | u32 digprog; | |
d8ce823f | 117 | u16 offset = ANADIG_DIGPROG; |
7006ba24 SG |
118 | |
119 | np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); | |
120 | anatop_base = of_iomap(np, 0); | |
121 | WARN_ON(!anatop_base); | |
d8ce823f SG |
122 | if (of_device_is_compatible(np, "fsl,imx6sl-anatop")) |
123 | offset = ANADIG_DIGPROG_IMX6SL; | |
124 | digprog = readl_relaxed(anatop_base + offset); | |
f1c6f314 SG |
125 | iounmap(anatop_base); |
126 | ||
127 | switch (digprog & 0xff) { | |
128 | case 0: | |
129 | revision = IMX_CHIP_REVISION_1_0; | |
130 | break; | |
131 | case 1: | |
132 | revision = IMX_CHIP_REVISION_1_1; | |
133 | break; | |
134 | case 2: | |
135 | revision = IMX_CHIP_REVISION_1_2; | |
136 | break; | |
c896e938 JL |
137 | case 3: |
138 | revision = IMX_CHIP_REVISION_1_3; | |
139 | break; | |
140 | case 4: | |
141 | revision = IMX_CHIP_REVISION_1_4; | |
142 | break; | |
143 | case 5: | |
144 | /* | |
145 | * i.MX6DQ TO1.5 is defined as Rev 1.3 in Data Sheet, marked | |
146 | * as 'D' in Part Number last character. | |
147 | */ | |
148 | revision = IMX_CHIP_REVISION_1_5; | |
149 | break; | |
f1c6f314 SG |
150 | default: |
151 | revision = IMX_CHIP_REVISION_UNKNOWN; | |
152 | } | |
7006ba24 | 153 | |
f1c6f314 SG |
154 | mxc_set_cpu_type(digprog >> 16 & 0xff); |
155 | imx_set_soc_revision(revision); | |
e95dddb3 AH |
156 | } |
157 | ||
158 | void __init imx_anatop_init(void) | |
159 | { | |
160 | anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop"); | |
161 | if (IS_ERR(anatop)) { | |
162 | pr_err("%s: failed to find imx6q-anatop regmap!\n", __func__); | |
163 | return; | |
164 | } | |
ddcb9aa6 PC |
165 | |
166 | imx_anatop_usb_chrg_detect_disable(); | |
e95dddb3 | 167 | } |