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Commit | Line | Data |
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e038ed50 SH |
1 | #include <linux/clk.h> |
2 | #include <linux/io.h> | |
3 | #include <linux/module.h> | |
4 | #include <linux/clkdev.h> | |
5 | #include <linux/err.h> | |
6 | #include <linux/clk-provider.h> | |
7 | #include <linux/of.h> | |
8 | ||
9 | #include <mach/common.h> | |
10 | #include <mach/hardware.h> | |
11 | #include "clk.h" | |
12 | ||
13 | #define IO_ADDR_CCM(off) (MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR + (off))) | |
14 | ||
15 | /* Register offsets */ | |
16 | #define CCM_CSCR IO_ADDR_CCM(0x0) | |
17 | #define CCM_MPCTL0 IO_ADDR_CCM(0x4) | |
18 | #define CCM_MPCTL1 IO_ADDR_CCM(0x8) | |
19 | #define CCM_SPCTL0 IO_ADDR_CCM(0xc) | |
20 | #define CCM_SPCTL1 IO_ADDR_CCM(0x10) | |
21 | #define CCM_OSC26MCTL IO_ADDR_CCM(0x14) | |
22 | #define CCM_PCDR0 IO_ADDR_CCM(0x18) | |
23 | #define CCM_PCDR1 IO_ADDR_CCM(0x1c) | |
24 | #define CCM_PCCR0 IO_ADDR_CCM(0x20) | |
25 | #define CCM_PCCR1 IO_ADDR_CCM(0x24) | |
26 | #define CCM_CCSR IO_ADDR_CCM(0x28) | |
27 | #define CCM_PMCTL IO_ADDR_CCM(0x2c) | |
28 | #define CCM_PMCOUNT IO_ADDR_CCM(0x30) | |
29 | #define CCM_WKGDCTL IO_ADDR_CCM(0x34) | |
30 | ||
31 | #define CCM_CSCR_UPDATE_DIS (1 << 31) | |
32 | #define CCM_CSCR_SSI2 (1 << 23) | |
33 | #define CCM_CSCR_SSI1 (1 << 22) | |
34 | #define CCM_CSCR_VPU (1 << 21) | |
35 | #define CCM_CSCR_MSHC (1 << 20) | |
36 | #define CCM_CSCR_SPLLRES (1 << 19) | |
37 | #define CCM_CSCR_MPLLRES (1 << 18) | |
38 | #define CCM_CSCR_SP (1 << 17) | |
39 | #define CCM_CSCR_MCU (1 << 16) | |
40 | #define CCM_CSCR_OSC26MDIV (1 << 4) | |
41 | #define CCM_CSCR_OSC26M (1 << 3) | |
42 | #define CCM_CSCR_FPM (1 << 2) | |
43 | #define CCM_CSCR_SPEN (1 << 1) | |
44 | #define CCM_CSCR_MPEN (1 << 0) | |
45 | ||
46 | /* i.MX27 TO 2+ */ | |
47 | #define CCM_CSCR_ARM_SRC (1 << 15) | |
48 | ||
49 | #define CCM_SPCTL1_LF (1 << 15) | |
50 | #define CCM_SPCTL1_BRMO (1 << 6) | |
51 | ||
52 | static const char *vpu_sel_clks[] = { "spll", "mpll_main2", }; | |
53 | static const char *cpu_sel_clks[] = { "mpll_main2", "mpll", }; | |
54 | static const char *clko_sel_clks[] = { | |
55 | "ckil", "prem", "ckih", "ckih", | |
56 | "ckih", "mpll", "spll", "cpu_div", | |
57 | "ahb", "ipg", "per1_div", "per2_div", | |
58 | "per3_div", "per4_div", "ssi1_div", "ssi2_div", | |
59 | "nfc_div", "mshc_div", "vpu_div", "60m", | |
60 | "32k", "usb_div", "dptc", | |
61 | }; | |
62 | ||
63 | static const char *ssi_sel_clks[] = { "spll", "mpll", }; | |
64 | ||
65 | enum mx27_clks { | |
66 | dummy, ckih, ckil, mpll, spll, mpll_main2, ahb, ipg, nfc_div, per1_div, | |
67 | per2_div, per3_div, per4_div, vpu_sel, vpu_div, usb_div, cpu_sel, | |
68 | clko_sel, cpu_div, clko_div, ssi1_sel, ssi2_sel, ssi1_div, ssi2_div, | |
69 | clko_en, ssi2_ipg_gate, ssi1_ipg_gate, slcdc_ipg_gate, sdhc3_ipg_gate, | |
70 | sdhc2_ipg_gate, sdhc1_ipg_gate, scc_ipg_gate, sahara_ipg_gate, | |
71 | rtc_ipg_gate, pwm_ipg_gate, owire_ipg_gate, lcdc_ipg_gate, | |
72 | kpp_ipg_gate, iim_ipg_gate, i2c2_ipg_gate, i2c1_ipg_gate, | |
73 | gpt6_ipg_gate, gpt5_ipg_gate, gpt4_ipg_gate, gpt3_ipg_gate, | |
74 | gpt2_ipg_gate, gpt1_ipg_gate, gpio_ipg_gate, fec_ipg_gate, | |
75 | emma_ipg_gate, dma_ipg_gate, cspi3_ipg_gate, cspi2_ipg_gate, | |
76 | cspi1_ipg_gate, nfc_baud_gate, ssi2_baud_gate, ssi1_baud_gate, | |
77 | vpu_baud_gate, per4_gate, per3_gate, per2_gate, per1_gate, | |
78 | usb_ahb_gate, slcdc_ahb_gate, sahara_ahb_gate, lcdc_ahb_gate, | |
79 | vpu_ahb_gate, fec_ahb_gate, emma_ahb_gate, emi_ahb_gate, dma_ahb_gate, | |
80 | csi_ahb_gate, brom_ahb_gate, ata_ahb_gate, wdog_ipg_gate, usb_ipg_gate, | |
81 | uart6_ipg_gate, uart5_ipg_gate, uart4_ipg_gate, uart3_ipg_gate, | |
82 | uart2_ipg_gate, uart1_ipg_gate, clk_max | |
83 | }; | |
84 | ||
85 | static struct clk *clk[clk_max]; | |
86 | ||
87 | int __init mx27_clocks_init(unsigned long fref) | |
88 | { | |
89 | int i; | |
90 | ||
91 | clk[dummy] = imx_clk_fixed("dummy", 0); | |
92 | clk[ckih] = imx_clk_fixed("ckih", fref); | |
93 | clk[ckil] = imx_clk_fixed("ckil", 32768); | |
94 | clk[mpll] = imx_clk_pllv1("mpll", "ckih", CCM_MPCTL0); | |
95 | clk[spll] = imx_clk_pllv1("spll", "ckih", CCM_SPCTL0); | |
96 | clk[mpll_main2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3); | |
97 | ||
98 | if (mx27_revision() >= IMX_CHIP_REVISION_2_0) { | |
99 | clk[ahb] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2); | |
100 | clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); | |
101 | } else { | |
102 | clk[ahb] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4); | |
103 | clk[ipg] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1); | |
104 | } | |
105 | ||
106 | clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4); | |
107 | clk[per1_div] = imx_clk_divider("per1_div", "mpll_main2", CCM_PCDR1, 0, 6); | |
108 | clk[per2_div] = imx_clk_divider("per2_div", "mpll_main2", CCM_PCDR1, 8, 6); | |
109 | clk[per3_div] = imx_clk_divider("per3_div", "mpll_main2", CCM_PCDR1, 16, 6); | |
110 | clk[per4_div] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6); | |
111 | clk[vpu_sel] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks)); | |
3b4d6c82 | 112 | clk[vpu_div] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6); |
e038ed50 SH |
113 | clk[usb_div] = imx_clk_divider("usb_div", "spll", CCM_CSCR, 28, 3); |
114 | clk[cpu_sel] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks)); | |
115 | clk[clko_sel] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks)); | |
116 | if (mx27_revision() >= IMX_CHIP_REVISION_2_0) | |
117 | clk[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 12, 2); | |
118 | else | |
119 | clk[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 13, 3); | |
120 | clk[clko_div] = imx_clk_divider("clko_div", "clko_sel", CCM_PCDR0, 22, 3); | |
121 | clk[ssi1_sel] = imx_clk_mux("ssi1_sel", CCM_CSCR, 22, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks)); | |
122 | clk[ssi2_sel] = imx_clk_mux("ssi2_sel", CCM_CSCR, 23, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks)); | |
123 | clk[ssi1_div] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6); | |
3b4d6c82 | 124 | clk[ssi2_div] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6); |
e038ed50 SH |
125 | clk[clko_en] = imx_clk_gate("clko_en", "clko_div", CCM_PCCR0, 0); |
126 | clk[ssi2_ipg_gate] = imx_clk_gate("ssi2_ipg_gate", "ipg", CCM_PCCR0, 0); | |
127 | clk[ssi1_ipg_gate] = imx_clk_gate("ssi1_ipg_gate", "ipg", CCM_PCCR0, 1); | |
128 | clk[slcdc_ipg_gate] = imx_clk_gate("slcdc_ipg_gate", "ipg", CCM_PCCR0, 2); | |
129 | clk[sdhc3_ipg_gate] = imx_clk_gate("sdhc3_ipg_gate", "ipg", CCM_PCCR0, 3); | |
130 | clk[sdhc2_ipg_gate] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 4); | |
131 | clk[sdhc1_ipg_gate] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 5); | |
132 | clk[scc_ipg_gate] = imx_clk_gate("scc_ipg_gate", "ipg", CCM_PCCR0, 6); | |
133 | clk[sahara_ipg_gate] = imx_clk_gate("sahara_ipg_gate", "ipg", CCM_PCCR0, 7); | |
134 | clk[rtc_ipg_gate] = imx_clk_gate("rtc_ipg_gate", "ipg", CCM_PCCR0, 9); | |
135 | clk[pwm_ipg_gate] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR0, 11); | |
136 | clk[owire_ipg_gate] = imx_clk_gate("owire_ipg_gate", "ipg", CCM_PCCR0, 12); | |
137 | clk[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 14); | |
138 | clk[kpp_ipg_gate] = imx_clk_gate("kpp_ipg_gate", "ipg", CCM_PCCR0, 15); | |
139 | clk[iim_ipg_gate] = imx_clk_gate("iim_ipg_gate", "ipg", CCM_PCCR0, 16); | |
140 | clk[i2c2_ipg_gate] = imx_clk_gate("i2c2_ipg_gate", "ipg", CCM_PCCR0, 17); | |
141 | clk[i2c1_ipg_gate] = imx_clk_gate("i2c1_ipg_gate", "ipg", CCM_PCCR0, 18); | |
142 | clk[gpt6_ipg_gate] = imx_clk_gate("gpt6_ipg_gate", "ipg", CCM_PCCR0, 19); | |
143 | clk[gpt5_ipg_gate] = imx_clk_gate("gpt5_ipg_gate", "ipg", CCM_PCCR0, 20); | |
144 | clk[gpt4_ipg_gate] = imx_clk_gate("gpt4_ipg_gate", "ipg", CCM_PCCR0, 21); | |
145 | clk[gpt3_ipg_gate] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR0, 22); | |
146 | clk[gpt2_ipg_gate] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR0, 23); | |
147 | clk[gpt1_ipg_gate] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR0, 24); | |
148 | clk[gpio_ipg_gate] = imx_clk_gate("gpio_ipg_gate", "ipg", CCM_PCCR0, 25); | |
149 | clk[fec_ipg_gate] = imx_clk_gate("fec_ipg_gate", "ipg", CCM_PCCR0, 26); | |
150 | clk[emma_ipg_gate] = imx_clk_gate("emma_ipg_gate", "ipg", CCM_PCCR0, 27); | |
151 | clk[dma_ipg_gate] = imx_clk_gate("dma_ipg_gate", "ipg", CCM_PCCR0, 28); | |
152 | clk[cspi3_ipg_gate] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR0, 29); | |
153 | clk[cspi2_ipg_gate] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 30); | |
154 | clk[cspi1_ipg_gate] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 31); | |
155 | clk[nfc_baud_gate] = imx_clk_gate("nfc_baud_gate", "nfc_div", CCM_PCCR1, 3); | |
156 | clk[ssi2_baud_gate] = imx_clk_gate("ssi2_baud_gate", "ssi2_div", CCM_PCCR1, 4); | |
157 | clk[ssi1_baud_gate] = imx_clk_gate("ssi1_baud_gate", "ssi1_div", CCM_PCCR1, 5); | |
158 | clk[vpu_baud_gate] = imx_clk_gate("vpu_baud_gate", "vpu_div", CCM_PCCR1, 6); | |
159 | clk[per4_gate] = imx_clk_gate("per4_gate", "per4_div", CCM_PCCR1, 7); | |
160 | clk[per3_gate] = imx_clk_gate("per3_gate", "per3_div", CCM_PCCR1, 8); | |
161 | clk[per2_gate] = imx_clk_gate("per2_gate", "per2_div", CCM_PCCR1, 9); | |
162 | clk[per1_gate] = imx_clk_gate("per1_gate", "per1_div", CCM_PCCR1, 10); | |
163 | clk[usb_ahb_gate] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11); | |
164 | clk[slcdc_ahb_gate] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12); | |
165 | clk[sahara_ahb_gate] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13); | |
166 | clk[lcdc_ahb_gate] = imx_clk_gate("lcdc_ahb_gate", "ahb", CCM_PCCR1, 15); | |
167 | clk[vpu_ahb_gate] = imx_clk_gate("vpu_ahb_gate", "ahb", CCM_PCCR1, 16); | |
168 | clk[fec_ahb_gate] = imx_clk_gate("fec_ahb_gate", "ahb", CCM_PCCR1, 17); | |
169 | clk[emma_ahb_gate] = imx_clk_gate("emma_ahb_gate", "ahb", CCM_PCCR1, 18); | |
170 | clk[emi_ahb_gate] = imx_clk_gate("emi_ahb_gate", "ahb", CCM_PCCR1, 19); | |
171 | clk[dma_ahb_gate] = imx_clk_gate("dma_ahb_gate", "ahb", CCM_PCCR1, 20); | |
172 | clk[csi_ahb_gate] = imx_clk_gate("csi_ahb_gate", "ahb", CCM_PCCR1, 21); | |
173 | clk[brom_ahb_gate] = imx_clk_gate("brom_ahb_gate", "ahb", CCM_PCCR1, 22); | |
174 | clk[ata_ahb_gate] = imx_clk_gate("ata_ahb_gate", "ahb", CCM_PCCR1, 23); | |
175 | clk[wdog_ipg_gate] = imx_clk_gate("wdog_ipg_gate", "ipg", CCM_PCCR1, 24); | |
176 | clk[usb_ipg_gate] = imx_clk_gate("usb_ipg_gate", "ipg", CCM_PCCR1, 25); | |
177 | clk[uart6_ipg_gate] = imx_clk_gate("uart6_ipg_gate", "ipg", CCM_PCCR1, 26); | |
178 | clk[uart5_ipg_gate] = imx_clk_gate("uart5_ipg_gate", "ipg", CCM_PCCR1, 27); | |
179 | clk[uart4_ipg_gate] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR1, 28); | |
180 | clk[uart3_ipg_gate] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR1, 29); | |
181 | clk[uart2_ipg_gate] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR1, 30); | |
182 | clk[uart1_ipg_gate] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31); | |
183 | ||
184 | for (i = 0; i < ARRAY_SIZE(clk); i++) | |
185 | if (IS_ERR(clk[i])) | |
186 | pr_err("i.MX27 clk %d: register failed with %ld\n", | |
187 | i, PTR_ERR(clk[i])); | |
188 | ||
189 | clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0"); | |
190 | clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.0"); | |
191 | clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1"); | |
192 | clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.1"); | |
193 | clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2"); | |
194 | clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.2"); | |
195 | clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3"); | |
196 | clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.3"); | |
197 | clk_register_clkdev(clk[uart5_ipg_gate], "ipg", "imx21-uart.4"); | |
198 | clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.4"); | |
199 | clk_register_clkdev(clk[uart6_ipg_gate], "ipg", "imx21-uart.5"); | |
200 | clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.5"); | |
201 | clk_register_clkdev(clk[gpt1_ipg_gate], "ipg", "imx-gpt.0"); | |
202 | clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.0"); | |
203 | clk_register_clkdev(clk[gpt2_ipg_gate], "ipg", "imx-gpt.1"); | |
204 | clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.1"); | |
205 | clk_register_clkdev(clk[gpt3_ipg_gate], "ipg", "imx-gpt.2"); | |
206 | clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.2"); | |
207 | clk_register_clkdev(clk[gpt4_ipg_gate], "ipg", "imx-gpt.3"); | |
208 | clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.3"); | |
209 | clk_register_clkdev(clk[gpt5_ipg_gate], "ipg", "imx-gpt.4"); | |
210 | clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.4"); | |
211 | clk_register_clkdev(clk[gpt6_ipg_gate], "ipg", "imx-gpt.5"); | |
212 | clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.5"); | |
213 | clk_register_clkdev(clk[pwm_ipg_gate], NULL, "mxc_pwm.0"); | |
214 | clk_register_clkdev(clk[per2_gate], "per", "mxc-mmc.0"); | |
215 | clk_register_clkdev(clk[sdhc1_ipg_gate], "ipg", "mxc-mmc.0"); | |
216 | clk_register_clkdev(clk[per2_gate], "per", "mxc-mmc.1"); | |
217 | clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "mxc-mmc.1"); | |
218 | clk_register_clkdev(clk[per2_gate], "per", "mxc-mmc.2"); | |
219 | clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "mxc-mmc.2"); | |
220 | clk_register_clkdev(clk[cspi1_ipg_gate], NULL, "imx27-cspi.0"); | |
221 | clk_register_clkdev(clk[cspi2_ipg_gate], NULL, "imx27-cspi.1"); | |
222 | clk_register_clkdev(clk[cspi3_ipg_gate], NULL, "imx27-cspi.2"); | |
223 | clk_register_clkdev(clk[per3_gate], "per", "imx-fb.0"); | |
224 | clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx-fb.0"); | |
225 | clk_register_clkdev(clk[lcdc_ahb_gate], "ahb", "imx-fb.0"); | |
9de76b6d | 226 | clk_register_clkdev(clk[csi_ahb_gate], "ahb", "mx2-camera.0"); |
e038ed50 SH |
227 | clk_register_clkdev(clk[usb_div], "per", "fsl-usb2-udc"); |
228 | clk_register_clkdev(clk[usb_ipg_gate], "ipg", "fsl-usb2-udc"); | |
229 | clk_register_clkdev(clk[usb_ahb_gate], "ahb", "fsl-usb2-udc"); | |
230 | clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0"); | |
231 | clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.0"); | |
232 | clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.0"); | |
233 | clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1"); | |
234 | clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.1"); | |
235 | clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.1"); | |
236 | clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2"); | |
237 | clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.2"); | |
238 | clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.2"); | |
239 | clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0"); | |
240 | clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1"); | |
241 | clk_register_clkdev(clk[nfc_baud_gate], NULL, "mxc_nand.0"); | |
6d8c4529 JM |
242 | clk_register_clkdev(clk[vpu_baud_gate], "per", "coda-imx27.0"); |
243 | clk_register_clkdev(clk[vpu_ahb_gate], "ahb", "coda-imx27.0"); | |
e038ed50 SH |
244 | clk_register_clkdev(clk[dma_ahb_gate], "ahb", "imx-dma"); |
245 | clk_register_clkdev(clk[dma_ipg_gate], "ipg", "imx-dma"); | |
246 | clk_register_clkdev(clk[fec_ipg_gate], "ipg", "imx27-fec.0"); | |
247 | clk_register_clkdev(clk[fec_ahb_gate], "ahb", "imx27-fec.0"); | |
248 | clk_register_clkdev(clk[wdog_ipg_gate], NULL, "imx2-wdt.0"); | |
249 | clk_register_clkdev(clk[i2c1_ipg_gate], NULL, "imx-i2c.0"); | |
250 | clk_register_clkdev(clk[i2c2_ipg_gate], NULL, "imx-i2c.1"); | |
251 | clk_register_clkdev(clk[owire_ipg_gate], NULL, "mxc_w1.0"); | |
252 | clk_register_clkdev(clk[kpp_ipg_gate], NULL, "imx-keypad"); | |
9de76b6d JM |
253 | clk_register_clkdev(clk[emma_ahb_gate], "emma-ahb", "mx2-camera.0"); |
254 | clk_register_clkdev(clk[emma_ipg_gate], "emma-ipg", "mx2-camera.0"); | |
255 | clk_register_clkdev(clk[emma_ahb_gate], "ahb", "m2m-emmaprp.0"); | |
256 | clk_register_clkdev(clk[emma_ipg_gate], "ipg", "m2m-emmaprp.0"); | |
e038ed50 SH |
257 | clk_register_clkdev(clk[iim_ipg_gate], "iim", NULL); |
258 | clk_register_clkdev(clk[gpio_ipg_gate], "gpio", NULL); | |
259 | clk_register_clkdev(clk[brom_ahb_gate], "brom", NULL); | |
260 | clk_register_clkdev(clk[ata_ahb_gate], "ata", NULL); | |
2c1706dd | 261 | clk_register_clkdev(clk[rtc_ipg_gate], NULL, "mxc_rtc"); |
e038ed50 SH |
262 | clk_register_clkdev(clk[scc_ipg_gate], "scc", NULL); |
263 | clk_register_clkdev(clk[cpu_div], "cpu", NULL); | |
264 | clk_register_clkdev(clk[emi_ahb_gate], "emi_ahb" , NULL); | |
265 | clk_register_clkdev(clk[ssi1_baud_gate], "bitrate" , "imx-ssi.0"); | |
266 | clk_register_clkdev(clk[ssi2_baud_gate], "bitrate" , "imx-ssi.1"); | |
267 | ||
2cfb4518 | 268 | mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1); |
e038ed50 SH |
269 | |
270 | clk_prepare_enable(clk[emi_ahb_gate]); | |
271 | ||
1b76b74d FE |
272 | imx_print_silicon_rev("i.MX27", mx27_revision()); |
273 | ||
e038ed50 SH |
274 | return 0; |
275 | } | |
276 | ||
277 | #ifdef CONFIG_OF | |
278 | int __init mx27_clocks_init_dt(void) | |
279 | { | |
280 | struct device_node *np; | |
281 | u32 fref = 26000000; /* default */ | |
282 | ||
283 | for_each_compatible_node(np, NULL, "fixed-clock") { | |
284 | if (!of_device_is_compatible(np, "fsl,imx-osc26m")) | |
285 | continue; | |
286 | ||
287 | if (!of_property_read_u32(np, "clock-frequency", &fref)) | |
288 | break; | |
289 | } | |
290 | ||
291 | return mx27_clocks_init(fref); | |
292 | } | |
293 | #endif |