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Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-imx / clk-imx51-imx53.c
CommitLineData
b8d4176f
SH		 1/*
2 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9#include <linux/mm.h>
10#include <linux/delay.h>
11#include <linux/clk.h>
12#include <linux/io.h>
13#include <linux/clkdev.h>
4d9d18a5 14#include <linux/clk-provider.h>
b8d4176f 15#include <linux/err.h>
bfcc7bce
FE		 16#include <linux/of.h>
17#include <linux/of_address.h>
18#include <linux/of_irq.h>
490dd880 19#include <dt-bindings/clock/imx5-clock.h>
b8d4176f 20
b8d4176f 21#include "clk.h"
e3372474 22#include "common.h"
50f2de61 23#include "hardware.h"
b8d4176f 24
20484c13
SG		 25#define MX51_DPLL1_BASE 0x83f80000
26#define MX51_DPLL2_BASE 0x83f84000
27#define MX51_DPLL3_BASE 0x83f88000
28
29#define MX53_DPLL1_BASE 0x63f80000
30#define MX53_DPLL2_BASE 0x63f84000
31#define MX53_DPLL3_BASE 0x63f88000
32#define MX53_DPLL4_BASE 0x63f8c000
e7d5eb3c 33
18c1d989
SG		 34#define MXC_CCM_CCR (ccm_base + 0x00)
35#define MXC_CCM_CCDR (ccm_base + 0x04)
36#define MXC_CCM_CSR (ccm_base + 0x08)
37#define MXC_CCM_CCSR (ccm_base + 0x0c)
38#define MXC_CCM_CACRR (ccm_base + 0x10)
39#define MXC_CCM_CBCDR (ccm_base + 0x14)
40#define MXC_CCM_CBCMR (ccm_base + 0x18)
41#define MXC_CCM_CSCMR1 (ccm_base + 0x1c)
42#define MXC_CCM_CSCMR2 (ccm_base + 0x20)
43#define MXC_CCM_CSCDR1 (ccm_base + 0x24)
44#define MXC_CCM_CS1CDR (ccm_base + 0x28)
45#define MXC_CCM_CS2CDR (ccm_base + 0x2c)
46#define MXC_CCM_CDCDR (ccm_base + 0x30)
47#define MXC_CCM_CHSCDR (ccm_base + 0x34)
48#define MXC_CCM_CSCDR2 (ccm_base + 0x38)
49#define MXC_CCM_CSCDR3 (ccm_base + 0x3c)
50#define MXC_CCM_CSCDR4 (ccm_base + 0x40)
51#define MXC_CCM_CWDR (ccm_base + 0x44)
52#define MXC_CCM_CDHIPR (ccm_base + 0x48)
53#define MXC_CCM_CDCR (ccm_base + 0x4c)
54#define MXC_CCM_CTOR (ccm_base + 0x50)
55#define MXC_CCM_CLPCR (ccm_base + 0x54)
56#define MXC_CCM_CISR (ccm_base + 0x58)
57#define MXC_CCM_CIMR (ccm_base + 0x5c)
58#define MXC_CCM_CCOSR (ccm_base + 0x60)
59#define MXC_CCM_CGPR (ccm_base + 0x64)
60#define MXC_CCM_CCGR0 (ccm_base + 0x68)
61#define MXC_CCM_CCGR1 (ccm_base + 0x6c)
62#define MXC_CCM_CCGR2 (ccm_base + 0x70)
63#define MXC_CCM_CCGR3 (ccm_base + 0x74)
64#define MXC_CCM_CCGR4 (ccm_base + 0x78)
65#define MXC_CCM_CCGR5 (ccm_base + 0x7c)
66#define MXC_CCM_CCGR6 (ccm_base + 0x80)
67#define MXC_CCM_CCGR7 (ccm_base + 0x84)
e7d5eb3c 68
b8d4176f
SH		 69/* Low-power Audio Playback Mode clock */
70static const char *lp_apm_sel[] = { "osc", };
71
72/* This is used multiple times */
73static const char *standard_pll_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "lp_apm", };
74static const char *periph_apm_sel[] = { "pll1_sw", "pll3_sw", "lp_apm", };
75static const char *main_bus_sel[] = { "pll2_sw", "periph_apm", };
76static const char *per_lp_apm_sel[] = { "main_bus", "lp_apm", };
77static const char *per_root_sel[] = { "per_podf", "ipg", };
78static const char *esdhc_c_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
79static const char *esdhc_d_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
13b3a07a
SG		 80static const char *ssi_apm_sels[] = { "ckih1", "lp_amp", "ckih2", };
81static const char *ssi_clk_sels[] = { "pll1_sw", "pll2_sw", "pll3_sw", "ssi_apm", };
82static const char *ssi3_clk_sels[] = { "ssi1_root_gate", "ssi2_root_gate", };
83static const char *ssi_ext1_com_sels[] = { "ssi_ext1_podf", "ssi1_root_gate", };
84static const char *ssi_ext2_com_sels[] = { "ssi_ext2_podf", "ssi2_root_gate", };
b8d4176f
SH		 85static const char *emi_slow_sel[] = { "main_bus", "ahb", };
86static const char *usb_phy_sel_str[] = { "osc", "usb_phy_podf", };
87static const char *mx51_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "tve_di", };
51f66191 88static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0_gate", };
b8d4176f
SH		 89static const char *mx53_ldb_di0_sel[] = { "pll3_sw", "pll4_sw", };
90static const char *mx51_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", };
51f66191 91static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1_gate", };
b8d4176f
SH		 92static const char *mx53_ldb_di1_sel[] = { "pll3_sw", "pll4_sw", };
93static const char *mx51_tve_ext_sel[] = { "osc", "ckih1", };
94static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", };
3f487bed 95static const char *mx51_tve_sel[] = { "tve_pred", "tve_ext_sel", };
b8d4176f 96static const char *ipu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
8ecb167f
PZ		 97static const char *gpu3d_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb" };
98static const char *gpu2d_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb" };
b8d4176f 99static const char *vpu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
a745f039 100static const char *mx53_can_sel[] = { "ipg", "ckih1", "ckih2", "lp_apm", };
04b41e84
MF		 101static const char *mx53_cko1_sel[] = {
102 "cpu_podf", "pll1_sw", "pll2_sw", "pll3_sw",
103 "emi_slow_podf", "pll4_sw", "nfc_podf", "dummy",
104 "di_pred", "dummy", "dummy", "ahb",
105 "ipg", "per_root", "ckil", "dummy",};
106static const char *mx53_cko2_sel[] = {
107 "dummy"/* dptc_core */, "dummy"/* dptc_perich */,
108 "dummy", "esdhc_a_podf",
109 "usboh3_podf", "dummy"/* wrck_clk_root */,
110 "ecspi_podf", "dummy"/* pll1_ref_clk */,
111 "esdhc_b_podf", "dummy"/* ddr_clk_root */,
112 "dummy"/* arm_axi_clk_root */, "dummy"/* usb_phy_out */,
113 "vpu_sel", "ipu_sel",
114 "osc", "ckih1",
115 "dummy", "esdhc_c_sel",
116 "ssi1_root_podf", "ssi2_root_podf",
117 "dummy", "dummy",
118 "dummy"/* lpsr_clk_root */, "dummy"/* pgc_clk_root */,
119 "dummy"/* tve_out */, "usb_phy_sel",
120 "tve_sel", "lp_apm",
121 "uart_root", "dummy"/* spdif0_clk_root */,
122 "dummy", "dummy", };
beb2d1c1
PZ		 123static const char *mx51_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", };
124static const char *mx53_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", "pll4_sw", };
125static const char *spdif_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "spdif_xtal_sel", };
126static const char *spdif0_com_sel[] = { "spdif0_podf", "ssi1_root_gate", };
127static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", };
6f0628aa
LS		 128static const char *step_sels[] = { "lp_apm", };
129static const char *cpu_podf_sels[] = { "pll1_sw", "step_sel" };
beb2d1c1 130
490dd880 131static struct clk *clk[IMX5_CLK_END];
f40f38d1 132static struct clk_onecell_data clk_data;
b8d4176f 133
18c1d989 134static void __init mx5_clocks_common_init(void __iomem *ccm_base)
b8d4176f 135{
4ef5e387
SG		 136 imx5_pm_set_ccm_base(ccm_base);
137
490dd880 138 clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
b674cf2f
SG		 139 clk[IMX5_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
140 clk[IMX5_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
141 clk[IMX5_CLK_CKIH1] = imx_obtain_fixed_clock("ckih1", 0);
142 clk[IMX5_CLK_CKIH2] = imx_obtain_fixed_clock("ckih2", 0);
490dd880 143
490dd880
LS		 144 clk[IMX5_CLK_PERIPH_APM] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
145 periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
146 clk[IMX5_CLK_MAIN_BUS] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
147 main_bus_sel, ARRAY_SIZE(main_bus_sel));
148 clk[IMX5_CLK_PER_LP_APM] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1,
149 per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));
150 clk[IMX5_CLK_PER_PRED1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2);
151 clk[IMX5_CLK_PER_PRED2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3);
152 clk[IMX5_CLK_PER_PODF] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3);
153 clk[IMX5_CLK_PER_ROOT] = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1,
154 per_root_sel, ARRAY_SIZE(per_root_sel));
155 clk[IMX5_CLK_AHB] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3);
156 clk[IMX5_CLK_AHB_MAX] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28);
157 clk[IMX5_CLK_AIPS_TZ1] = imx_clk_gate2("aips_tz1", "ahb", MXC_CCM_CCGR0, 24);
158 clk[IMX5_CLK_AIPS_TZ2] = imx_clk_gate2("aips_tz2", "ahb", MXC_CCM_CCGR0, 26);
159 clk[IMX5_CLK_TMAX1] = imx_clk_gate2("tmax1", "ahb", MXC_CCM_CCGR1, 0);
160 clk[IMX5_CLK_TMAX2] = imx_clk_gate2("tmax2", "ahb", MXC_CCM_CCGR1, 2);
161 clk[IMX5_CLK_TMAX3] = imx_clk_gate2("tmax3", "ahb", MXC_CCM_CCGR1, 4);
162 clk[IMX5_CLK_SPBA] = imx_clk_gate2("spba", "ipg", MXC_CCM_CCGR5, 0);
163 clk[IMX5_CLK_IPG] = imx_clk_divider("ipg", "ahb", MXC_CCM_CBCDR, 8, 2);
164 clk[IMX5_CLK_AXI_A] = imx_clk_divider("axi_a", "main_bus", MXC_CCM_CBCDR, 16, 3);
165 clk[IMX5_CLK_AXI_B] = imx_clk_divider("axi_b", "main_bus", MXC_CCM_CBCDR, 19, 3);
166 clk[IMX5_CLK_UART_SEL] = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1, 24, 2,
167 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
168 clk[IMX5_CLK_UART_PRED] = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3);
169 clk[IMX5_CLK_UART_ROOT] = imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3);
170
171 clk[IMX5_CLK_ESDHC_A_SEL] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2,
172 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
173 clk[IMX5_CLK_ESDHC_B_SEL] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
174 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
175 clk[IMX5_CLK_ESDHC_A_PRED] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3);
176 clk[IMX5_CLK_ESDHC_A_PODF] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3);
177 clk[IMX5_CLK_ESDHC_B_PRED] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3);
178 clk[IMX5_CLK_ESDHC_B_PODF] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3);
179 clk[IMX5_CLK_ESDHC_C_SEL] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
180 clk[IMX5_CLK_ESDHC_D_SEL] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
181
182 clk[IMX5_CLK_EMI_SEL] = imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1,
183 emi_slow_sel, ARRAY_SIZE(emi_slow_sel));
184 clk[IMX5_CLK_EMI_SLOW_PODF] = imx_clk_divider("emi_slow_podf", "emi_sel", MXC_CCM_CBCDR, 22, 3);
185 clk[IMX5_CLK_NFC_PODF] = imx_clk_divider("nfc_podf", "emi_slow_podf", MXC_CCM_CBCDR, 13, 3);
186 clk[IMX5_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", MXC_CCM_CSCMR1, 4, 2,
187 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
188 clk[IMX5_CLK_ECSPI_PRED] = imx_clk_divider("ecspi_pred", "ecspi_sel", MXC_CCM_CSCDR2, 25, 3);
189 clk[IMX5_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf", "ecspi_pred", MXC_CCM_CSCDR2, 19, 6);
190 clk[IMX5_CLK_USBOH3_SEL] = imx_clk_mux("usboh3_sel", MXC_CCM_CSCMR1, 22, 2,
191 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
192 clk[IMX5_CLK_USBOH3_PRED] = imx_clk_divider("usboh3_pred", "usboh3_sel", MXC_CCM_CSCDR1, 8, 3);
193 clk[IMX5_CLK_USBOH3_PODF] = imx_clk_divider("usboh3_podf", "usboh3_pred", MXC_CCM_CSCDR1, 6, 2);
194 clk[IMX5_CLK_USB_PHY_PRED] = imx_clk_divider("usb_phy_pred", "pll3_sw", MXC_CCM_CDCDR, 3, 3);
195 clk[IMX5_CLK_USB_PHY_PODF] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3);
196 clk[IMX5_CLK_USB_PHY_SEL] = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1,
197 usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str));
6f0628aa
LS		 198 clk[IMX5_CLK_STEP_SEL] = imx_clk_mux("step_sel", MXC_CCM_CCSR, 7, 2, step_sels, ARRAY_SIZE(step_sels));
199 clk[IMX5_CLK_CPU_PODF_SEL] = imx_clk_mux("cpu_podf_sel", MXC_CCM_CCSR, 2, 1, cpu_podf_sels, ARRAY_SIZE(cpu_podf_sels));
200 clk[IMX5_CLK_CPU_PODF] = imx_clk_divider("cpu_podf", "cpu_podf_sel", MXC_CCM_CACRR, 0, 3);
490dd880
LS		 201 clk[IMX5_CLK_DI_PRED] = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3);
202 clk[IMX5_CLK_IIM_GATE] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30);
203 clk[IMX5_CLK_UART1_IPG_GATE] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6);
204 clk[IMX5_CLK_UART1_PER_GATE] = imx_clk_gate2("uart1_per_gate", "uart_root", MXC_CCM_CCGR1, 8);
205 clk[IMX5_CLK_UART2_IPG_GATE] = imx_clk_gate2("uart2_ipg_gate", "ipg", MXC_CCM_CCGR1, 10);
206 clk[IMX5_CLK_UART2_PER_GATE] = imx_clk_gate2("uart2_per_gate", "uart_root", MXC_CCM_CCGR1, 12);
207 clk[IMX5_CLK_UART3_IPG_GATE] = imx_clk_gate2("uart3_ipg_gate", "ipg", MXC_CCM_CCGR1, 14);
208 clk[IMX5_CLK_UART3_PER_GATE] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16);
209 clk[IMX5_CLK_I2C1_GATE] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18);
210 clk[IMX5_CLK_I2C2_GATE] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20);
211 clk[IMX5_CLK_PWM1_IPG_GATE] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10);
212 clk[IMX5_CLK_PWM1_HF_GATE] = imx_clk_gate2("pwm1_hf_gate", "per_root", MXC_CCM_CCGR2, 12);
213 clk[IMX5_CLK_PWM2_IPG_GATE] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14);
214 clk[IMX5_CLK_PWM2_HF_GATE] = imx_clk_gate2("pwm2_hf_gate", "per_root", MXC_CCM_CCGR2, 16);
215 clk[IMX5_CLK_GPT_IPG_GATE] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18);
216 clk[IMX5_CLK_GPT_HF_GATE] = imx_clk_gate2("gpt_hf_gate", "per_root", MXC_CCM_CCGR2, 20);
217 clk[IMX5_CLK_FEC_GATE] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24);
218 clk[IMX5_CLK_USBOH3_GATE] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26);
219 clk[IMX5_CLK_USBOH3_PER_GATE] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28);
220 clk[IMX5_CLK_ESDHC1_IPG_GATE] = imx_clk_gate2("esdhc1_ipg_gate", "ipg", MXC_CCM_CCGR3, 0);
221 clk[IMX5_CLK_ESDHC2_IPG_GATE] = imx_clk_gate2("esdhc2_ipg_gate", "ipg", MXC_CCM_CCGR3, 4);
222 clk[IMX5_CLK_ESDHC3_IPG_GATE] = imx_clk_gate2("esdhc3_ipg_gate", "ipg", MXC_CCM_CCGR3, 8);
223 clk[IMX5_CLK_ESDHC4_IPG_GATE] = imx_clk_gate2("esdhc4_ipg_gate", "ipg", MXC_CCM_CCGR3, 12);
224 clk[IMX5_CLK_SSI1_IPG_GATE] = imx_clk_gate2("ssi1_ipg_gate", "ipg", MXC_CCM_CCGR3, 16);
225 clk[IMX5_CLK_SSI2_IPG_GATE] = imx_clk_gate2("ssi2_ipg_gate", "ipg", MXC_CCM_CCGR3, 20);
226 clk[IMX5_CLK_SSI3_IPG_GATE] = imx_clk_gate2("ssi3_ipg_gate", "ipg", MXC_CCM_CCGR3, 24);
227 clk[IMX5_CLK_ECSPI1_IPG_GATE] = imx_clk_gate2("ecspi1_ipg_gate", "ipg", MXC_CCM_CCGR4, 18);
228 clk[IMX5_CLK_ECSPI1_PER_GATE] = imx_clk_gate2("ecspi1_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 20);
229 clk[IMX5_CLK_ECSPI2_IPG_GATE] = imx_clk_gate2("ecspi2_ipg_gate", "ipg", MXC_CCM_CCGR4, 22);
230 clk[IMX5_CLK_ECSPI2_PER_GATE] = imx_clk_gate2("ecspi2_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 24);
231 clk[IMX5_CLK_CSPI_IPG_GATE] = imx_clk_gate2("cspi_ipg_gate", "ipg", MXC_CCM_CCGR4, 26);
232 clk[IMX5_CLK_SDMA_GATE] = imx_clk_gate2("sdma_gate", "ipg", MXC_CCM_CCGR4, 30);
233 clk[IMX5_CLK_EMI_FAST_GATE] = imx_clk_gate2("emi_fast_gate", "dummy", MXC_CCM_CCGR5, 14);
234 clk[IMX5_CLK_EMI_SLOW_GATE] = imx_clk_gate2("emi_slow_gate", "emi_slow_podf", MXC_CCM_CCGR5, 16);
235 clk[IMX5_CLK_IPU_SEL] = imx_clk_mux("ipu_sel", MXC_CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel));
236 clk[IMX5_CLK_IPU_GATE] = imx_clk_gate2("ipu_gate", "ipu_sel", MXC_CCM_CCGR5, 10);
237 clk[IMX5_CLK_NFC_GATE] = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20);
238 clk[IMX5_CLK_IPU_DI0_GATE] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10);
239 clk[IMX5_CLK_IPU_DI1_GATE] = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12);
240 clk[IMX5_CLK_GPU3D_SEL] = imx_clk_mux("gpu3d_sel", MXC_CCM_CBCMR, 4, 2, gpu3d_sel, ARRAY_SIZE(gpu3d_sel));
241 clk[IMX5_CLK_GPU2D_SEL] = imx_clk_mux("gpu2d_sel", MXC_CCM_CBCMR, 16, 2, gpu2d_sel, ARRAY_SIZE(gpu2d_sel));
242 clk[IMX5_CLK_GPU3D_GATE] = imx_clk_gate2("gpu3d_gate", "gpu3d_sel", MXC_CCM_CCGR5, 2);
243 clk[IMX5_CLK_GARB_GATE] = imx_clk_gate2("garb_gate", "axi_a", MXC_CCM_CCGR5, 4);
244 clk[IMX5_CLK_GPU2D_GATE] = imx_clk_gate2("gpu2d_gate", "gpu2d_sel", MXC_CCM_CCGR6, 14);
245 clk[IMX5_CLK_VPU_SEL] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel));
246 clk[IMX5_CLK_VPU_GATE] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6);
247 clk[IMX5_CLK_VPU_REFERENCE_GATE] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8);
248 clk[IMX5_CLK_UART4_IPG_GATE] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8);
249 clk[IMX5_CLK_UART4_PER_GATE] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10);
250 clk[IMX5_CLK_UART5_IPG_GATE] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12);
251 clk[IMX5_CLK_UART5_PER_GATE] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14);
252 clk[IMX5_CLK_GPC_DVFS] = imx_clk_gate2("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24);
253
254 clk[IMX5_CLK_SSI_APM] = imx_clk_mux("ssi_apm", MXC_CCM_CSCMR1, 8, 2, ssi_apm_sels, ARRAY_SIZE(ssi_apm_sels));
255 clk[IMX5_CLK_SSI1_ROOT_SEL] = imx_clk_mux("ssi1_root_sel", MXC_CCM_CSCMR1, 14, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
256 clk[IMX5_CLK_SSI2_ROOT_SEL] = imx_clk_mux("ssi2_root_sel", MXC_CCM_CSCMR1, 12, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
257 clk[IMX5_CLK_SSI3_ROOT_SEL] = imx_clk_mux("ssi3_root_sel", MXC_CCM_CSCMR1, 11, 1, ssi3_clk_sels, ARRAY_SIZE(ssi3_clk_sels));
258 clk[IMX5_CLK_SSI_EXT1_SEL] = imx_clk_mux("ssi_ext1_sel", MXC_CCM_CSCMR1, 28, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
259 clk[IMX5_CLK_SSI_EXT2_SEL] = imx_clk_mux("ssi_ext2_sel", MXC_CCM_CSCMR1, 30, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
260 clk[IMX5_CLK_SSI_EXT1_COM_SEL] = imx_clk_mux("ssi_ext1_com_sel", MXC_CCM_CSCMR1, 0, 1, ssi_ext1_com_sels, ARRAY_SIZE(ssi_ext1_com_sels));
261 clk[IMX5_CLK_SSI_EXT2_COM_SEL] = imx_clk_mux("ssi_ext2_com_sel", MXC_CCM_CSCMR1, 1, 1, ssi_ext2_com_sels, ARRAY_SIZE(ssi_ext2_com_sels));
262 clk[IMX5_CLK_SSI1_ROOT_PRED] = imx_clk_divider("ssi1_root_pred", "ssi1_root_sel", MXC_CCM_CS1CDR, 6, 3);
263 clk[IMX5_CLK_SSI1_ROOT_PODF] = imx_clk_divider("ssi1_root_podf", "ssi1_root_pred", MXC_CCM_CS1CDR, 0, 6);
264 clk[IMX5_CLK_SSI2_ROOT_PRED] = imx_clk_divider("ssi2_root_pred", "ssi2_root_sel", MXC_CCM_CS2CDR, 6, 3);
265 clk[IMX5_CLK_SSI2_ROOT_PODF] = imx_clk_divider("ssi2_root_podf", "ssi2_root_pred", MXC_CCM_CS2CDR, 0, 6);
266 clk[IMX5_CLK_SSI_EXT1_PRED] = imx_clk_divider("ssi_ext1_pred", "ssi_ext1_sel", MXC_CCM_CS1CDR, 22, 3);
267 clk[IMX5_CLK_SSI_EXT1_PODF] = imx_clk_divider("ssi_ext1_podf", "ssi_ext1_pred", MXC_CCM_CS1CDR, 16, 6);
268 clk[IMX5_CLK_SSI_EXT2_PRED] = imx_clk_divider("ssi_ext2_pred", "ssi_ext2_sel", MXC_CCM_CS2CDR, 22, 3);
269 clk[IMX5_CLK_SSI_EXT2_PODF] = imx_clk_divider("ssi_ext2_podf", "ssi_ext2_pred", MXC_CCM_CS2CDR, 16, 6);
270 clk[IMX5_CLK_SSI1_ROOT_GATE] = imx_clk_gate2("ssi1_root_gate", "ssi1_root_podf", MXC_CCM_CCGR3, 18);
271 clk[IMX5_CLK_SSI2_ROOT_GATE] = imx_clk_gate2("ssi2_root_gate", "ssi2_root_podf", MXC_CCM_CCGR3, 22);
272 clk[IMX5_CLK_SSI3_ROOT_GATE] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26);
273 clk[IMX5_CLK_SSI_EXT1_GATE] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28);
274 clk[IMX5_CLK_SSI_EXT2_GATE] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30);
275 clk[IMX5_CLK_EPIT1_IPG_GATE] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2);
276 clk[IMX5_CLK_EPIT1_HF_GATE] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4);
277 clk[IMX5_CLK_EPIT2_IPG_GATE] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6);
278 clk[IMX5_CLK_EPIT2_HF_GATE] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8);
279 clk[IMX5_CLK_OWIRE_GATE] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22);
280 clk[IMX5_CLK_SRTC_GATE] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28);
281 clk[IMX5_CLK_PATA_GATE] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0);
282 clk[IMX5_CLK_SPDIF0_SEL] = imx_clk_mux("spdif0_sel", MXC_CCM_CSCMR2, 0, 2, spdif_sel, ARRAY_SIZE(spdif_sel));
283 clk[IMX5_CLK_SPDIF0_PRED] = imx_clk_divider("spdif0_pred", "spdif0_sel", MXC_CCM_CDCDR, 25, 3);
284 clk[IMX5_CLK_SPDIF0_PODF] = imx_clk_divider("spdif0_podf", "spdif0_pred", MXC_CCM_CDCDR, 19, 6);
285 clk[IMX5_CLK_SPDIF0_COM_SEL] = imx_clk_mux_flags("spdif0_com_sel", MXC_CCM_CSCMR2, 4, 1,
286 spdif0_com_sel, ARRAY_SIZE(spdif0_com_sel), CLK_SET_RATE_PARENT);
287 clk[IMX5_CLK_SPDIF0_GATE] = imx_clk_gate2("spdif0_gate", "spdif0_com_sel", MXC_CCM_CCGR5, 26);
288 clk[IMX5_CLK_SPDIF_IPG_GATE] = imx_clk_gate2("spdif_ipg_gate", "ipg", MXC_CCM_CCGR5, 30);
289 clk[IMX5_CLK_SAHARA_IPG_GATE] = imx_clk_gate2("sahara_ipg_gate", "ipg", MXC_CCM_CCGR4, 14);
6fb8954b 290 clk[IMX5_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "usb_phy1_gate", 1, 1);
13b3a07a 291
490dd880 292 clk_register_clkdev(clk[IMX5_CLK_CPU_PODF], NULL, "cpu0");
490dd880 293 clk_register_clkdev(clk[IMX5_CLK_GPC_DVFS], "gpc_dvfs", NULL);
b8d4176f
SH		 294
295 /* Set SDHC parents to be PLL2 */
490dd880
LS		 296 clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);
297 clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]);
b8d4176f
SH		 298
299 /* move usb phy clk to 24MHz */
490dd880
LS		 300 clk_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]);
301
302 clk_prepare_enable(clk[IMX5_CLK_GPC_DVFS]);
303 clk_prepare_enable(clk[IMX5_CLK_AHB_MAX]); /* esdhc3 */
304 clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ1]);
305 clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ2]); /* fec */
306 clk_prepare_enable(clk[IMX5_CLK_SPBA]);
307 clk_prepare_enable(clk[IMX5_CLK_EMI_FAST_GATE]); /* fec */
308 clk_prepare_enable(clk[IMX5_CLK_EMI_SLOW_GATE]); /* eim */
309 clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC1_GATE]);
310 clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC2_GATE]);
311 clk_prepare_enable(clk[IMX5_CLK_MIPI_ESC_GATE]);
312 clk_prepare_enable(clk[IMX5_CLK_MIPI_HSP_GATE]);
313 clk_prepare_enable(clk[IMX5_CLK_TMAX1]);
314 clk_prepare_enable(clk[IMX5_CLK_TMAX2]); /* esdhc2, fec */
315 clk_prepare_enable(clk[IMX5_CLK_TMAX3]); /* esdhc1, esdhc4 */
b8d4176f
SH		 316}
317
7a9cc1ad
GU		 318static void __init mx50_clocks_init(struct device_node *np)
319{
18c1d989 320 void __iomem *ccm_base;
20484c13 321 void __iomem *pll_base;
7a9cc1ad 322 unsigned long r;
7a9cc1ad 323
20484c13
SG		 324 pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K);
325 WARN_ON(!pll_base);
326 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base);
327
328 pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K);
329 WARN_ON(!pll_base);
330 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base);
331
332 pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K);
333 WARN_ON(!pll_base);
334 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base);
7a9cc1ad 335
18c1d989
SG		 336 ccm_base = of_iomap(np, 0);
337 WARN_ON(!ccm_base);
338
229be9c1
AS		 339 mx5_clocks_common_init(ccm_base);
340
630a2125
MKB		 341 clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
342 lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
490dd880
LS		 343 clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
344 clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
345 clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
346 clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
347 clk[IMX5_CLK_USB_PHY1_GATE] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
348 clk[IMX5_CLK_USB_PHY2_GATE] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
349 clk[IMX5_CLK_I2C3_GATE] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
7a9cc1ad 350
490dd880
LS		 351 clk[IMX5_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
352 mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
353 clk[IMX5_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3);
354 clk[IMX5_CLK_CKO1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7);
7a9cc1ad 355
490dd880
LS		 356 clk[IMX5_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5,
357 mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
358 clk[IMX5_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
359 clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
7a9cc1ad 360
229be9c1 361 imx_check_clocks(clk, ARRAY_SIZE(clk));
7a9cc1ad
GU		 362
363 clk_data.clks = clk;
364 clk_data.clk_num = ARRAY_SIZE(clk);
365 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
366
7a9cc1ad 367 /* set SDHC root clock to 200MHZ*/
490dd880
LS		 368 clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
369 clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
7a9cc1ad 370
490dd880 371 clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
7a9cc1ad 372 imx_print_silicon_rev("i.MX50", IMX_CHIP_REVISION_1_1);
490dd880 373 clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
7a9cc1ad 374
490dd880
LS		 375 r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
376 clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
7a9cc1ad
GU		 377}
378CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init);
379
c16cc8a0 380static void __init mx51_clocks_init(struct device_node *np)
b8d4176f 381{
18c1d989 382 void __iomem *ccm_base;
20484c13 383 void __iomem *pll_base;
69155fd6 384 u32 val;
b8d4176f 385
20484c13
SG		 386 pll_base = ioremap(MX51_DPLL1_BASE, SZ_16K);
387 WARN_ON(!pll_base);
388 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base);
389
390 pll_base = ioremap(MX51_DPLL2_BASE, SZ_16K);
391 WARN_ON(!pll_base);
392 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base);
393
394 pll_base = ioremap(MX51_DPLL3_BASE, SZ_16K);
395 WARN_ON(!pll_base);
396 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base);
18c1d989
SG		 397
398 ccm_base = of_iomap(np, 0);
399 WARN_ON(!ccm_base);
400
229be9c1
AS		 401 mx5_clocks_common_init(ccm_base);
402
630a2125
MKB		 403 clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
404 lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
490dd880
LS		 405 clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
406 mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel));
407 clk[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
408 mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel));
409 clk[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
410 mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel), CLK_SET_RATE_PARENT);
411 clk[IMX5_CLK_TVE_SEL] = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1,
412 mx51_tve_sel, ARRAY_SIZE(mx51_tve_sel));
413 clk[IMX5_CLK_TVE_GATE] = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30);
414 clk[IMX5_CLK_TVE_PRED] = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3);
415 clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
416 clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6);
417 clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10);
418 clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
419 clk[IMX5_CLK_USB_PHY_GATE] = imx_clk_gate2("usb_phy_gate", "usb_phy_sel", MXC_CCM_CCGR2, 0);
420 clk[IMX5_CLK_HSI2C_GATE] = imx_clk_gate2("hsi2c_gate", "ipg", MXC_CCM_CCGR1, 22);
421 clk[IMX5_CLK_MIPI_HSC1_GATE] = imx_clk_gate2("mipi_hsc1_gate", "ipg", MXC_CCM_CCGR4, 6);
422 clk[IMX5_CLK_MIPI_HSC2_GATE] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8);
423 clk[IMX5_CLK_MIPI_ESC_GATE] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10);
424 clk[IMX5_CLK_MIPI_HSP_GATE] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12);
425 clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
426 mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel));
427 clk[IMX5_CLK_SPDIF1_SEL] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2,
428 spdif_sel, ARRAY_SIZE(spdif_sel));
429 clk[IMX5_CLK_SPDIF1_PRED] = imx_clk_divider("spdif1_pred", "spdif1_sel", MXC_CCM_CDCDR, 16, 3);
430 clk[IMX5_CLK_SPDIF1_PODF] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6);
431 clk[IMX5_CLK_SPDIF1_COM_SEL] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1,
432 mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel));
433 clk[IMX5_CLK_SPDIF1_GATE] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28);
b8d4176f 434
229be9c1 435 imx_check_clocks(clk, ARRAY_SIZE(clk));
b8d4176f 436
f40f38d1
FE		 437 clk_data.clks = clk;
438 clk_data.clk_num = ARRAY_SIZE(clk);
439 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
440
b8d4176f 441 /* set the usboh3 parent to pll2_sw */
490dd880 442 clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]);
b8d4176f
SH		 443
444 /* set SDHC root clock to 166.25MHZ*/
490dd880
LS		 445 clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000);
446 clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000);
b8d4176f 447
490dd880 448 clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
b8d4176f 449 imx_print_silicon_rev("i.MX51", mx51_revision());
490dd880 450 clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
69155fd6
SH		 451
452 /*
453 * Reference Manual says: Functionality of CCDR[18] and CLPCR[23] is no
454 * longer supported. Set to one for better power saving.
455 *
456 * The effect of not setting these bits is that MIPI clocks can't be
457 * enabled without the IPU clock being enabled aswell.
458 */
459 val = readl(MXC_CCM_CCDR);
460 val |= 1 << 18;
461 writel(val, MXC_CCM_CCDR);
462
463 val = readl(MXC_CCM_CLPCR);
464 val |= 1 << 23;
465 writel(val, MXC_CCM_CLPCR);
4d9d18a5 466}
c16cc8a0 467CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init);
4d9d18a5
SH		 468
469static void __init mx53_clocks_init(struct device_node *np)
b8d4176f 470{
18c1d989 471 void __iomem *ccm_base;
20484c13 472 void __iomem *pll_base;
b8d4176f
SH		 473 unsigned long r;
474
20484c13
SG		 475 pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K);
476 WARN_ON(!pll_base);
477 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base);
478
479 pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K);
480 WARN_ON(!pll_base);
481 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base);
482
483 pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K);
484 WARN_ON(!pll_base);
485 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base);
486
487 pll_base = ioremap(MX53_DPLL4_BASE, SZ_16K);
488 WARN_ON(!pll_base);
489 clk[IMX5_CLK_PLL4_SW] = imx_clk_pllv2("pll4_sw", "osc", pll_base);
490dd880 490
18c1d989
SG		 491 ccm_base = of_iomap(np, 0);
492 WARN_ON(!ccm_base);
493
229be9c1
AS		 494 mx5_clocks_common_init(ccm_base);
495
630a2125
MKB		 496 clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
497 lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
490dd880
LS		 498 clk[IMX5_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
499 clk[IMX5_CLK_LDB_DI1_DIV] = imx_clk_divider_flags("ldb_di1_div", "ldb_di1_div_3_5", MXC_CCM_CSCMR2, 11, 1, 0);
500 clk[IMX5_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", MXC_CCM_CSCMR2, 9, 1,
501 mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel), CLK_SET_RATE_PARENT);
502 clk[IMX5_CLK_DI_PLL4_PODF] = imx_clk_divider("di_pll4_podf", "pll4_sw", MXC_CCM_CDCDR, 16, 3);
503 clk[IMX5_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
504 clk[IMX5_CLK_LDB_DI0_DIV] = imx_clk_divider_flags("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2, 10, 1, 0);
505 clk[IMX5_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", MXC_CCM_CSCMR2, 8, 1,
506 mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT);
d5e9b243 507 clk[IMX5_CLK_LDB_DI0_GATE] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28);
490dd880
LS		 508 clk[IMX5_CLK_LDB_DI1_GATE] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30);
509 clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
510 mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel));
511 clk[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
512 mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel));
513 clk[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
514 mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT);
515 clk[IMX5_CLK_TVE_GATE] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30);
516 clk[IMX5_CLK_TVE_PRED] = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3);
517 clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
518 clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
519 clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
520 clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
521 clk[IMX5_CLK_USB_PHY1_GATE] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
522 clk[IMX5_CLK_USB_PHY2_GATE] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
523 clk[IMX5_CLK_CAN_SEL] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2,
524 mx53_can_sel, ARRAY_SIZE(mx53_can_sel));
525 clk[IMX5_CLK_CAN1_SERIAL_GATE] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22);
526 clk[IMX5_CLK_CAN1_IPG_GATE] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20);
527 clk[IMX5_CLK_OCRAM] = imx_clk_gate2("ocram", "ahb", MXC_CCM_CCGR6, 2);
528 clk[IMX5_CLK_CAN2_SERIAL_GATE] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
529 clk[IMX5_CLK_CAN2_IPG_GATE] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
530 clk[IMX5_CLK_I2C3_GATE] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
531 clk[IMX5_CLK_SATA_GATE] = imx_clk_gate2("sata_gate", "ipg", MXC_CCM_CCGR4, 2);
532
533 clk[IMX5_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
534 mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
535 clk[IMX5_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3);
536 clk[IMX5_CLK_CKO1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7);
537
538 clk[IMX5_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5,
539 mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
540 clk[IMX5_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
541 clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
542 clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
543 mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel));
82a40b54
LS		 544 clk[IMX5_CLK_ARM] = imx_clk_cpu("arm", "cpu_podf",
545 clk[IMX5_CLK_CPU_PODF],
546 clk[IMX5_CLK_CPU_PODF_SEL],
547 clk[IMX5_CLK_PLL1_SW],
548 clk[IMX5_CLK_STEP_SEL]);
04b41e84 549
229be9c1 550 imx_check_clocks(clk, ARRAY_SIZE(clk));
b8d4176f 551
f40f38d1
FE		 552 clk_data.clks = clk;
553 clk_data.clk_num = ARRAY_SIZE(clk);
554 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
555
b8d4176f 556 /* set SDHC root clock to 200MHZ*/
490dd880
LS		 557 clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
558 clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
b8d4176f 559
10471fa3
MKB		 560 /* move can bus clk to 24MHz */
561 clk_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]);
562
6f0628aa
LS		 563 /* make sure step clock is running from 24MHz */
564 clk_set_parent(clk[IMX5_CLK_STEP_SEL], clk[IMX5_CLK_LP_APM]);
565
490dd880 566 clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
b8d4176f 567 imx_print_silicon_rev("i.MX53", mx53_revision());
490dd880 568 clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
b8d4176f 569
490dd880
LS		 570 r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
571 clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
b8d4176f 572}
4d9d18a5 573CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init);
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