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b8d4176f SH |
1 | /* |
2 | * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | */ | |
9 | #include <linux/mm.h> | |
10 | #include <linux/delay.h> | |
11 | #include <linux/clk.h> | |
12 | #include <linux/io.h> | |
13 | #include <linux/clkdev.h> | |
4d9d18a5 | 14 | #include <linux/clk-provider.h> |
b8d4176f | 15 | #include <linux/err.h> |
bfcc7bce FE |
16 | #include <linux/of.h> |
17 | #include <linux/of_address.h> | |
18 | #include <linux/of_irq.h> | |
490dd880 | 19 | #include <dt-bindings/clock/imx5-clock.h> |
b8d4176f | 20 | |
b8d4176f SH |
21 | #include "crm-regs-imx5.h" |
22 | #include "clk.h" | |
e3372474 | 23 | #include "common.h" |
50f2de61 | 24 | #include "hardware.h" |
b8d4176f SH |
25 | |
26 | /* Low-power Audio Playback Mode clock */ | |
27 | static const char *lp_apm_sel[] = { "osc", }; | |
28 | ||
29 | /* This is used multiple times */ | |
30 | static const char *standard_pll_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "lp_apm", }; | |
31 | static const char *periph_apm_sel[] = { "pll1_sw", "pll3_sw", "lp_apm", }; | |
32 | static const char *main_bus_sel[] = { "pll2_sw", "periph_apm", }; | |
33 | static const char *per_lp_apm_sel[] = { "main_bus", "lp_apm", }; | |
34 | static const char *per_root_sel[] = { "per_podf", "ipg", }; | |
35 | static const char *esdhc_c_sel[] = { "esdhc_a_podf", "esdhc_b_podf", }; | |
36 | static const char *esdhc_d_sel[] = { "esdhc_a_podf", "esdhc_b_podf", }; | |
13b3a07a SG |
37 | static const char *ssi_apm_sels[] = { "ckih1", "lp_amp", "ckih2", }; |
38 | static const char *ssi_clk_sels[] = { "pll1_sw", "pll2_sw", "pll3_sw", "ssi_apm", }; | |
39 | static const char *ssi3_clk_sels[] = { "ssi1_root_gate", "ssi2_root_gate", }; | |
40 | static const char *ssi_ext1_com_sels[] = { "ssi_ext1_podf", "ssi1_root_gate", }; | |
41 | static const char *ssi_ext2_com_sels[] = { "ssi_ext2_podf", "ssi2_root_gate", }; | |
b8d4176f SH |
42 | static const char *emi_slow_sel[] = { "main_bus", "ahb", }; |
43 | static const char *usb_phy_sel_str[] = { "osc", "usb_phy_podf", }; | |
44 | static const char *mx51_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "tve_di", }; | |
51f66191 | 45 | static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0_gate", }; |
b8d4176f SH |
46 | static const char *mx53_ldb_di0_sel[] = { "pll3_sw", "pll4_sw", }; |
47 | static const char *mx51_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", }; | |
51f66191 | 48 | static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1_gate", }; |
b8d4176f SH |
49 | static const char *mx53_ldb_di1_sel[] = { "pll3_sw", "pll4_sw", }; |
50 | static const char *mx51_tve_ext_sel[] = { "osc", "ckih1", }; | |
51 | static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", }; | |
3f487bed | 52 | static const char *mx51_tve_sel[] = { "tve_pred", "tve_ext_sel", }; |
b8d4176f | 53 | static const char *ipu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", }; |
8ecb167f PZ |
54 | static const char *gpu3d_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb" }; |
55 | static const char *gpu2d_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb" }; | |
b8d4176f | 56 | static const char *vpu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", }; |
a745f039 | 57 | static const char *mx53_can_sel[] = { "ipg", "ckih1", "ckih2", "lp_apm", }; |
04b41e84 MF |
58 | static const char *mx53_cko1_sel[] = { |
59 | "cpu_podf", "pll1_sw", "pll2_sw", "pll3_sw", | |
60 | "emi_slow_podf", "pll4_sw", "nfc_podf", "dummy", | |
61 | "di_pred", "dummy", "dummy", "ahb", | |
62 | "ipg", "per_root", "ckil", "dummy",}; | |
63 | static const char *mx53_cko2_sel[] = { | |
64 | "dummy"/* dptc_core */, "dummy"/* dptc_perich */, | |
65 | "dummy", "esdhc_a_podf", | |
66 | "usboh3_podf", "dummy"/* wrck_clk_root */, | |
67 | "ecspi_podf", "dummy"/* pll1_ref_clk */, | |
68 | "esdhc_b_podf", "dummy"/* ddr_clk_root */, | |
69 | "dummy"/* arm_axi_clk_root */, "dummy"/* usb_phy_out */, | |
70 | "vpu_sel", "ipu_sel", | |
71 | "osc", "ckih1", | |
72 | "dummy", "esdhc_c_sel", | |
73 | "ssi1_root_podf", "ssi2_root_podf", | |
74 | "dummy", "dummy", | |
75 | "dummy"/* lpsr_clk_root */, "dummy"/* pgc_clk_root */, | |
76 | "dummy"/* tve_out */, "usb_phy_sel", | |
77 | "tve_sel", "lp_apm", | |
78 | "uart_root", "dummy"/* spdif0_clk_root */, | |
79 | "dummy", "dummy", }; | |
beb2d1c1 PZ |
80 | static const char *mx51_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", }; |
81 | static const char *mx53_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", "pll4_sw", }; | |
82 | static const char *spdif_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "spdif_xtal_sel", }; | |
83 | static const char *spdif0_com_sel[] = { "spdif0_podf", "ssi1_root_gate", }; | |
84 | static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", }; | |
85 | ||
490dd880 | 86 | static struct clk *clk[IMX5_CLK_END]; |
f40f38d1 | 87 | static struct clk_onecell_data clk_data; |
b8d4176f SH |
88 | |
89 | static void __init mx5_clocks_common_init(unsigned long rate_ckil, | |
90 | unsigned long rate_osc, unsigned long rate_ckih1, | |
91 | unsigned long rate_ckih2) | |
92 | { | |
93 | int i; | |
94 | ||
490dd880 LS |
95 | clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0); |
96 | clk[IMX5_CLK_CKIL] = imx_obtain_fixed_clock("ckil", rate_ckil); | |
97 | clk[IMX5_CLK_OSC] = imx_obtain_fixed_clock("osc", rate_osc); | |
98 | clk[IMX5_CLK_CKIH1] = imx_obtain_fixed_clock("ckih1", rate_ckih1); | |
99 | clk[IMX5_CLK_CKIH2] = imx_obtain_fixed_clock("ckih2", rate_ckih2); | |
100 | ||
101 | clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1, | |
102 | lp_apm_sel, ARRAY_SIZE(lp_apm_sel)); | |
103 | clk[IMX5_CLK_PERIPH_APM] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2, | |
104 | periph_apm_sel, ARRAY_SIZE(periph_apm_sel)); | |
105 | clk[IMX5_CLK_MAIN_BUS] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1, | |
106 | main_bus_sel, ARRAY_SIZE(main_bus_sel)); | |
107 | clk[IMX5_CLK_PER_LP_APM] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1, | |
108 | per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel)); | |
109 | clk[IMX5_CLK_PER_PRED1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2); | |
110 | clk[IMX5_CLK_PER_PRED2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3); | |
111 | clk[IMX5_CLK_PER_PODF] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3); | |
112 | clk[IMX5_CLK_PER_ROOT] = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1, | |
113 | per_root_sel, ARRAY_SIZE(per_root_sel)); | |
114 | clk[IMX5_CLK_AHB] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3); | |
115 | clk[IMX5_CLK_AHB_MAX] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28); | |
116 | clk[IMX5_CLK_AIPS_TZ1] = imx_clk_gate2("aips_tz1", "ahb", MXC_CCM_CCGR0, 24); | |
117 | clk[IMX5_CLK_AIPS_TZ2] = imx_clk_gate2("aips_tz2", "ahb", MXC_CCM_CCGR0, 26); | |
118 | clk[IMX5_CLK_TMAX1] = imx_clk_gate2("tmax1", "ahb", MXC_CCM_CCGR1, 0); | |
119 | clk[IMX5_CLK_TMAX2] = imx_clk_gate2("tmax2", "ahb", MXC_CCM_CCGR1, 2); | |
120 | clk[IMX5_CLK_TMAX3] = imx_clk_gate2("tmax3", "ahb", MXC_CCM_CCGR1, 4); | |
121 | clk[IMX5_CLK_SPBA] = imx_clk_gate2("spba", "ipg", MXC_CCM_CCGR5, 0); | |
122 | clk[IMX5_CLK_IPG] = imx_clk_divider("ipg", "ahb", MXC_CCM_CBCDR, 8, 2); | |
123 | clk[IMX5_CLK_AXI_A] = imx_clk_divider("axi_a", "main_bus", MXC_CCM_CBCDR, 16, 3); | |
124 | clk[IMX5_CLK_AXI_B] = imx_clk_divider("axi_b", "main_bus", MXC_CCM_CBCDR, 19, 3); | |
125 | clk[IMX5_CLK_UART_SEL] = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1, 24, 2, | |
126 | standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); | |
127 | clk[IMX5_CLK_UART_PRED] = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3); | |
128 | clk[IMX5_CLK_UART_ROOT] = imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3); | |
129 | ||
130 | clk[IMX5_CLK_ESDHC_A_SEL] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2, | |
131 | standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); | |
132 | clk[IMX5_CLK_ESDHC_B_SEL] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2, | |
133 | standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); | |
134 | clk[IMX5_CLK_ESDHC_A_PRED] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3); | |
135 | clk[IMX5_CLK_ESDHC_A_PODF] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3); | |
136 | clk[IMX5_CLK_ESDHC_B_PRED] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3); | |
137 | clk[IMX5_CLK_ESDHC_B_PODF] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3); | |
138 | clk[IMX5_CLK_ESDHC_C_SEL] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel)); | |
139 | clk[IMX5_CLK_ESDHC_D_SEL] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel)); | |
140 | ||
141 | clk[IMX5_CLK_EMI_SEL] = imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1, | |
142 | emi_slow_sel, ARRAY_SIZE(emi_slow_sel)); | |
143 | clk[IMX5_CLK_EMI_SLOW_PODF] = imx_clk_divider("emi_slow_podf", "emi_sel", MXC_CCM_CBCDR, 22, 3); | |
144 | clk[IMX5_CLK_NFC_PODF] = imx_clk_divider("nfc_podf", "emi_slow_podf", MXC_CCM_CBCDR, 13, 3); | |
145 | clk[IMX5_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", MXC_CCM_CSCMR1, 4, 2, | |
146 | standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); | |
147 | clk[IMX5_CLK_ECSPI_PRED] = imx_clk_divider("ecspi_pred", "ecspi_sel", MXC_CCM_CSCDR2, 25, 3); | |
148 | clk[IMX5_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf", "ecspi_pred", MXC_CCM_CSCDR2, 19, 6); | |
149 | clk[IMX5_CLK_USBOH3_SEL] = imx_clk_mux("usboh3_sel", MXC_CCM_CSCMR1, 22, 2, | |
150 | standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); | |
151 | clk[IMX5_CLK_USBOH3_PRED] = imx_clk_divider("usboh3_pred", "usboh3_sel", MXC_CCM_CSCDR1, 8, 3); | |
152 | clk[IMX5_CLK_USBOH3_PODF] = imx_clk_divider("usboh3_podf", "usboh3_pred", MXC_CCM_CSCDR1, 6, 2); | |
153 | clk[IMX5_CLK_USB_PHY_PRED] = imx_clk_divider("usb_phy_pred", "pll3_sw", MXC_CCM_CDCDR, 3, 3); | |
154 | clk[IMX5_CLK_USB_PHY_PODF] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3); | |
155 | clk[IMX5_CLK_USB_PHY_SEL] = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1, | |
156 | usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str)); | |
157 | clk[IMX5_CLK_CPU_PODF] = imx_clk_divider("cpu_podf", "pll1_sw", MXC_CCM_CACRR, 0, 3); | |
158 | clk[IMX5_CLK_DI_PRED] = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3); | |
159 | clk[IMX5_CLK_IIM_GATE] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30); | |
160 | clk[IMX5_CLK_UART1_IPG_GATE] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6); | |
161 | clk[IMX5_CLK_UART1_PER_GATE] = imx_clk_gate2("uart1_per_gate", "uart_root", MXC_CCM_CCGR1, 8); | |
162 | clk[IMX5_CLK_UART2_IPG_GATE] = imx_clk_gate2("uart2_ipg_gate", "ipg", MXC_CCM_CCGR1, 10); | |
163 | clk[IMX5_CLK_UART2_PER_GATE] = imx_clk_gate2("uart2_per_gate", "uart_root", MXC_CCM_CCGR1, 12); | |
164 | clk[IMX5_CLK_UART3_IPG_GATE] = imx_clk_gate2("uart3_ipg_gate", "ipg", MXC_CCM_CCGR1, 14); | |
165 | clk[IMX5_CLK_UART3_PER_GATE] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16); | |
166 | clk[IMX5_CLK_I2C1_GATE] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18); | |
167 | clk[IMX5_CLK_I2C2_GATE] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20); | |
168 | clk[IMX5_CLK_PWM1_IPG_GATE] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10); | |
169 | clk[IMX5_CLK_PWM1_HF_GATE] = imx_clk_gate2("pwm1_hf_gate", "per_root", MXC_CCM_CCGR2, 12); | |
170 | clk[IMX5_CLK_PWM2_IPG_GATE] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14); | |
171 | clk[IMX5_CLK_PWM2_HF_GATE] = imx_clk_gate2("pwm2_hf_gate", "per_root", MXC_CCM_CCGR2, 16); | |
172 | clk[IMX5_CLK_GPT_IPG_GATE] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18); | |
173 | clk[IMX5_CLK_GPT_HF_GATE] = imx_clk_gate2("gpt_hf_gate", "per_root", MXC_CCM_CCGR2, 20); | |
174 | clk[IMX5_CLK_FEC_GATE] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24); | |
175 | clk[IMX5_CLK_USBOH3_GATE] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26); | |
176 | clk[IMX5_CLK_USBOH3_PER_GATE] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28); | |
177 | clk[IMX5_CLK_ESDHC1_IPG_GATE] = imx_clk_gate2("esdhc1_ipg_gate", "ipg", MXC_CCM_CCGR3, 0); | |
178 | clk[IMX5_CLK_ESDHC2_IPG_GATE] = imx_clk_gate2("esdhc2_ipg_gate", "ipg", MXC_CCM_CCGR3, 4); | |
179 | clk[IMX5_CLK_ESDHC3_IPG_GATE] = imx_clk_gate2("esdhc3_ipg_gate", "ipg", MXC_CCM_CCGR3, 8); | |
180 | clk[IMX5_CLK_ESDHC4_IPG_GATE] = imx_clk_gate2("esdhc4_ipg_gate", "ipg", MXC_CCM_CCGR3, 12); | |
181 | clk[IMX5_CLK_SSI1_IPG_GATE] = imx_clk_gate2("ssi1_ipg_gate", "ipg", MXC_CCM_CCGR3, 16); | |
182 | clk[IMX5_CLK_SSI2_IPG_GATE] = imx_clk_gate2("ssi2_ipg_gate", "ipg", MXC_CCM_CCGR3, 20); | |
183 | clk[IMX5_CLK_SSI3_IPG_GATE] = imx_clk_gate2("ssi3_ipg_gate", "ipg", MXC_CCM_CCGR3, 24); | |
184 | clk[IMX5_CLK_ECSPI1_IPG_GATE] = imx_clk_gate2("ecspi1_ipg_gate", "ipg", MXC_CCM_CCGR4, 18); | |
185 | clk[IMX5_CLK_ECSPI1_PER_GATE] = imx_clk_gate2("ecspi1_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 20); | |
186 | clk[IMX5_CLK_ECSPI2_IPG_GATE] = imx_clk_gate2("ecspi2_ipg_gate", "ipg", MXC_CCM_CCGR4, 22); | |
187 | clk[IMX5_CLK_ECSPI2_PER_GATE] = imx_clk_gate2("ecspi2_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 24); | |
188 | clk[IMX5_CLK_CSPI_IPG_GATE] = imx_clk_gate2("cspi_ipg_gate", "ipg", MXC_CCM_CCGR4, 26); | |
189 | clk[IMX5_CLK_SDMA_GATE] = imx_clk_gate2("sdma_gate", "ipg", MXC_CCM_CCGR4, 30); | |
190 | clk[IMX5_CLK_EMI_FAST_GATE] = imx_clk_gate2("emi_fast_gate", "dummy", MXC_CCM_CCGR5, 14); | |
191 | clk[IMX5_CLK_EMI_SLOW_GATE] = imx_clk_gate2("emi_slow_gate", "emi_slow_podf", MXC_CCM_CCGR5, 16); | |
192 | clk[IMX5_CLK_IPU_SEL] = imx_clk_mux("ipu_sel", MXC_CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel)); | |
193 | clk[IMX5_CLK_IPU_GATE] = imx_clk_gate2("ipu_gate", "ipu_sel", MXC_CCM_CCGR5, 10); | |
194 | clk[IMX5_CLK_NFC_GATE] = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20); | |
195 | clk[IMX5_CLK_IPU_DI0_GATE] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10); | |
196 | clk[IMX5_CLK_IPU_DI1_GATE] = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12); | |
197 | clk[IMX5_CLK_GPU3D_SEL] = imx_clk_mux("gpu3d_sel", MXC_CCM_CBCMR, 4, 2, gpu3d_sel, ARRAY_SIZE(gpu3d_sel)); | |
198 | clk[IMX5_CLK_GPU2D_SEL] = imx_clk_mux("gpu2d_sel", MXC_CCM_CBCMR, 16, 2, gpu2d_sel, ARRAY_SIZE(gpu2d_sel)); | |
199 | clk[IMX5_CLK_GPU3D_GATE] = imx_clk_gate2("gpu3d_gate", "gpu3d_sel", MXC_CCM_CCGR5, 2); | |
200 | clk[IMX5_CLK_GARB_GATE] = imx_clk_gate2("garb_gate", "axi_a", MXC_CCM_CCGR5, 4); | |
201 | clk[IMX5_CLK_GPU2D_GATE] = imx_clk_gate2("gpu2d_gate", "gpu2d_sel", MXC_CCM_CCGR6, 14); | |
202 | clk[IMX5_CLK_VPU_SEL] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel)); | |
203 | clk[IMX5_CLK_VPU_GATE] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6); | |
204 | clk[IMX5_CLK_VPU_REFERENCE_GATE] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8); | |
205 | clk[IMX5_CLK_UART4_IPG_GATE] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8); | |
206 | clk[IMX5_CLK_UART4_PER_GATE] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10); | |
207 | clk[IMX5_CLK_UART5_IPG_GATE] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12); | |
208 | clk[IMX5_CLK_UART5_PER_GATE] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14); | |
209 | clk[IMX5_CLK_GPC_DVFS] = imx_clk_gate2("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24); | |
210 | ||
211 | clk[IMX5_CLK_SSI_APM] = imx_clk_mux("ssi_apm", MXC_CCM_CSCMR1, 8, 2, ssi_apm_sels, ARRAY_SIZE(ssi_apm_sels)); | |
212 | clk[IMX5_CLK_SSI1_ROOT_SEL] = imx_clk_mux("ssi1_root_sel", MXC_CCM_CSCMR1, 14, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); | |
213 | clk[IMX5_CLK_SSI2_ROOT_SEL] = imx_clk_mux("ssi2_root_sel", MXC_CCM_CSCMR1, 12, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); | |
214 | clk[IMX5_CLK_SSI3_ROOT_SEL] = imx_clk_mux("ssi3_root_sel", MXC_CCM_CSCMR1, 11, 1, ssi3_clk_sels, ARRAY_SIZE(ssi3_clk_sels)); | |
215 | clk[IMX5_CLK_SSI_EXT1_SEL] = imx_clk_mux("ssi_ext1_sel", MXC_CCM_CSCMR1, 28, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); | |
216 | clk[IMX5_CLK_SSI_EXT2_SEL] = imx_clk_mux("ssi_ext2_sel", MXC_CCM_CSCMR1, 30, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); | |
217 | clk[IMX5_CLK_SSI_EXT1_COM_SEL] = imx_clk_mux("ssi_ext1_com_sel", MXC_CCM_CSCMR1, 0, 1, ssi_ext1_com_sels, ARRAY_SIZE(ssi_ext1_com_sels)); | |
218 | clk[IMX5_CLK_SSI_EXT2_COM_SEL] = imx_clk_mux("ssi_ext2_com_sel", MXC_CCM_CSCMR1, 1, 1, ssi_ext2_com_sels, ARRAY_SIZE(ssi_ext2_com_sels)); | |
219 | clk[IMX5_CLK_SSI1_ROOT_PRED] = imx_clk_divider("ssi1_root_pred", "ssi1_root_sel", MXC_CCM_CS1CDR, 6, 3); | |
220 | clk[IMX5_CLK_SSI1_ROOT_PODF] = imx_clk_divider("ssi1_root_podf", "ssi1_root_pred", MXC_CCM_CS1CDR, 0, 6); | |
221 | clk[IMX5_CLK_SSI2_ROOT_PRED] = imx_clk_divider("ssi2_root_pred", "ssi2_root_sel", MXC_CCM_CS2CDR, 6, 3); | |
222 | clk[IMX5_CLK_SSI2_ROOT_PODF] = imx_clk_divider("ssi2_root_podf", "ssi2_root_pred", MXC_CCM_CS2CDR, 0, 6); | |
223 | clk[IMX5_CLK_SSI_EXT1_PRED] = imx_clk_divider("ssi_ext1_pred", "ssi_ext1_sel", MXC_CCM_CS1CDR, 22, 3); | |
224 | clk[IMX5_CLK_SSI_EXT1_PODF] = imx_clk_divider("ssi_ext1_podf", "ssi_ext1_pred", MXC_CCM_CS1CDR, 16, 6); | |
225 | clk[IMX5_CLK_SSI_EXT2_PRED] = imx_clk_divider("ssi_ext2_pred", "ssi_ext2_sel", MXC_CCM_CS2CDR, 22, 3); | |
226 | clk[IMX5_CLK_SSI_EXT2_PODF] = imx_clk_divider("ssi_ext2_podf", "ssi_ext2_pred", MXC_CCM_CS2CDR, 16, 6); | |
227 | clk[IMX5_CLK_SSI1_ROOT_GATE] = imx_clk_gate2("ssi1_root_gate", "ssi1_root_podf", MXC_CCM_CCGR3, 18); | |
228 | clk[IMX5_CLK_SSI2_ROOT_GATE] = imx_clk_gate2("ssi2_root_gate", "ssi2_root_podf", MXC_CCM_CCGR3, 22); | |
229 | clk[IMX5_CLK_SSI3_ROOT_GATE] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26); | |
230 | clk[IMX5_CLK_SSI_EXT1_GATE] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28); | |
231 | clk[IMX5_CLK_SSI_EXT2_GATE] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30); | |
232 | clk[IMX5_CLK_EPIT1_IPG_GATE] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2); | |
233 | clk[IMX5_CLK_EPIT1_HF_GATE] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4); | |
234 | clk[IMX5_CLK_EPIT2_IPG_GATE] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6); | |
235 | clk[IMX5_CLK_EPIT2_HF_GATE] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8); | |
236 | clk[IMX5_CLK_OWIRE_GATE] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22); | |
237 | clk[IMX5_CLK_SRTC_GATE] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28); | |
238 | clk[IMX5_CLK_PATA_GATE] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0); | |
239 | clk[IMX5_CLK_SPDIF0_SEL] = imx_clk_mux("spdif0_sel", MXC_CCM_CSCMR2, 0, 2, spdif_sel, ARRAY_SIZE(spdif_sel)); | |
240 | clk[IMX5_CLK_SPDIF0_PRED] = imx_clk_divider("spdif0_pred", "spdif0_sel", MXC_CCM_CDCDR, 25, 3); | |
241 | clk[IMX5_CLK_SPDIF0_PODF] = imx_clk_divider("spdif0_podf", "spdif0_pred", MXC_CCM_CDCDR, 19, 6); | |
242 | clk[IMX5_CLK_SPDIF0_COM_SEL] = imx_clk_mux_flags("spdif0_com_sel", MXC_CCM_CSCMR2, 4, 1, | |
243 | spdif0_com_sel, ARRAY_SIZE(spdif0_com_sel), CLK_SET_RATE_PARENT); | |
244 | clk[IMX5_CLK_SPDIF0_GATE] = imx_clk_gate2("spdif0_gate", "spdif0_com_sel", MXC_CCM_CCGR5, 26); | |
245 | clk[IMX5_CLK_SPDIF_IPG_GATE] = imx_clk_gate2("spdif_ipg_gate", "ipg", MXC_CCM_CCGR5, 30); | |
246 | clk[IMX5_CLK_SAHARA_IPG_GATE] = imx_clk_gate2("sahara_ipg_gate", "ipg", MXC_CCM_CCGR4, 14); | |
6fb8954b | 247 | clk[IMX5_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "usb_phy1_gate", 1, 1); |
13b3a07a | 248 | |
b8d4176f SH |
249 | for (i = 0; i < ARRAY_SIZE(clk); i++) |
250 | if (IS_ERR(clk[i])) | |
251 | pr_err("i.MX5 clk %d: register failed with %ld\n", | |
252 | i, PTR_ERR(clk[i])); | |
f1550a1c | 253 | |
490dd880 LS |
254 | clk_register_clkdev(clk[IMX5_CLK_GPT_HF_GATE], "per", "imx-gpt.0"); |
255 | clk_register_clkdev(clk[IMX5_CLK_GPT_IPG_GATE], "ipg", "imx-gpt.0"); | |
256 | clk_register_clkdev(clk[IMX5_CLK_UART1_PER_GATE], "per", "imx21-uart.0"); | |
257 | clk_register_clkdev(clk[IMX5_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0"); | |
258 | clk_register_clkdev(clk[IMX5_CLK_UART2_PER_GATE], "per", "imx21-uart.1"); | |
259 | clk_register_clkdev(clk[IMX5_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1"); | |
260 | clk_register_clkdev(clk[IMX5_CLK_UART3_PER_GATE], "per", "imx21-uart.2"); | |
261 | clk_register_clkdev(clk[IMX5_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2"); | |
262 | clk_register_clkdev(clk[IMX5_CLK_UART4_PER_GATE], "per", "imx21-uart.3"); | |
263 | clk_register_clkdev(clk[IMX5_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3"); | |
264 | clk_register_clkdev(clk[IMX5_CLK_UART5_PER_GATE], "per", "imx21-uart.4"); | |
265 | clk_register_clkdev(clk[IMX5_CLK_UART5_IPG_GATE], "ipg", "imx21-uart.4"); | |
266 | clk_register_clkdev(clk[IMX5_CLK_ECSPI1_PER_GATE], "per", "imx51-ecspi.0"); | |
267 | clk_register_clkdev(clk[IMX5_CLK_ECSPI1_IPG_GATE], "ipg", "imx51-ecspi.0"); | |
268 | clk_register_clkdev(clk[IMX5_CLK_ECSPI2_PER_GATE], "per", "imx51-ecspi.1"); | |
269 | clk_register_clkdev(clk[IMX5_CLK_ECSPI2_IPG_GATE], "ipg", "imx51-ecspi.1"); | |
270 | clk_register_clkdev(clk[IMX5_CLK_CSPI_IPG_GATE], NULL, "imx35-cspi.2"); | |
271 | clk_register_clkdev(clk[IMX5_CLK_PWM1_IPG_GATE], "pwm", "mxc_pwm.0"); | |
272 | clk_register_clkdev(clk[IMX5_CLK_PWM2_IPG_GATE], "pwm", "mxc_pwm.1"); | |
273 | clk_register_clkdev(clk[IMX5_CLK_I2C1_GATE], NULL, "imx21-i2c.0"); | |
274 | clk_register_clkdev(clk[IMX5_CLK_I2C2_GATE], NULL, "imx21-i2c.1"); | |
275 | clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.0"); | |
276 | clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.0"); | |
277 | clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.0"); | |
278 | clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.1"); | |
279 | clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.1"); | |
280 | clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.1"); | |
281 | clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.2"); | |
282 | clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.2"); | |
283 | clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.2"); | |
284 | clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "imx-udc-mx51"); | |
285 | clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "imx-udc-mx51"); | |
286 | clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "imx-udc-mx51"); | |
287 | clk_register_clkdev(clk[IMX5_CLK_NFC_GATE], NULL, "imx51-nand"); | |
288 | clk_register_clkdev(clk[IMX5_CLK_SSI1_IPG_GATE], NULL, "imx-ssi.0"); | |
289 | clk_register_clkdev(clk[IMX5_CLK_SSI2_IPG_GATE], NULL, "imx-ssi.1"); | |
290 | clk_register_clkdev(clk[IMX5_CLK_SSI3_IPG_GATE], NULL, "imx-ssi.2"); | |
291 | clk_register_clkdev(clk[IMX5_CLK_SDMA_GATE], NULL, "imx35-sdma"); | |
292 | clk_register_clkdev(clk[IMX5_CLK_CPU_PODF], NULL, "cpu0"); | |
293 | clk_register_clkdev(clk[IMX5_CLK_IIM_GATE], "iim", NULL); | |
294 | clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx2-wdt.0"); | |
295 | clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx2-wdt.1"); | |
296 | clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx-keypad"); | |
297 | clk_register_clkdev(clk[IMX5_CLK_IPU_DI1_GATE], "di1", "imx-tve.0"); | |
298 | clk_register_clkdev(clk[IMX5_CLK_GPC_DVFS], "gpc_dvfs", NULL); | |
299 | clk_register_clkdev(clk[IMX5_CLK_EPIT1_IPG_GATE], "ipg", "imx-epit.0"); | |
300 | clk_register_clkdev(clk[IMX5_CLK_EPIT1_HF_GATE], "per", "imx-epit.0"); | |
301 | clk_register_clkdev(clk[IMX5_CLK_EPIT2_IPG_GATE], "ipg", "imx-epit.1"); | |
302 | clk_register_clkdev(clk[IMX5_CLK_EPIT2_HF_GATE], "per", "imx-epit.1"); | |
b8d4176f SH |
303 | |
304 | /* Set SDHC parents to be PLL2 */ | |
490dd880 LS |
305 | clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]); |
306 | clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]); | |
b8d4176f SH |
307 | |
308 | /* move usb phy clk to 24MHz */ | |
490dd880 LS |
309 | clk_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]); |
310 | ||
311 | clk_prepare_enable(clk[IMX5_CLK_GPC_DVFS]); | |
312 | clk_prepare_enable(clk[IMX5_CLK_AHB_MAX]); /* esdhc3 */ | |
313 | clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ1]); | |
314 | clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ2]); /* fec */ | |
315 | clk_prepare_enable(clk[IMX5_CLK_SPBA]); | |
316 | clk_prepare_enable(clk[IMX5_CLK_EMI_FAST_GATE]); /* fec */ | |
317 | clk_prepare_enable(clk[IMX5_CLK_EMI_SLOW_GATE]); /* eim */ | |
318 | clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC1_GATE]); | |
319 | clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC2_GATE]); | |
320 | clk_prepare_enable(clk[IMX5_CLK_MIPI_ESC_GATE]); | |
321 | clk_prepare_enable(clk[IMX5_CLK_MIPI_HSP_GATE]); | |
322 | clk_prepare_enable(clk[IMX5_CLK_TMAX1]); | |
323 | clk_prepare_enable(clk[IMX5_CLK_TMAX2]); /* esdhc2, fec */ | |
324 | clk_prepare_enable(clk[IMX5_CLK_TMAX3]); /* esdhc1, esdhc4 */ | |
b8d4176f SH |
325 | } |
326 | ||
7a9cc1ad GU |
327 | static void __init mx50_clocks_init(struct device_node *np) |
328 | { | |
329 | void __iomem *base; | |
330 | unsigned long r; | |
331 | int i, irq; | |
332 | ||
490dd880 LS |
333 | clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE); |
334 | clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE); | |
335 | clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE); | |
7a9cc1ad | 336 | |
490dd880 LS |
337 | clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2); |
338 | clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6); | |
339 | clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10); | |
340 | clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14); | |
341 | clk[IMX5_CLK_USB_PHY1_GATE] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10); | |
342 | clk[IMX5_CLK_USB_PHY2_GATE] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12); | |
343 | clk[IMX5_CLK_I2C3_GATE] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22); | |
7a9cc1ad | 344 | |
490dd880 LS |
345 | clk[IMX5_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4, |
346 | mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel)); | |
347 | clk[IMX5_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3); | |
348 | clk[IMX5_CLK_CKO1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7); | |
7a9cc1ad | 349 | |
490dd880 LS |
350 | clk[IMX5_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5, |
351 | mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel)); | |
352 | clk[IMX5_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3); | |
353 | clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24); | |
7a9cc1ad GU |
354 | |
355 | for (i = 0; i < ARRAY_SIZE(clk); i++) | |
356 | if (IS_ERR(clk[i])) | |
357 | pr_err("i.MX50 clk %d: register failed with %ld\n", | |
358 | i, PTR_ERR(clk[i])); | |
359 | ||
360 | clk_data.clks = clk; | |
361 | clk_data.clk_num = ARRAY_SIZE(clk); | |
362 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | |
363 | ||
364 | mx5_clocks_common_init(0, 0, 0, 0); | |
365 | ||
366 | /* set SDHC root clock to 200MHZ*/ | |
490dd880 LS |
367 | clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000); |
368 | clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000); | |
7a9cc1ad | 369 | |
490dd880 | 370 | clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]); |
7a9cc1ad | 371 | imx_print_silicon_rev("i.MX50", IMX_CHIP_REVISION_1_1); |
490dd880 | 372 | clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); |
7a9cc1ad | 373 | |
490dd880 LS |
374 | r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); |
375 | clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); | |
7a9cc1ad GU |
376 | |
377 | np = of_find_compatible_node(NULL, NULL, "fsl,imx50-gpt"); | |
378 | base = of_iomap(np, 0); | |
379 | WARN_ON(!base); | |
380 | irq = irq_of_parse_and_map(np, 0); | |
381 | mxc_timer_init(base, irq); | |
382 | } | |
383 | CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init); | |
384 | ||
b8d4176f SH |
385 | int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, |
386 | unsigned long rate_ckih1, unsigned long rate_ckih2) | |
387 | { | |
388 | int i; | |
69155fd6 | 389 | u32 val; |
f40f38d1 | 390 | struct device_node *np; |
b8d4176f | 391 | |
490dd880 LS |
392 | clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE); |
393 | clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE); | |
394 | clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", MX51_DPLL3_BASE); | |
395 | clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3, | |
396 | mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel)); | |
397 | clk[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3, | |
398 | mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel)); | |
399 | clk[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1, | |
400 | mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel), CLK_SET_RATE_PARENT); | |
401 | clk[IMX5_CLK_TVE_SEL] = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1, | |
402 | mx51_tve_sel, ARRAY_SIZE(mx51_tve_sel)); | |
403 | clk[IMX5_CLK_TVE_GATE] = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30); | |
404 | clk[IMX5_CLK_TVE_PRED] = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3); | |
405 | clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2); | |
406 | clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6); | |
407 | clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10); | |
408 | clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14); | |
409 | clk[IMX5_CLK_USB_PHY_GATE] = imx_clk_gate2("usb_phy_gate", "usb_phy_sel", MXC_CCM_CCGR2, 0); | |
410 | clk[IMX5_CLK_HSI2C_GATE] = imx_clk_gate2("hsi2c_gate", "ipg", MXC_CCM_CCGR1, 22); | |
411 | clk[IMX5_CLK_MIPI_HSC1_GATE] = imx_clk_gate2("mipi_hsc1_gate", "ipg", MXC_CCM_CCGR4, 6); | |
412 | clk[IMX5_CLK_MIPI_HSC2_GATE] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8); | |
413 | clk[IMX5_CLK_MIPI_ESC_GATE] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10); | |
414 | clk[IMX5_CLK_MIPI_HSP_GATE] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12); | |
415 | clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2, | |
416 | mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel)); | |
417 | clk[IMX5_CLK_SPDIF1_SEL] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2, | |
418 | spdif_sel, ARRAY_SIZE(spdif_sel)); | |
419 | clk[IMX5_CLK_SPDIF1_PRED] = imx_clk_divider("spdif1_pred", "spdif1_sel", MXC_CCM_CDCDR, 16, 3); | |
420 | clk[IMX5_CLK_SPDIF1_PODF] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6); | |
421 | clk[IMX5_CLK_SPDIF1_COM_SEL] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1, | |
422 | mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel)); | |
423 | clk[IMX5_CLK_SPDIF1_GATE] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28); | |
b8d4176f SH |
424 | |
425 | for (i = 0; i < ARRAY_SIZE(clk); i++) | |
426 | if (IS_ERR(clk[i])) | |
427 | pr_err("i.MX51 clk %d: register failed with %ld\n", | |
428 | i, PTR_ERR(clk[i])); | |
429 | ||
f40f38d1 FE |
430 | np = of_find_compatible_node(NULL, NULL, "fsl,imx51-ccm"); |
431 | clk_data.clks = clk; | |
432 | clk_data.clk_num = ARRAY_SIZE(clk); | |
433 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | |
434 | ||
b8d4176f SH |
435 | mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2); |
436 | ||
490dd880 LS |
437 | clk_register_clkdev(clk[IMX5_CLK_HSI2C_GATE], NULL, "imx21-i2c.2"); |
438 | clk_register_clkdev(clk[IMX5_CLK_MX51_MIPI], "mipi_hsp", NULL); | |
439 | clk_register_clkdev(clk[IMX5_CLK_VPU_GATE], NULL, "imx51-vpu.0"); | |
440 | clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx27-fec.0"); | |
441 | clk_register_clkdev(clk[IMX5_CLK_USB_PHY_GATE], "phy", "mxc-ehci.0"); | |
442 | clk_register_clkdev(clk[IMX5_CLK_ESDHC1_IPG_GATE], "ipg", "sdhci-esdhc-imx51.0"); | |
443 | clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.0"); | |
444 | clk_register_clkdev(clk[IMX5_CLK_ESDHC1_PER_GATE], "per", "sdhci-esdhc-imx51.0"); | |
445 | clk_register_clkdev(clk[IMX5_CLK_ESDHC2_IPG_GATE], "ipg", "sdhci-esdhc-imx51.1"); | |
446 | clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.1"); | |
447 | clk_register_clkdev(clk[IMX5_CLK_ESDHC2_PER_GATE], "per", "sdhci-esdhc-imx51.1"); | |
448 | clk_register_clkdev(clk[IMX5_CLK_ESDHC3_IPG_GATE], "ipg", "sdhci-esdhc-imx51.2"); | |
449 | clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.2"); | |
450 | clk_register_clkdev(clk[IMX5_CLK_ESDHC3_PER_GATE], "per", "sdhci-esdhc-imx51.2"); | |
451 | clk_register_clkdev(clk[IMX5_CLK_ESDHC4_IPG_GATE], "ipg", "sdhci-esdhc-imx51.3"); | |
452 | clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.3"); | |
453 | clk_register_clkdev(clk[IMX5_CLK_ESDHC4_PER_GATE], "per", "sdhci-esdhc-imx51.3"); | |
b8d4176f SH |
454 | |
455 | /* set the usboh3 parent to pll2_sw */ | |
490dd880 | 456 | clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]); |
b8d4176f SH |
457 | |
458 | /* set SDHC root clock to 166.25MHZ*/ | |
490dd880 LS |
459 | clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000); |
460 | clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000); | |
b8d4176f SH |
461 | |
462 | /* System timer */ | |
2cfb4518 | 463 | mxc_timer_init(MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), MX51_INT_GPT); |
b8d4176f | 464 | |
490dd880 | 465 | clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]); |
b8d4176f | 466 | imx_print_silicon_rev("i.MX51", mx51_revision()); |
490dd880 | 467 | clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); |
69155fd6 SH |
468 | |
469 | /* | |
470 | * Reference Manual says: Functionality of CCDR[18] and CLPCR[23] is no | |
471 | * longer supported. Set to one for better power saving. | |
472 | * | |
473 | * The effect of not setting these bits is that MIPI clocks can't be | |
474 | * enabled without the IPU clock being enabled aswell. | |
475 | */ | |
476 | val = readl(MXC_CCM_CCDR); | |
477 | val |= 1 << 18; | |
478 | writel(val, MXC_CCM_CCDR); | |
479 | ||
480 | val = readl(MXC_CCM_CLPCR); | |
481 | val |= 1 << 23; | |
482 | writel(val, MXC_CCM_CLPCR); | |
b8d4176f SH |
483 | |
484 | return 0; | |
485 | } | |
486 | ||
4d9d18a5 SH |
487 | static void __init mx51_clocks_init_dt(struct device_node *np) |
488 | { | |
489 | mx51_clocks_init(0, 0, 0, 0); | |
490 | } | |
491 | CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init_dt); | |
492 | ||
493 | static void __init mx53_clocks_init(struct device_node *np) | |
b8d4176f | 494 | { |
bfcc7bce | 495 | int i, irq; |
b8d4176f | 496 | unsigned long r; |
bfcc7bce | 497 | void __iomem *base; |
b8d4176f | 498 | |
490dd880 LS |
499 | clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE); |
500 | clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE); | |
501 | clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE); | |
502 | clk[IMX5_CLK_PLL4_SW] = imx_clk_pllv2("pll4_sw", "osc", MX53_DPLL4_BASE); | |
503 | ||
504 | clk[IMX5_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); | |
505 | clk[IMX5_CLK_LDB_DI1_DIV] = imx_clk_divider_flags("ldb_di1_div", "ldb_di1_div_3_5", MXC_CCM_CSCMR2, 11, 1, 0); | |
506 | clk[IMX5_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", MXC_CCM_CSCMR2, 9, 1, | |
507 | mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel), CLK_SET_RATE_PARENT); | |
508 | clk[IMX5_CLK_DI_PLL4_PODF] = imx_clk_divider("di_pll4_podf", "pll4_sw", MXC_CCM_CDCDR, 16, 3); | |
509 | clk[IMX5_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); | |
510 | clk[IMX5_CLK_LDB_DI0_DIV] = imx_clk_divider_flags("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2, 10, 1, 0); | |
511 | clk[IMX5_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", MXC_CCM_CSCMR2, 8, 1, | |
512 | mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT); | |
513 | clk[IMX5_CLK_LDB_DI1_GATE] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28); | |
514 | clk[IMX5_CLK_LDB_DI1_GATE] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30); | |
515 | clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3, | |
516 | mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel)); | |
517 | clk[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3, | |
518 | mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel)); | |
519 | clk[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1, | |
520 | mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT); | |
521 | clk[IMX5_CLK_TVE_GATE] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30); | |
522 | clk[IMX5_CLK_TVE_PRED] = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3); | |
523 | clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2); | |
524 | clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6); | |
525 | clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10); | |
526 | clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14); | |
527 | clk[IMX5_CLK_USB_PHY1_GATE] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10); | |
528 | clk[IMX5_CLK_USB_PHY2_GATE] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12); | |
529 | clk[IMX5_CLK_CAN_SEL] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2, | |
530 | mx53_can_sel, ARRAY_SIZE(mx53_can_sel)); | |
531 | clk[IMX5_CLK_CAN1_SERIAL_GATE] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22); | |
532 | clk[IMX5_CLK_CAN1_IPG_GATE] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20); | |
533 | clk[IMX5_CLK_OCRAM] = imx_clk_gate2("ocram", "ahb", MXC_CCM_CCGR6, 2); | |
534 | clk[IMX5_CLK_CAN2_SERIAL_GATE] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8); | |
535 | clk[IMX5_CLK_CAN2_IPG_GATE] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6); | |
536 | clk[IMX5_CLK_I2C3_GATE] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22); | |
537 | clk[IMX5_CLK_SATA_GATE] = imx_clk_gate2("sata_gate", "ipg", MXC_CCM_CCGR4, 2); | |
538 | ||
539 | clk[IMX5_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4, | |
540 | mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel)); | |
541 | clk[IMX5_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3); | |
542 | clk[IMX5_CLK_CKO1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7); | |
543 | ||
544 | clk[IMX5_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5, | |
545 | mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel)); | |
546 | clk[IMX5_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3); | |
547 | clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24); | |
548 | clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2, | |
549 | mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel)); | |
04b41e84 | 550 | |
b8d4176f SH |
551 | for (i = 0; i < ARRAY_SIZE(clk); i++) |
552 | if (IS_ERR(clk[i])) | |
553 | pr_err("i.MX53 clk %d: register failed with %ld\n", | |
554 | i, PTR_ERR(clk[i])); | |
555 | ||
f40f38d1 FE |
556 | clk_data.clks = clk; |
557 | clk_data.clk_num = ARRAY_SIZE(clk); | |
558 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | |
559 | ||
4d9d18a5 | 560 | mx5_clocks_common_init(0, 0, 0, 0); |
b8d4176f | 561 | |
490dd880 LS |
562 | clk_register_clkdev(clk[IMX5_CLK_VPU_GATE], NULL, "imx53-vpu.0"); |
563 | clk_register_clkdev(clk[IMX5_CLK_I2C3_GATE], NULL, "imx21-i2c.2"); | |
564 | clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx25-fec.0"); | |
565 | clk_register_clkdev(clk[IMX5_CLK_USB_PHY1_GATE], "usb_phy1", "mxc-ehci.0"); | |
566 | clk_register_clkdev(clk[IMX5_CLK_ESDHC1_IPG_GATE], "ipg", "sdhci-esdhc-imx53.0"); | |
567 | clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.0"); | |
568 | clk_register_clkdev(clk[IMX5_CLK_ESDHC1_PER_GATE], "per", "sdhci-esdhc-imx53.0"); | |
569 | clk_register_clkdev(clk[IMX5_CLK_ESDHC2_IPG_GATE], "ipg", "sdhci-esdhc-imx53.1"); | |
570 | clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.1"); | |
571 | clk_register_clkdev(clk[IMX5_CLK_ESDHC2_PER_GATE], "per", "sdhci-esdhc-imx53.1"); | |
572 | clk_register_clkdev(clk[IMX5_CLK_ESDHC3_IPG_GATE], "ipg", "sdhci-esdhc-imx53.2"); | |
573 | clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.2"); | |
574 | clk_register_clkdev(clk[IMX5_CLK_ESDHC3_PER_GATE], "per", "sdhci-esdhc-imx53.2"); | |
575 | clk_register_clkdev(clk[IMX5_CLK_ESDHC4_IPG_GATE], "ipg", "sdhci-esdhc-imx53.3"); | |
576 | clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.3"); | |
577 | clk_register_clkdev(clk[IMX5_CLK_ESDHC4_PER_GATE], "per", "sdhci-esdhc-imx53.3"); | |
b8d4176f SH |
578 | |
579 | /* set SDHC root clock to 200MHZ*/ | |
490dd880 LS |
580 | clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000); |
581 | clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000); | |
b8d4176f | 582 | |
490dd880 | 583 | clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]); |
b8d4176f | 584 | imx_print_silicon_rev("i.MX53", mx53_revision()); |
490dd880 | 585 | clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); |
b8d4176f | 586 | |
490dd880 LS |
587 | r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); |
588 | clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); | |
bfcc7bce FE |
589 | |
590 | np = of_find_compatible_node(NULL, NULL, "fsl,imx53-gpt"); | |
591 | base = of_iomap(np, 0); | |
592 | WARN_ON(!base); | |
593 | irq = irq_of_parse_and_map(np, 0); | |
594 | mxc_timer_init(base, irq); | |
b8d4176f | 595 | } |
4d9d18a5 | 596 | CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init); |