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ARM i.MX5: implement clocks using common clock framework
[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-imx / clk-imx51-imx53.c
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b8d4176f
SH		 1/*
2 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9#include <linux/mm.h>
10#include <linux/delay.h>
11#include <linux/clk.h>
12#include <linux/io.h>
13#include <linux/clkdev.h>
14#include <linux/of.h>
15#include <linux/err.h>
16
17#include <mach/hardware.h>
18#include <mach/common.h>
19
20#include "crm-regs-imx5.h"
21#include "clk.h"
22
23/* Low-power Audio Playback Mode clock */
24static const char *lp_apm_sel[] = { "osc", };
25
26/* This is used multiple times */
27static const char *standard_pll_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "lp_apm", };
28static const char *periph_apm_sel[] = { "pll1_sw", "pll3_sw", "lp_apm", };
29static const char *main_bus_sel[] = { "pll2_sw", "periph_apm", };
30static const char *per_lp_apm_sel[] = { "main_bus", "lp_apm", };
31static const char *per_root_sel[] = { "per_podf", "ipg", };
32static const char *esdhc_c_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
33static const char *esdhc_d_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
34static const char *emi_slow_sel[] = { "main_bus", "ahb", };
35static const char *usb_phy_sel_str[] = { "osc", "usb_phy_podf", };
36static const char *mx51_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "tve_di", };
37static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0", };
38static const char *mx53_ldb_di0_sel[] = { "pll3_sw", "pll4_sw", };
39static const char *mx51_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", };
40static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1", };
41static const char *mx53_ldb_di1_sel[] = { "pll3_sw", "pll4_sw", };
42static const char *mx51_tve_ext_sel[] = { "osc", "ckih1", };
43static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", };
44static const char *tve_sel[] = { "tve_pred", "tve_ext_sel", };
45static const char *ipu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
46static const char *vpu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
47
48enum imx5_clks {
49 dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred,
50 uart_root, esdhc_a_pred, esdhc_b_pred, esdhc_c_s, esdhc_d_s,
51 emi_sel, emi_slow_podf, nfc_podf, ecspi_pred, ecspi_podf, usboh3_pred,
52 usboh3_podf, usb_phy_pred, usb_phy_podf, cpu_podf, di_pred, tve_di,
53 tve_s, uart1_ipg_gate, uart1_per_gate, uart2_ipg_gate,
54 uart2_per_gate, uart3_ipg_gate, uart3_per_gate, i2c1_gate, i2c2_gate,
55 gpt_ipg_gate, pwm1_ipg_gate, pwm1_hf_gate, pwm2_ipg_gate, pwm2_hf_gate,
56 gpt_gate, fec_gate, usboh3_per_gate, esdhc1_ipg_gate, esdhc2_ipg_gate,
57 esdhc3_ipg_gate, esdhc4_ipg_gate, ssi1_ipg_gate, ssi2_ipg_gate,
58 ssi3_ipg_gate, ecspi1_ipg_gate, ecspi1_per_gate, ecspi2_ipg_gate,
59 ecspi2_per_gate, cspi_ipg_gate, sdma_gate, emi_slow_gate, ipu_s,
60 ipu_gate, nfc_gate, ipu_di1_gate, vpu_s, vpu_gate,
61 vpu_reference_gate, uart4_ipg_gate, uart4_per_gate, uart5_ipg_gate,
62 uart5_per_gate, tve_gate, tve_pred, esdhc1_per_gate, esdhc2_per_gate,
63 esdhc3_per_gate, esdhc4_per_gate, usb_phy_gate, hsi2c_gate,
64 mipi_hsc1_gate, mipi_hsc2_gate, mipi_esc_gate, mipi_hsp_gate,
65 ldb_di1_div_3_5, ldb_di1_div, ldb_di0_div_3_5, ldb_di0_div,
66 ldb_di1_gate, can2_serial_gate, can2_ipg_gate, i2c3_gate, lp_apm,
67 periph_apm, main_bus, ahb_max, aips_tz1, aips_tz2, tmax1, tmax2,
68 tmax3, spba, uart_sel, esdhc_a_sel, esdhc_b_sel, esdhc_a_podf,
69 esdhc_b_podf, ecspi_sel, usboh3_sel, usb_phy_sel, iim_gate,
70 usboh3_gate, emi_fast_gate, ipu_di0_gate,gpc_dvfs, pll1_sw, pll2_sw,
71 pll3_sw, ipu_di0_sel, ipu_di1_sel, tve_ext_sel, mx51_mipi, pll4_sw,
72 ldb_di1_sel, di_pll4_podf, ldb_di0_sel, ldb_di0_gate, usb_phy1_gate,
73 usb_phy2_gate, per_lp_apm, per_pred1, per_pred2, per_podf, per_root,
74 clk_max
75};
76
77static struct clk *clk[clk_max];
78
79static void __init mx5_clocks_common_init(unsigned long rate_ckil,
80 unsigned long rate_osc, unsigned long rate_ckih1,
81 unsigned long rate_ckih2)
82{
83 int i;
84
85 clk[dummy] = imx_clk_fixed("dummy", 0);
86 clk[ckil] = imx_clk_fixed("ckil", rate_ckil);
87 clk[osc] = imx_clk_fixed("osc", rate_osc);
88 clk[ckih1] = imx_clk_fixed("ckih1", rate_ckih1);
89 clk[ckih2] = imx_clk_fixed("ckih2", rate_ckih2);
90
91 clk[lp_apm] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
92 lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
93 clk[periph_apm] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
94 periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
95 clk[main_bus] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
96 main_bus_sel, ARRAY_SIZE(main_bus_sel));
97 clk[per_lp_apm] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCDR, 1, 1,
98 per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));
99 clk[per_pred1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2);
100 clk[per_pred2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3);
101 clk[per_podf] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3);
102 clk[per_root] = imx_clk_mux("per_root", MXC_CCM_CBCDR, 1, 0,
103 per_root_sel, ARRAY_SIZE(per_root_sel));
104 clk[ahb] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3);
105 clk[ahb_max] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28);
106 clk[aips_tz1] = imx_clk_gate2("aips_tz1", "ahb", MXC_CCM_CCGR0, 24);
107 clk[aips_tz2] = imx_clk_gate2("aips_tz2", "ahb", MXC_CCM_CCGR0, 26);
108 clk[tmax1] = imx_clk_gate2("tmax1", "ahb", MXC_CCM_CCGR1, 0);
109 clk[tmax2] = imx_clk_gate2("tmax2", "ahb", MXC_CCM_CCGR1, 2);
110 clk[tmax3] = imx_clk_gate2("tmax3", "ahb", MXC_CCM_CCGR1, 4);
111 clk[spba] = imx_clk_gate2("spba", "ipg", MXC_CCM_CCGR5, 0);
112 clk[ipg] = imx_clk_divider("ipg", "ahb", MXC_CCM_CBCDR, 8, 2);
113 clk[axi_a] = imx_clk_divider("axi_a", "main_bus", MXC_CCM_CBCDR, 16, 3);
114 clk[axi_b] = imx_clk_divider("axi_b", "main_bus", MXC_CCM_CBCDR, 19, 3);
115 clk[uart_sel] = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1, 24, 2,
116 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
117 clk[uart_pred] = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3);
118 clk[uart_root] = imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3);
119
120 clk[esdhc_a_sel] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2,
121 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
122 clk[esdhc_b_sel] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
123 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
124 clk[esdhc_a_pred] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3);
125 clk[esdhc_a_podf] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3);
126 clk[esdhc_b_pred] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3);
127 clk[esdhc_b_podf] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3);
128 clk[esdhc_c_s] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
129 clk[esdhc_d_s] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
130
131 clk[emi_sel] = imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1,
132 emi_slow_sel, ARRAY_SIZE(emi_slow_sel));
133 clk[emi_slow_podf] = imx_clk_divider("emi_slow_podf", "emi_sel", MXC_CCM_CBCDR, 22, 3);
134 clk[nfc_podf] = imx_clk_divider("nfc_podf", "emi_slow_podf", MXC_CCM_CBCDR, 13, 3);
135 clk[ecspi_sel] = imx_clk_mux("ecspi_sel", MXC_CCM_CSCMR1, 4, 2,
136 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
137 clk[ecspi_pred] = imx_clk_divider("ecspi_pred", "ecspi_sel", MXC_CCM_CSCDR2, 25, 3);
138 clk[ecspi_podf] = imx_clk_divider("ecspi_podf", "ecspi_pred", MXC_CCM_CSCDR2, 19, 6);
139 clk[usboh3_sel] = imx_clk_mux("usboh3_sel", MXC_CCM_CSCMR1, 22, 2,
140 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
141 clk[usboh3_pred] = imx_clk_divider("usboh3_pred", "usboh3_sel", MXC_CCM_CSCDR1, 8, 3);
142 clk[usboh3_podf] = imx_clk_divider("usboh3_podf", "usboh3_pred", MXC_CCM_CSCDR1, 6, 2);
143 clk[usb_phy_pred] = imx_clk_divider("usb_phy_pred", "pll3_sw", MXC_CCM_CDCDR, 3, 3);
144 clk[usb_phy_podf] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3);
145 clk[usb_phy_sel] = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1,
146 usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str));
147 clk[cpu_podf] = imx_clk_divider("cpu_podf", "pll1_sw", MXC_CCM_CACRR, 0, 3);
148 clk[di_pred] = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3);
149 clk[tve_di] = imx_clk_fixed("tve_di", 65000000); /* FIXME */
150 clk[tve_s] = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1, tve_sel, ARRAY_SIZE(tve_sel));
151 clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30);
152 clk[uart1_ipg_gate] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6);
153 clk[uart1_per_gate] = imx_clk_gate2("uart1_per_gate", "uart_root", MXC_CCM_CCGR1, 8);
154 clk[uart2_ipg_gate] = imx_clk_gate2("uart2_ipg_gate", "ipg", MXC_CCM_CCGR1, 10);
155 clk[uart2_per_gate] = imx_clk_gate2("uart2_per_gate", "uart_root", MXC_CCM_CCGR1, 12);
156 clk[uart3_ipg_gate] = imx_clk_gate2("uart3_ipg_gate", "ipg", MXC_CCM_CCGR1, 14);
157 clk[uart3_per_gate] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16);
158 clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18);
159 clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20);
160 clk[gpt_ipg_gate] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 20);
161 clk[pwm1_ipg_gate] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10);
162 clk[pwm1_hf_gate] = imx_clk_gate2("pwm1_hf_gate", "ipg", MXC_CCM_CCGR2, 12);
163 clk[pwm2_ipg_gate] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14);
164 clk[pwm2_hf_gate] = imx_clk_gate2("pwm2_hf_gate", "ipg", MXC_CCM_CCGR2, 16);
165 clk[gpt_gate] = imx_clk_gate2("gpt_gate", "ipg", MXC_CCM_CCGR2, 18);
166 clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24);
167 clk[usboh3_gate] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26);
168 clk[usboh3_per_gate] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28);
169 clk[esdhc1_ipg_gate] = imx_clk_gate2("esdhc1_ipg_gate", "ipg", MXC_CCM_CCGR3, 0);
170 clk[esdhc2_ipg_gate] = imx_clk_gate2("esdhc2_ipg_gate", "ipg", MXC_CCM_CCGR3, 4);
171 clk[esdhc3_ipg_gate] = imx_clk_gate2("esdhc3_ipg_gate", "ipg", MXC_CCM_CCGR3, 8);
172 clk[esdhc4_ipg_gate] = imx_clk_gate2("esdhc4_ipg_gate", "ipg", MXC_CCM_CCGR3, 12);
173 clk[ssi1_ipg_gate] = imx_clk_gate2("ssi1_ipg_gate", "ipg", MXC_CCM_CCGR3, 16);
174 clk[ssi2_ipg_gate] = imx_clk_gate2("ssi2_ipg_gate", "ipg", MXC_CCM_CCGR3, 20);
175 clk[ssi3_ipg_gate] = imx_clk_gate2("ssi3_ipg_gate", "ipg", MXC_CCM_CCGR3, 24);
176 clk[ecspi1_ipg_gate] = imx_clk_gate2("ecspi1_ipg_gate", "ipg", MXC_CCM_CCGR4, 18);
177 clk[ecspi1_per_gate] = imx_clk_gate2("ecspi1_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 20);
178 clk[ecspi2_ipg_gate] = imx_clk_gate2("ecspi2_ipg_gate", "ipg", MXC_CCM_CCGR4, 22);
179 clk[ecspi2_per_gate] = imx_clk_gate2("ecspi2_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 24);
180 clk[cspi_ipg_gate] = imx_clk_gate2("cspi_ipg_gate", "ipg", MXC_CCM_CCGR4, 26);
181 clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ipg", MXC_CCM_CCGR4, 30);
182 clk[emi_fast_gate] = imx_clk_gate2("emi_fast_gate", "dummy", MXC_CCM_CCGR5, 14);
183 clk[emi_slow_gate] = imx_clk_gate2("emi_slow_gate", "emi_slow_podf", MXC_CCM_CCGR5, 16);
184 clk[ipu_s] = imx_clk_mux("ipu_sel", MXC_CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel));
185 clk[ipu_gate] = imx_clk_gate2("ipu_gate", "ipu_sel", MXC_CCM_CCGR5, 10);
186 clk[nfc_gate] = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20);
187 clk[ipu_di0_gate] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10);
188 clk[ipu_di1_gate] = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12);
189 clk[vpu_s] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel));
190 clk[vpu_gate] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6);
191 clk[vpu_reference_gate] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8);
192 clk[uart4_ipg_gate] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8);
193 clk[uart4_per_gate] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10);
194 clk[uart5_ipg_gate] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12);
195 clk[uart5_per_gate] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14);
196 clk[gpc_dvfs] = imx_clk_gate2("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24);
197
198 for (i = 0; i < ARRAY_SIZE(clk); i++)
199 if (IS_ERR(clk[i]))
200 pr_err("i.MX5 clk %d: register failed with %ld\n",
201 i, PTR_ERR(clk[i]));
202
203 clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
204 clk_register_clkdev(clk[gpt_ipg_gate], "ipg", "imx-gpt.0");
205 clk_register_clkdev(clk[uart1_per_gate], "per", "imx21-uart.0");
206 clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
207 clk_register_clkdev(clk[uart2_per_gate], "per", "imx21-uart.1");
208 clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
209 clk_register_clkdev(clk[uart3_per_gate], "per", "imx21-uart.2");
210 clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
211 clk_register_clkdev(clk[uart4_per_gate], "per", "imx21-uart.3");
212 clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
213 clk_register_clkdev(clk[uart5_per_gate], "per", "imx21-uart.4");
214 clk_register_clkdev(clk[uart5_ipg_gate], "ipg", "imx21-uart.4");
215 clk_register_clkdev(clk[ecspi1_per_gate], "per", "imx51-ecspi.0");
216 clk_register_clkdev(clk[ecspi1_ipg_gate], "ipg", "imx51-ecspi.0");
217 clk_register_clkdev(clk[ecspi2_per_gate], "per", "imx51-ecspi.1");
218 clk_register_clkdev(clk[ecspi2_ipg_gate], "ipg", "imx51-ecspi.1");
219 clk_register_clkdev(clk[cspi_ipg_gate], NULL, "imx51-cspi.0");
220 clk_register_clkdev(clk[pwm1_ipg_gate], "pwm", "mxc_pwm.0");
221 clk_register_clkdev(clk[pwm2_ipg_gate], "pwm", "mxc_pwm.1");
222 clk_register_clkdev(clk[i2c1_gate], NULL, "imx-i2c.0");
223 clk_register_clkdev(clk[i2c2_gate], NULL, "imx-i2c.1");
224 clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.0");
225 clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.0");
226 clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.0");
227 clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.1");
228 clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.1");
229 clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.1");
230 clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.2");
231 clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.2");
232 clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.2");
233 clk_register_clkdev(clk[usboh3_per_gate], "per", "fsl-usb2-udc");
234 clk_register_clkdev(clk[usboh3_gate], "ipg", "fsl-usb2-udc");
235 clk_register_clkdev(clk[usboh3_gate], "ahb", "fsl-usb2-udc");
236 clk_register_clkdev(clk[nfc_gate], NULL, "mxc_nand");
237 clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
238 clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
239 clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "imx-ssi.2");
240 clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
241 clk_register_clkdev(clk[cpu_podf], "cpu", NULL);
242 clk_register_clkdev(clk[iim_gate], "iim", NULL);
243 clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.0");
244 clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.1");
245 clk_register_clkdev(clk[dummy], NULL, "imx-keypad");
246 clk_register_clkdev(clk[tve_gate], NULL, "imx-tve.0");
247 clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx-tve.0");
248
249 /* Set SDHC parents to be PLL2 */
250 clk_set_parent(clk[esdhc_a_sel], clk[pll2_sw]);
251 clk_set_parent(clk[esdhc_b_sel], clk[pll2_sw]);
252
253 /* move usb phy clk to 24MHz */
254 clk_set_parent(clk[usb_phy_sel], clk[osc]);
255
256 clk_prepare_enable(clk[gpc_dvfs]);
257 clk_prepare_enable(clk[ahb_max]); /* esdhc3 */
258 clk_prepare_enable(clk[aips_tz1]);
259 clk_prepare_enable(clk[aips_tz2]); /* fec */
260 clk_prepare_enable(clk[spba]);
261 clk_prepare_enable(clk[emi_fast_gate]); /* fec */
262 clk_prepare_enable(clk[tmax1]);
263 clk_prepare_enable(clk[tmax2]); /* esdhc2, fec */
264 clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */
265}
266
267int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
268 unsigned long rate_ckih1, unsigned long rate_ckih2)
269{
270 int i;
271
272 clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE);
273 clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE);
274 clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX51_DPLL3_BASE);
275 clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
276 mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel));
277 clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
278 mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel));
279 clk[tve_ext_sel] = imx_clk_mux("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
280 mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel));
281 clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30);
282 clk[tve_pred] = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3);
283 clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
284 clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6);
285 clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10);
286 clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
287 clk[usb_phy_gate] = imx_clk_gate2("usb_phy_gate", "usb_phy_sel", MXC_CCM_CCGR2, 0);
288 clk[hsi2c_gate] = imx_clk_gate2("hsi2c_gate", "ipg", MXC_CCM_CCGR1, 22);
289 clk[mipi_hsc1_gate] = imx_clk_gate2("mipi_hsc1_gate", "ipg", MXC_CCM_CCGR4, 6);
290 clk[mipi_hsc2_gate] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8);
291 clk[mipi_esc_gate] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10);
292 clk[mipi_hsp_gate] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12);
293
294 for (i = 0; i < ARRAY_SIZE(clk); i++)
295 if (IS_ERR(clk[i]))
296 pr_err("i.MX51 clk %d: register failed with %ld\n",
297 i, PTR_ERR(clk[i]));
298
299 mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
300
301 clk_register_clkdev(clk[hsi2c_gate], NULL, "imx-i2c.2");
302 clk_register_clkdev(clk[mx51_mipi], "mipi_hsp", NULL);
303 clk_register_clkdev(clk[vpu_gate], NULL, "imx51-vpu.0");
304 clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0");
305 clk_register_clkdev(clk[gpc_dvfs], "gpc_dvfs", NULL);
306 clk_register_clkdev(clk[ipu_gate], "bus", "imx51-ipu");
307 clk_register_clkdev(clk[ipu_di0_gate], "di0", "imx51-ipu");
308 clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx51-ipu");
309 clk_register_clkdev(clk[ipu_gate], "hsp", "imx51-ipu");
310 clk_register_clkdev(clk[usb_phy_gate], "phy", "mxc-ehci.0");
311 clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx51.0");
312 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.0");
313 clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx51.0");
314 clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx51.1");
315 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.1");
316 clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx51.1");
317 clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx51.2");
318 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.2");
319 clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx51.2");
320 clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx51.3");
321 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.3");
322 clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx51.3");
323
324 /* set the usboh3 parent to pll2_sw */
325 clk_set_parent(clk[usboh3_sel], clk[pll2_sw]);
326
327 /* set SDHC root clock to 166.25MHZ*/
328 clk_set_rate(clk[esdhc_a_podf], 166250000);
329 clk_set_rate(clk[esdhc_b_podf], 166250000);
330
331 /* System timer */
332 mxc_timer_init(NULL, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
333 MX51_INT_GPT);
334
335 clk_prepare_enable(clk[iim_gate]);
336 imx_print_silicon_rev("i.MX51", mx51_revision());
337 clk_disable_unprepare(clk[iim_gate]);
338
339 return 0;
340}
341
342int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
343 unsigned long rate_ckih1, unsigned long rate_ckih2)
344{
345 int i;
346 unsigned long r;
347
348 clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
349 clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
350 clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
351 clk[pll4_sw] = imx_clk_pllv2("pll4_sw", "osc", MX53_DPLL4_BASE);
352
353 clk[ldb_di1_sel] = imx_clk_mux("ldb_di1_sel", MXC_CCM_CSCMR2, 9, 1,
354 mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel));
355 clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
356 clk[ldb_di1_div] = imx_clk_divider("ldb_di1_div", "ldb_di1_div_3_5", MXC_CCM_CSCMR2, 11, 1);
357 clk[di_pll4_podf] = imx_clk_divider("di_pll4_podf", "pll4_sw", MXC_CCM_CDCDR, 16, 3);
358 clk[ldb_di0_sel] = imx_clk_mux("ldb_di0_sel", MXC_CCM_CSCMR2, 8, 1,
359 mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel));
360 clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
361 clk[ldb_di0_div] = imx_clk_divider("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2, 10, 1);
362 clk[ldb_di0_gate] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28);
363 clk[ldb_di1_gate] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30);
364 clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
365 mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel));
366 clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
367 mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel));
368 clk[tve_ext_sel] = imx_clk_mux("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
369 mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel));
370 clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30);
371 clk[tve_pred] = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3);
372 clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
373 clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
374 clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
375 clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
376 clk[usb_phy1_gate] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
377 clk[usb_phy2_gate] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
378 clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "ipg", MXC_CCM_CCGR4, 6);
379 clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 8);
380 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
381
382 for (i = 0; i < ARRAY_SIZE(clk); i++)
383 if (IS_ERR(clk[i]))
384 pr_err("i.MX53 clk %d: register failed with %ld\n",
385 i, PTR_ERR(clk[i]));
386
387 mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
388
389 clk_register_clkdev(clk[vpu_gate], NULL, "imx53-vpu.0");
390 clk_register_clkdev(clk[i2c3_gate], NULL, "imx-i2c.2");
391 clk_register_clkdev(clk[fec_gate], NULL, "imx25-fec.0");
392 clk_register_clkdev(clk[ipu_gate], "bus", "imx53-ipu");
393 clk_register_clkdev(clk[ipu_di0_gate], "di0", "imx53-ipu");
394 clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx53-ipu");
395 clk_register_clkdev(clk[ipu_gate], "hsp", "imx53-ipu");
396 clk_register_clkdev(clk[usb_phy1_gate], "usb_phy1", "mxc-ehci.0");
397 clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx53.0");
398 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.0");
399 clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx53.0");
400 clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx53.1");
401 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.1");
402 clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx53.1");
403 clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx53.2");
404 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.2");
405 clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx53.2");
406 clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx53.3");
407 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.3");
408 clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx53.3");
409
410 /* set SDHC root clock to 200MHZ*/
411 clk_set_rate(clk[esdhc_a_podf], 200000000);
412 clk_set_rate(clk[esdhc_b_podf], 200000000);
413
414 /* System timer */
415 mxc_timer_init(NULL, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR),
416 MX53_INT_GPT);
417
418 clk_prepare_enable(clk[iim_gate]);
419 imx_print_silicon_rev("i.MX53", mx53_revision());
420 clk_disable_unprepare(clk[iim_gate]);
421
422 r = clk_round_rate(clk[usboh3_per_gate], 54000000);
423 clk_set_rate(clk[usboh3_per_gate], r);
424
425 return 0;
426}
427
428#ifdef CONFIG_OF
429static void __init clk_get_freq_dt(unsigned long *ckil, unsigned long *osc,
430 unsigned long *ckih1, unsigned long *ckih2)
431{
432 struct device_node *np;
433
434 /* retrieve the freqency of fixed clocks from device tree */
435 for_each_compatible_node(np, NULL, "fixed-clock") {
436 u32 rate;
437 if (of_property_read_u32(np, "clock-frequency", &rate))
438 continue;
439
440 if (of_device_is_compatible(np, "fsl,imx-ckil"))
441 *ckil = rate;
442 else if (of_device_is_compatible(np, "fsl,imx-osc"))
443 *osc = rate;
444 else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
445 *ckih1 = rate;
446 else if (of_device_is_compatible(np, "fsl,imx-ckih2"))
447 *ckih2 = rate;
448 }
449}
450
451int __init mx51_clocks_init_dt(void)
452{
453 unsigned long ckil, osc, ckih1, ckih2;
454
455 clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
456 return mx51_clocks_init(ckil, osc, ckih1, ckih2);
457}
458
459int __init mx53_clocks_init_dt(void)
460{
461 unsigned long ckil, osc, ckih1, ckih2;
462
463 clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
464 return mx53_clocks_init(ckil, osc, ckih1, ckih2);
465}
466#endif
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