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ARM i.MX53: Add SATA clock
[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-imx / clk-imx51-imx53.c
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b8d4176f
SH		 1/*
2 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9#include <linux/mm.h>
10#include <linux/delay.h>
11#include <linux/clk.h>
12#include <linux/io.h>
13#include <linux/clkdev.h>
14#include <linux/of.h>
15#include <linux/err.h>
16
b8d4176f
SH		 17#include "crm-regs-imx5.h"
18#include "clk.h"
e3372474 19#include "common.h"
50f2de61 20#include "hardware.h"
b8d4176f
SH		 21
22/* Low-power Audio Playback Mode clock */
23static const char *lp_apm_sel[] = { "osc", };
24
25/* This is used multiple times */
26static const char *standard_pll_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "lp_apm", };
27static const char *periph_apm_sel[] = { "pll1_sw", "pll3_sw", "lp_apm", };
28static const char *main_bus_sel[] = { "pll2_sw", "periph_apm", };
29static const char *per_lp_apm_sel[] = { "main_bus", "lp_apm", };
30static const char *per_root_sel[] = { "per_podf", "ipg", };
31static const char *esdhc_c_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
32static const char *esdhc_d_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
13b3a07a
SG		 33static const char *ssi_apm_sels[] = { "ckih1", "lp_amp", "ckih2", };
34static const char *ssi_clk_sels[] = { "pll1_sw", "pll2_sw", "pll3_sw", "ssi_apm", };
35static const char *ssi3_clk_sels[] = { "ssi1_root_gate", "ssi2_root_gate", };
36static const char *ssi_ext1_com_sels[] = { "ssi_ext1_podf", "ssi1_root_gate", };
37static const char *ssi_ext2_com_sels[] = { "ssi_ext2_podf", "ssi2_root_gate", };
b8d4176f
SH		 38static const char *emi_slow_sel[] = { "main_bus", "ahb", };
39static const char *usb_phy_sel_str[] = { "osc", "usb_phy_podf", };
40static const char *mx51_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "tve_di", };
51f66191 41static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0_gate", };
b8d4176f
SH		 42static const char *mx53_ldb_di0_sel[] = { "pll3_sw", "pll4_sw", };
43static const char *mx51_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", };
51f66191 44static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1_gate", };
b8d4176f
SH		 45static const char *mx53_ldb_di1_sel[] = { "pll3_sw", "pll4_sw", };
46static const char *mx51_tve_ext_sel[] = { "osc", "ckih1", };
47static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", };
3f487bed 48static const char *mx51_tve_sel[] = { "tve_pred", "tve_ext_sel", };
b8d4176f 49static const char *ipu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
8ecb167f
PZ		 50static const char *gpu3d_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb" };
51static const char *gpu2d_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb" };
b8d4176f 52static const char *vpu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
a745f039 53static const char *mx53_can_sel[] = { "ipg", "ckih1", "ckih2", "lp_apm", };
04b41e84
MF		 54static const char *mx53_cko1_sel[] = {
55 "cpu_podf", "pll1_sw", "pll2_sw", "pll3_sw",
56 "emi_slow_podf", "pll4_sw", "nfc_podf", "dummy",
57 "di_pred", "dummy", "dummy", "ahb",
58 "ipg", "per_root", "ckil", "dummy",};
59static const char *mx53_cko2_sel[] = {
60 "dummy"/* dptc_core */, "dummy"/* dptc_perich */,
61 "dummy", "esdhc_a_podf",
62 "usboh3_podf", "dummy"/* wrck_clk_root */,
63 "ecspi_podf", "dummy"/* pll1_ref_clk */,
64 "esdhc_b_podf", "dummy"/* ddr_clk_root */,
65 "dummy"/* arm_axi_clk_root */, "dummy"/* usb_phy_out */,
66 "vpu_sel", "ipu_sel",
67 "osc", "ckih1",
68 "dummy", "esdhc_c_sel",
69 "ssi1_root_podf", "ssi2_root_podf",
70 "dummy", "dummy",
71 "dummy"/* lpsr_clk_root */, "dummy"/* pgc_clk_root */,
72 "dummy"/* tve_out */, "usb_phy_sel",
73 "tve_sel", "lp_apm",
74 "uart_root", "dummy"/* spdif0_clk_root */,
75 "dummy", "dummy", };
b8d4176f
SH		 76
77enum imx5_clks {
78 dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred,
79 uart_root, esdhc_a_pred, esdhc_b_pred, esdhc_c_s, esdhc_d_s,
80 emi_sel, emi_slow_podf, nfc_podf, ecspi_pred, ecspi_podf, usboh3_pred,
d24de495 81 usboh3_podf, usb_phy_pred, usb_phy_podf, cpu_podf, di_pred, tve_di_unused,
b8d4176f
SH		 82 tve_s, uart1_ipg_gate, uart1_per_gate, uart2_ipg_gate,
83 uart2_per_gate, uart3_ipg_gate, uart3_per_gate, i2c1_gate, i2c2_gate,
84 gpt_ipg_gate, pwm1_ipg_gate, pwm1_hf_gate, pwm2_ipg_gate, pwm2_hf_gate,
0f3557c3 85 gpt_hf_gate, fec_gate, usboh3_per_gate, esdhc1_ipg_gate, esdhc2_ipg_gate,
b8d4176f
SH		 86 esdhc3_ipg_gate, esdhc4_ipg_gate, ssi1_ipg_gate, ssi2_ipg_gate,
87 ssi3_ipg_gate, ecspi1_ipg_gate, ecspi1_per_gate, ecspi2_ipg_gate,
88 ecspi2_per_gate, cspi_ipg_gate, sdma_gate, emi_slow_gate, ipu_s,
89 ipu_gate, nfc_gate, ipu_di1_gate, vpu_s, vpu_gate,
90 vpu_reference_gate, uart4_ipg_gate, uart4_per_gate, uart5_ipg_gate,
91 uart5_per_gate, tve_gate, tve_pred, esdhc1_per_gate, esdhc2_per_gate,
92 esdhc3_per_gate, esdhc4_per_gate, usb_phy_gate, hsi2c_gate,
93 mipi_hsc1_gate, mipi_hsc2_gate, mipi_esc_gate, mipi_hsp_gate,
94 ldb_di1_div_3_5, ldb_di1_div, ldb_di0_div_3_5, ldb_di0_div,
95 ldb_di1_gate, can2_serial_gate, can2_ipg_gate, i2c3_gate, lp_apm,
96 periph_apm, main_bus, ahb_max, aips_tz1, aips_tz2, tmax1, tmax2,
97 tmax3, spba, uart_sel, esdhc_a_sel, esdhc_b_sel, esdhc_a_podf,
98 esdhc_b_podf, ecspi_sel, usboh3_sel, usb_phy_sel, iim_gate,
99 usboh3_gate, emi_fast_gate, ipu_di0_gate,gpc_dvfs, pll1_sw, pll2_sw,
100 pll3_sw, ipu_di0_sel, ipu_di1_sel, tve_ext_sel, mx51_mipi, pll4_sw,
101 ldb_di1_sel, di_pll4_podf, ldb_di0_sel, ldb_di0_gate, usb_phy1_gate,
102 usb_phy2_gate, per_lp_apm, per_pred1, per_pred2, per_podf, per_root,
13b3a07a
SG		 103 ssi_apm, ssi1_root_sel, ssi2_root_sel, ssi3_root_sel, ssi_ext1_sel,
104 ssi_ext2_sel, ssi_ext1_com_sel, ssi_ext2_com_sel, ssi1_root_pred,
105 ssi1_root_podf, ssi2_root_pred, ssi2_root_podf, ssi_ext1_pred,
106 ssi_ext1_podf, ssi_ext2_pred, ssi_ext2_podf, ssi1_root_gate,
107 ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate,
d1e9e0ea 108 epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate,
a745f039 109 can_sel, can1_serial_gate, can1_ipg_gate,
8ecb167f 110 owire_gate, gpu3d_s, gpu2d_s, gpu3d_gate, gpu2d_gate, garb_gate,
04b41e84
MF		 111 cko1_sel, cko1_podf, cko1,
112 cko2_sel, cko2_podf, cko2,
c9a74f55 113 srtc_gate, pata_gate, sata_gate,
b8d4176f
SH		 114 clk_max
115};
116
117static struct clk *clk[clk_max];
f40f38d1 118static struct clk_onecell_data clk_data;
b8d4176f
SH		 119
120static void __init mx5_clocks_common_init(unsigned long rate_ckil,
121 unsigned long rate_osc, unsigned long rate_ckih1,
122 unsigned long rate_ckih2)
123{
124 int i;
125
75f83d06
MF		 126 of_clk_init(NULL);
127
b8d4176f 128 clk[dummy] = imx_clk_fixed("dummy", 0);
75f83d06
MF		 129 clk[ckil] = imx_obtain_fixed_clock("ckil", rate_ckil);
130 clk[osc] = imx_obtain_fixed_clock("osc", rate_osc);
131 clk[ckih1] = imx_obtain_fixed_clock("ckih1", rate_ckih1);
132 clk[ckih2] = imx_obtain_fixed_clock("ckih2", rate_ckih2);
b8d4176f
SH		 133
134 clk[lp_apm] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
135 lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
136 clk[periph_apm] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
137 periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
138 clk[main_bus] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
139 main_bus_sel, ARRAY_SIZE(main_bus_sel));
c040be00 140 clk[per_lp_apm] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1,
b8d4176f
SH		 141 per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));
142 clk[per_pred1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2);
143 clk[per_pred2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3);
144 clk[per_podf] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3);
c040be00 145 clk[per_root] = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1,
b8d4176f
SH		 146 per_root_sel, ARRAY_SIZE(per_root_sel));
147 clk[ahb] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3);
148 clk[ahb_max] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28);
149 clk[aips_tz1] = imx_clk_gate2("aips_tz1", "ahb", MXC_CCM_CCGR0, 24);
150 clk[aips_tz2] = imx_clk_gate2("aips_tz2", "ahb", MXC_CCM_CCGR0, 26);
151 clk[tmax1] = imx_clk_gate2("tmax1", "ahb", MXC_CCM_CCGR1, 0);
152 clk[tmax2] = imx_clk_gate2("tmax2", "ahb", MXC_CCM_CCGR1, 2);
153 clk[tmax3] = imx_clk_gate2("tmax3", "ahb", MXC_CCM_CCGR1, 4);
154 clk[spba] = imx_clk_gate2("spba", "ipg", MXC_CCM_CCGR5, 0);
155 clk[ipg] = imx_clk_divider("ipg", "ahb", MXC_CCM_CBCDR, 8, 2);
156 clk[axi_a] = imx_clk_divider("axi_a", "main_bus", MXC_CCM_CBCDR, 16, 3);
157 clk[axi_b] = imx_clk_divider("axi_b", "main_bus", MXC_CCM_CBCDR, 19, 3);
158 clk[uart_sel] = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1, 24, 2,
159 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
160 clk[uart_pred] = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3);
161 clk[uart_root] = imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3);
162
163 clk[esdhc_a_sel] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2,
164 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
165 clk[esdhc_b_sel] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
166 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
167 clk[esdhc_a_pred] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3);
168 clk[esdhc_a_podf] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3);
169 clk[esdhc_b_pred] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3);
170 clk[esdhc_b_podf] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3);
171 clk[esdhc_c_s] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
172 clk[esdhc_d_s] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
173
174 clk[emi_sel] = imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1,
175 emi_slow_sel, ARRAY_SIZE(emi_slow_sel));
176 clk[emi_slow_podf] = imx_clk_divider("emi_slow_podf", "emi_sel", MXC_CCM_CBCDR, 22, 3);
177 clk[nfc_podf] = imx_clk_divider("nfc_podf", "emi_slow_podf", MXC_CCM_CBCDR, 13, 3);
178 clk[ecspi_sel] = imx_clk_mux("ecspi_sel", MXC_CCM_CSCMR1, 4, 2,
179 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
180 clk[ecspi_pred] = imx_clk_divider("ecspi_pred", "ecspi_sel", MXC_CCM_CSCDR2, 25, 3);
181 clk[ecspi_podf] = imx_clk_divider("ecspi_podf", "ecspi_pred", MXC_CCM_CSCDR2, 19, 6);
182 clk[usboh3_sel] = imx_clk_mux("usboh3_sel", MXC_CCM_CSCMR1, 22, 2,
183 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
184 clk[usboh3_pred] = imx_clk_divider("usboh3_pred", "usboh3_sel", MXC_CCM_CSCDR1, 8, 3);
185 clk[usboh3_podf] = imx_clk_divider("usboh3_podf", "usboh3_pred", MXC_CCM_CSCDR1, 6, 2);
186 clk[usb_phy_pred] = imx_clk_divider("usb_phy_pred", "pll3_sw", MXC_CCM_CDCDR, 3, 3);
187 clk[usb_phy_podf] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3);
188 clk[usb_phy_sel] = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1,
189 usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str));
190 clk[cpu_podf] = imx_clk_divider("cpu_podf", "pll1_sw", MXC_CCM_CACRR, 0, 3);
191 clk[di_pred] = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3);
b8d4176f
SH		 192 clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30);
193 clk[uart1_ipg_gate] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6);
194 clk[uart1_per_gate] = imx_clk_gate2("uart1_per_gate", "uart_root", MXC_CCM_CCGR1, 8);
195 clk[uart2_ipg_gate] = imx_clk_gate2("uart2_ipg_gate", "ipg", MXC_CCM_CCGR1, 10);
196 clk[uart2_per_gate] = imx_clk_gate2("uart2_per_gate", "uart_root", MXC_CCM_CCGR1, 12);
197 clk[uart3_ipg_gate] = imx_clk_gate2("uart3_ipg_gate", "ipg", MXC_CCM_CCGR1, 14);
198 clk[uart3_per_gate] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16);
199 clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18);
200 clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20);
b8d4176f 201 clk[pwm1_ipg_gate] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10);
796b72cc 202 clk[pwm1_hf_gate] = imx_clk_gate2("pwm1_hf_gate", "per_root", MXC_CCM_CCGR2, 12);
b8d4176f 203 clk[pwm2_ipg_gate] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14);
796b72cc 204 clk[pwm2_hf_gate] = imx_clk_gate2("pwm2_hf_gate", "per_root", MXC_CCM_CCGR2, 16);
0f3557c3
AS		 205 clk[gpt_ipg_gate] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18);
206 clk[gpt_hf_gate] = imx_clk_gate2("gpt_hf_gate", "per_root", MXC_CCM_CCGR2, 20);
b8d4176f
SH		 207 clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24);
208 clk[usboh3_gate] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26);
209 clk[usboh3_per_gate] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28);
210 clk[esdhc1_ipg_gate] = imx_clk_gate2("esdhc1_ipg_gate", "ipg", MXC_CCM_CCGR3, 0);
211 clk[esdhc2_ipg_gate] = imx_clk_gate2("esdhc2_ipg_gate", "ipg", MXC_CCM_CCGR3, 4);
212 clk[esdhc3_ipg_gate] = imx_clk_gate2("esdhc3_ipg_gate", "ipg", MXC_CCM_CCGR3, 8);
213 clk[esdhc4_ipg_gate] = imx_clk_gate2("esdhc4_ipg_gate", "ipg", MXC_CCM_CCGR3, 12);
214 clk[ssi1_ipg_gate] = imx_clk_gate2("ssi1_ipg_gate", "ipg", MXC_CCM_CCGR3, 16);
215 clk[ssi2_ipg_gate] = imx_clk_gate2("ssi2_ipg_gate", "ipg", MXC_CCM_CCGR3, 20);
216 clk[ssi3_ipg_gate] = imx_clk_gate2("ssi3_ipg_gate", "ipg", MXC_CCM_CCGR3, 24);
217 clk[ecspi1_ipg_gate] = imx_clk_gate2("ecspi1_ipg_gate", "ipg", MXC_CCM_CCGR4, 18);
218 clk[ecspi1_per_gate] = imx_clk_gate2("ecspi1_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 20);
219 clk[ecspi2_ipg_gate] = imx_clk_gate2("ecspi2_ipg_gate", "ipg", MXC_CCM_CCGR4, 22);
220 clk[ecspi2_per_gate] = imx_clk_gate2("ecspi2_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 24);
221 clk[cspi_ipg_gate] = imx_clk_gate2("cspi_ipg_gate", "ipg", MXC_CCM_CCGR4, 26);
222 clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ipg", MXC_CCM_CCGR4, 30);
223 clk[emi_fast_gate] = imx_clk_gate2("emi_fast_gate", "dummy", MXC_CCM_CCGR5, 14);
224 clk[emi_slow_gate] = imx_clk_gate2("emi_slow_gate", "emi_slow_podf", MXC_CCM_CCGR5, 16);
225 clk[ipu_s] = imx_clk_mux("ipu_sel", MXC_CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel));
226 clk[ipu_gate] = imx_clk_gate2("ipu_gate", "ipu_sel", MXC_CCM_CCGR5, 10);
227 clk[nfc_gate] = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20);
228 clk[ipu_di0_gate] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10);
229 clk[ipu_di1_gate] = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12);
8ecb167f
PZ		 230 clk[gpu3d_s] = imx_clk_mux("gpu3d_sel", MXC_CCM_CBCMR, 4, 2, gpu3d_sel, ARRAY_SIZE(gpu3d_sel));
231 clk[gpu2d_s] = imx_clk_mux("gpu2d_sel", MXC_CCM_CBCMR, 16, 2, gpu2d_sel, ARRAY_SIZE(gpu2d_sel));
232 clk[gpu3d_gate] = imx_clk_gate2("gpu3d_gate", "gpu3d_sel", MXC_CCM_CCGR5, 2);
233 clk[garb_gate] = imx_clk_gate2("garb_gate", "axi_a", MXC_CCM_CCGR5, 4);
234 clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "gpu2d_sel", MXC_CCM_CCGR6, 14);
b8d4176f
SH		 235 clk[vpu_s] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel));
236 clk[vpu_gate] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6);
237 clk[vpu_reference_gate] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8);
238 clk[uart4_ipg_gate] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8);
239 clk[uart4_per_gate] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10);
240 clk[uart5_ipg_gate] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12);
241 clk[uart5_per_gate] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14);
242 clk[gpc_dvfs] = imx_clk_gate2("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24);
243
13b3a07a
SG		 244 clk[ssi_apm] = imx_clk_mux("ssi_apm", MXC_CCM_CSCMR1, 8, 2, ssi_apm_sels, ARRAY_SIZE(ssi_apm_sels));
245 clk[ssi1_root_sel] = imx_clk_mux("ssi1_root_sel", MXC_CCM_CSCMR1, 14, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
246 clk[ssi2_root_sel] = imx_clk_mux("ssi2_root_sel", MXC_CCM_CSCMR1, 12, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
247 clk[ssi3_root_sel] = imx_clk_mux("ssi3_root_sel", MXC_CCM_CSCMR1, 11, 1, ssi3_clk_sels, ARRAY_SIZE(ssi3_clk_sels));
248 clk[ssi_ext1_sel] = imx_clk_mux("ssi_ext1_sel", MXC_CCM_CSCMR1, 28, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
249 clk[ssi_ext2_sel] = imx_clk_mux("ssi_ext2_sel", MXC_CCM_CSCMR1, 30, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
250 clk[ssi_ext1_com_sel] = imx_clk_mux("ssi_ext1_com_sel", MXC_CCM_CSCMR1, 0, 1, ssi_ext1_com_sels, ARRAY_SIZE(ssi_ext1_com_sels));
251 clk[ssi_ext2_com_sel] = imx_clk_mux("ssi_ext2_com_sel", MXC_CCM_CSCMR1, 1, 1, ssi_ext2_com_sels, ARRAY_SIZE(ssi_ext2_com_sels));
252 clk[ssi1_root_pred] = imx_clk_divider("ssi1_root_pred", "ssi1_root_sel", MXC_CCM_CS1CDR, 6, 3);
253 clk[ssi1_root_podf] = imx_clk_divider("ssi1_root_podf", "ssi1_root_pred", MXC_CCM_CS1CDR, 0, 6);
254 clk[ssi2_root_pred] = imx_clk_divider("ssi2_root_pred", "ssi2_root_sel", MXC_CCM_CS2CDR, 6, 3);
255 clk[ssi2_root_podf] = imx_clk_divider("ssi2_root_podf", "ssi2_root_pred", MXC_CCM_CS2CDR, 0, 6);
256 clk[ssi_ext1_pred] = imx_clk_divider("ssi_ext1_pred", "ssi_ext1_sel", MXC_CCM_CS1CDR, 22, 3);
257 clk[ssi_ext1_podf] = imx_clk_divider("ssi_ext1_podf", "ssi_ext1_pred", MXC_CCM_CS1CDR, 16, 6);
258 clk[ssi_ext2_pred] = imx_clk_divider("ssi_ext2_pred", "ssi_ext2_sel", MXC_CCM_CS2CDR, 22, 3);
259 clk[ssi_ext2_podf] = imx_clk_divider("ssi_ext2_podf", "ssi_ext2_pred", MXC_CCM_CS2CDR, 16, 6);
260 clk[ssi1_root_gate] = imx_clk_gate2("ssi1_root_gate", "ssi1_root_podf", MXC_CCM_CCGR3, 18);
261 clk[ssi2_root_gate] = imx_clk_gate2("ssi2_root_gate", "ssi2_root_podf", MXC_CCM_CCGR3, 22);
262 clk[ssi3_root_gate] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26);
263 clk[ssi_ext1_gate] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28);
264 clk[ssi_ext2_gate] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30);
d1e9e0ea
AS		 265 clk[epit1_ipg_gate] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2);
266 clk[epit1_hf_gate] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4);
267 clk[epit2_ipg_gate] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6);
268 clk[epit2_hf_gate] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8);
f1550a1c 269 clk[owire_gate] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22);
5d530bb0
SH		 270 clk[srtc_gate] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28);
271 clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0);
13b3a07a 272
b8d4176f
SH		 273 for (i = 0; i < ARRAY_SIZE(clk); i++)
274 if (IS_ERR(clk[i]))
275 pr_err("i.MX5 clk %d: register failed with %ld\n",
276 i, PTR_ERR(clk[i]));
f1550a1c 277
0f3557c3 278 clk_register_clkdev(clk[gpt_hf_gate], "per", "imx-gpt.0");
b8d4176f
SH		 279 clk_register_clkdev(clk[gpt_ipg_gate], "ipg", "imx-gpt.0");
280 clk_register_clkdev(clk[uart1_per_gate], "per", "imx21-uart.0");
281 clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
282 clk_register_clkdev(clk[uart2_per_gate], "per", "imx21-uart.1");
283 clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
284 clk_register_clkdev(clk[uart3_per_gate], "per", "imx21-uart.2");
285 clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
286 clk_register_clkdev(clk[uart4_per_gate], "per", "imx21-uart.3");
287 clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
288 clk_register_clkdev(clk[uart5_per_gate], "per", "imx21-uart.4");
289 clk_register_clkdev(clk[uart5_ipg_gate], "ipg", "imx21-uart.4");
290 clk_register_clkdev(clk[ecspi1_per_gate], "per", "imx51-ecspi.0");
291 clk_register_clkdev(clk[ecspi1_ipg_gate], "ipg", "imx51-ecspi.0");
292 clk_register_clkdev(clk[ecspi2_per_gate], "per", "imx51-ecspi.1");
293 clk_register_clkdev(clk[ecspi2_ipg_gate], "ipg", "imx51-ecspi.1");
e0c29dce 294 clk_register_clkdev(clk[cspi_ipg_gate], NULL, "imx35-cspi.2");
b8d4176f
SH		 295 clk_register_clkdev(clk[pwm1_ipg_gate], "pwm", "mxc_pwm.0");
296 clk_register_clkdev(clk[pwm2_ipg_gate], "pwm", "mxc_pwm.1");
5bdfba29
SG		 297 clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0");
298 clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1");
b8d4176f
SH		 299 clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.0");
300 clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.0");
301 clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.0");
302 clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.1");
303 clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.1");
304 clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.1");
305 clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.2");
306 clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.2");
307 clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.2");
61c4b560
PC		 308 clk_register_clkdev(clk[usboh3_per_gate], "per", "imx-udc-mx51");
309 clk_register_clkdev(clk[usboh3_gate], "ipg", "imx-udc-mx51");
310 clk_register_clkdev(clk[usboh3_gate], "ahb", "imx-udc-mx51");
4d62435f 311 clk_register_clkdev(clk[nfc_gate], NULL, "imx51-nand");
b8d4176f
SH		 312 clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
313 clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
314 clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "imx-ssi.2");
13b3a07a
SG		 315 clk_register_clkdev(clk[ssi_ext1_gate], "ssi_ext1", NULL);
316 clk_register_clkdev(clk[ssi_ext2_gate], "ssi_ext2", NULL);
b8d4176f 317 clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
371b3f18 318 clk_register_clkdev(clk[cpu_podf], NULL, "cpufreq-cpu0.0");
b8d4176f
SH		 319 clk_register_clkdev(clk[iim_gate], "iim", NULL);
320 clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.0");
321 clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.1");
322 clk_register_clkdev(clk[dummy], NULL, "imx-keypad");
b8d4176f 323 clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx-tve.0");
aa96a18d 324 clk_register_clkdev(clk[gpc_dvfs], "gpc_dvfs", NULL);
d1e9e0ea
AS		 325 clk_register_clkdev(clk[epit1_ipg_gate], "ipg", "imx-epit.0");
326 clk_register_clkdev(clk[epit1_hf_gate], "per", "imx-epit.0");
327 clk_register_clkdev(clk[epit2_ipg_gate], "ipg", "imx-epit.1");
328 clk_register_clkdev(clk[epit2_hf_gate], "per", "imx-epit.1");
b8d4176f
SH		 329
330 /* Set SDHC parents to be PLL2 */
331 clk_set_parent(clk[esdhc_a_sel], clk[pll2_sw]);
332 clk_set_parent(clk[esdhc_b_sel], clk[pll2_sw]);
333
334 /* move usb phy clk to 24MHz */
335 clk_set_parent(clk[usb_phy_sel], clk[osc]);
336
337 clk_prepare_enable(clk[gpc_dvfs]);
338 clk_prepare_enable(clk[ahb_max]); /* esdhc3 */
339 clk_prepare_enable(clk[aips_tz1]);
340 clk_prepare_enable(clk[aips_tz2]); /* fec */
341 clk_prepare_enable(clk[spba]);
342 clk_prepare_enable(clk[emi_fast_gate]); /* fec */
68b0562d 343 clk_prepare_enable(clk[emi_slow_gate]); /* eim */
9a2d4825
SH		 344 clk_prepare_enable(clk[mipi_hsc1_gate]);
345 clk_prepare_enable(clk[mipi_hsc2_gate]);
346 clk_prepare_enable(clk[mipi_esc_gate]);
347 clk_prepare_enable(clk[mipi_hsp_gate]);
b8d4176f
SH		 348 clk_prepare_enable(clk[tmax1]);
349 clk_prepare_enable(clk[tmax2]); /* esdhc2, fec */
350 clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */
351}
352
353int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
354 unsigned long rate_ckih1, unsigned long rate_ckih2)
355{
356 int i;
69155fd6 357 u32 val;
f40f38d1 358 struct device_node *np;
b8d4176f
SH		 359
360 clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE);
361 clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE);
362 clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX51_DPLL3_BASE);
363 clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
364 mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel));
365 clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
366 mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel));
80f72d2d
PZ		 367 clk[tve_ext_sel] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
368 mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel), CLK_SET_RATE_PARENT);
3f487bed
PZ		 369 clk[tve_s] = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1,
370 mx51_tve_sel, ARRAY_SIZE(mx51_tve_sel));
b8d4176f
SH		 371 clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30);
372 clk[tve_pred] = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3);
373 clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
374 clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6);
375 clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10);
376 clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
377 clk[usb_phy_gate] = imx_clk_gate2("usb_phy_gate", "usb_phy_sel", MXC_CCM_CCGR2, 0);
378 clk[hsi2c_gate] = imx_clk_gate2("hsi2c_gate", "ipg", MXC_CCM_CCGR1, 22);
379 clk[mipi_hsc1_gate] = imx_clk_gate2("mipi_hsc1_gate", "ipg", MXC_CCM_CCGR4, 6);
380 clk[mipi_hsc2_gate] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8);
381 clk[mipi_esc_gate] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10);
382 clk[mipi_hsp_gate] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12);
383
384 for (i = 0; i < ARRAY_SIZE(clk); i++)
385 if (IS_ERR(clk[i]))
386 pr_err("i.MX51 clk %d: register failed with %ld\n",
387 i, PTR_ERR(clk[i]));
388
f40f38d1
FE		 389 np = of_find_compatible_node(NULL, NULL, "fsl,imx51-ccm");
390 clk_data.clks = clk;
391 clk_data.clk_num = ARRAY_SIZE(clk);
392 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
393
b8d4176f
SH		 394 mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
395
5bdfba29 396 clk_register_clkdev(clk[hsi2c_gate], NULL, "imx21-i2c.2");
b8d4176f
SH		 397 clk_register_clkdev(clk[mx51_mipi], "mipi_hsp", NULL);
398 clk_register_clkdev(clk[vpu_gate], NULL, "imx51-vpu.0");
399 clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0");
b8d4176f
SH		 400 clk_register_clkdev(clk[usb_phy_gate], "phy", "mxc-ehci.0");
401 clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx51.0");
402 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.0");
403 clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx51.0");
404 clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx51.1");
405 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.1");
406 clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx51.1");
407 clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx51.2");
408 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.2");
409 clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx51.2");
410 clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx51.3");
411 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.3");
412 clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx51.3");
413
414 /* set the usboh3 parent to pll2_sw */
415 clk_set_parent(clk[usboh3_sel], clk[pll2_sw]);
416
417 /* set SDHC root clock to 166.25MHZ*/
418 clk_set_rate(clk[esdhc_a_podf], 166250000);
419 clk_set_rate(clk[esdhc_b_podf], 166250000);
420
421 /* System timer */
2cfb4518 422 mxc_timer_init(MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), MX51_INT_GPT);
b8d4176f
SH		 423
424 clk_prepare_enable(clk[iim_gate]);
425 imx_print_silicon_rev("i.MX51", mx51_revision());
426 clk_disable_unprepare(clk[iim_gate]);
69155fd6
SH		 427
428 /*
429 * Reference Manual says: Functionality of CCDR[18] and CLPCR[23] is no
430 * longer supported. Set to one for better power saving.
431 *
432 * The effect of not setting these bits is that MIPI clocks can't be
433 * enabled without the IPU clock being enabled aswell.
434 */
435 val = readl(MXC_CCM_CCDR);
436 val |= 1 << 18;
437 writel(val, MXC_CCM_CCDR);
438
439 val = readl(MXC_CCM_CLPCR);
440 val |= 1 << 23;
441 writel(val, MXC_CCM_CLPCR);
b8d4176f
SH		 442
443 return 0;
444}
445
446int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
447 unsigned long rate_ckih1, unsigned long rate_ckih2)
448{
449 int i;
450 unsigned long r;
f40f38d1 451 struct device_node *np;
b8d4176f
SH		 452
453 clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
454 clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
455 clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
456 clk[pll4_sw] = imx_clk_pllv2("pll4_sw", "osc", MX53_DPLL4_BASE);
457
b8d4176f 458 clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
cc7b6339
PZ		 459 clk[ldb_di1_div] = imx_clk_divider_flags("ldb_di1_div", "ldb_di1_div_3_5", MXC_CCM_CSCMR2, 11, 1, 0);
460 clk[ldb_di1_sel] = imx_clk_mux_flags("ldb_di1_sel", MXC_CCM_CSCMR2, 9, 1,
461 mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel), CLK_SET_RATE_PARENT);
b8d4176f 462 clk[di_pll4_podf] = imx_clk_divider("di_pll4_podf", "pll4_sw", MXC_CCM_CDCDR, 16, 3);
b8d4176f 463 clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
cc7b6339
PZ		 464 clk[ldb_di0_div] = imx_clk_divider_flags("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2, 10, 1, 0);
465 clk[ldb_di0_sel] = imx_clk_mux_flags("ldb_di0_sel", MXC_CCM_CSCMR2, 8, 1,
466 mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT);
b8d4176f
SH		 467 clk[ldb_di0_gate] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28);
468 clk[ldb_di1_gate] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30);
469 clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
470 mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel));
471 clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
472 mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel));
f550e701
PZ		 473 clk[tve_ext_sel] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
474 mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT);
b8d4176f
SH		 475 clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30);
476 clk[tve_pred] = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3);
477 clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
478 clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
479 clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
480 clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
481 clk[usb_phy1_gate] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
482 clk[usb_phy2_gate] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
a745f039
SH		 483 clk[can_sel] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2,
484 mx53_can_sel, ARRAY_SIZE(mx53_can_sel));
485 clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22);
486 clk[can1_ipg_gate] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20);
487 clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
488 clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
b8d4176f 489 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
c9a74f55 490 clk[sata_gate] = imx_clk_gate2("sata_gate", "ipg", MXC_CCM_CCGR4, 2);
b8d4176f 491
04b41e84
MF		 492 clk[cko1_sel] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
493 mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
494 clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3);
495 clk[cko1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7);
496
497 clk[cko2_sel] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5,
498 mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
499 clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
500 clk[cko2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
501
b8d4176f
SH		 502 for (i = 0; i < ARRAY_SIZE(clk); i++)
503 if (IS_ERR(clk[i]))
504 pr_err("i.MX53 clk %d: register failed with %ld\n",
505 i, PTR_ERR(clk[i]));
506
f40f38d1
FE		 507 np = of_find_compatible_node(NULL, NULL, "fsl,imx53-ccm");
508 clk_data.clks = clk;
509 clk_data.clk_num = ARRAY_SIZE(clk);
510 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
511
b8d4176f
SH		 512 mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
513
514 clk_register_clkdev(clk[vpu_gate], NULL, "imx53-vpu.0");
5bdfba29 515 clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2");
b8d4176f 516 clk_register_clkdev(clk[fec_gate], NULL, "imx25-fec.0");
b8d4176f
SH		 517 clk_register_clkdev(clk[usb_phy1_gate], "usb_phy1", "mxc-ehci.0");
518 clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx53.0");
519 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.0");
520 clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx53.0");
521 clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx53.1");
522 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.1");
523 clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx53.1");
524 clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx53.2");
525 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.2");
526 clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx53.2");
527 clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx53.3");
528 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.3");
529 clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx53.3");
530
531 /* set SDHC root clock to 200MHZ*/
532 clk_set_rate(clk[esdhc_a_podf], 200000000);
533 clk_set_rate(clk[esdhc_b_podf], 200000000);
534
535 /* System timer */
2cfb4518 536 mxc_timer_init(MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), MX53_INT_GPT);
b8d4176f
SH		 537
538 clk_prepare_enable(clk[iim_gate]);
539 imx_print_silicon_rev("i.MX53", mx53_revision());
540 clk_disable_unprepare(clk[iim_gate]);
541
542 r = clk_round_rate(clk[usboh3_per_gate], 54000000);
543 clk_set_rate(clk[usboh3_per_gate], r);
544
545 return 0;
546}
547
b8d4176f
SH		 548int __init mx51_clocks_init_dt(void)
549{
75f83d06 550 return mx51_clocks_init(0, 0, 0, 0);
b8d4176f
SH		 551}
552
553int __init mx53_clocks_init_dt(void)
554{
75f83d06 555 return mx53_clocks_init(0, 0, 0, 0);
b8d4176f 556}
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