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2acd1b6f | 1 | /* |
e7b82d64 | 2 | * Copyright 2011-2013 Freescale Semiconductor, Inc. |
2acd1b6f SG |
3 | * Copyright 2011 Linaro Ltd. |
4 | * | |
5 | * The code contained herein is licensed under the GNU General Public | |
6 | * License. You may obtain a copy of the GNU General Public License | |
7 | * Version 2 or later at the following locations: | |
8 | * | |
9 | * http://www.opensource.org/licenses/gpl-license.html | |
10 | * http://www.gnu.org/copyleft/gpl.html | |
11 | */ | |
12 | ||
13 | #include <linux/init.h> | |
14 | #include <linux/types.h> | |
15 | #include <linux/clk.h> | |
16 | #include <linux/clkdev.h> | |
17 | #include <linux/err.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/of.h> | |
20 | #include <linux/of_address.h> | |
21 | #include <linux/of_irq.h> | |
e3372474 | 22 | |
2acd1b6f | 23 | #include "clk.h" |
e3372474 | 24 | #include "common.h" |
2df1d026 | 25 | #include "hardware.h" |
2acd1b6f | 26 | |
2acd1b6f SG |
27 | static const char *step_sels[] = { "osc", "pll2_pfd2_396m", }; |
28 | static const char *pll1_sw_sels[] = { "pll1_sys", "step", }; | |
29 | static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", }; | |
72cd7447 PZ |
30 | static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", }; |
31 | static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", }; | |
2acd1b6f SG |
32 | static const char *periph_sels[] = { "periph_pre", "periph_clk2", }; |
33 | static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", }; | |
a08b9bc5 | 34 | static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", }; |
64990a43 | 35 | static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", }; |
2acd1b6f SG |
36 | static const char *gpu_axi_sels[] = { "axi", "ahb", }; |
37 | static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", }; | |
38 | static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", }; | |
de78a23d | 39 | static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m", }; |
2acd1b6f | 40 | static const char *ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", }; |
cc9a3e99 | 41 | static const char *ldb_di_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", }; |
2df1d026 | 42 | static const char *ipu_di_pre_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", }; |
2acd1b6f SG |
43 | static const char *ipu1_di0_sels[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; |
44 | static const char *ipu1_di1_sels[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; | |
45 | static const char *ipu2_di0_sels[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; | |
46 | static const char *ipu2_di1_sels[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; | |
47 | static const char *hsi_tx_sels[] = { "pll3_120m", "pll2_pfd2_396m", }; | |
48 | static const char *pcie_axi_sels[] = { "axi", "ahb", }; | |
64990a43 | 49 | static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", }; |
2acd1b6f SG |
50 | static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; |
51 | static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", }; | |
3b79cd15 LY |
52 | static const char *emi_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", }; |
53 | static const char *emi_slow_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", }; | |
2acd1b6f SG |
54 | static const char *vdo_axi_sels[] = { "axi", "ahb", }; |
55 | static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", }; | |
2df1d026 | 56 | static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div", |
2acd1b6f | 57 | "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0", |
64990a43 | 58 | "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio_div", }; |
6526bb3c SG |
59 | static const char *cko2_sels[] = { |
60 | "mmdc_ch0_axi", "mmdc_ch1_axi", "usdhc4", "usdhc1", | |
61 | "gpu2d_axi", "dummy", "ecspi_root", "gpu3d_axi", | |
62 | "usdhc3", "dummy", "arm", "ipu1", | |
63 | "ipu2", "vdo_axi", "osc", "gpu2d_core", | |
64 | "gpu3d_core", "usdhc2", "ssi1", "ssi2", | |
65 | "ssi3", "gpu3d_shader", "vpu_axi", "can_root", | |
66 | "ldb_di0", "ldb_di1", "esai", "eim_slow", | |
67 | "uart_serial", "spdif", "asrc", "hsi_tx", | |
68 | }; | |
6cd62235 | 69 | static const char *cko_sels[] = { "cko1", "cko2", }; |
bf221721 SC |
70 | static const char *lvds_sels[] = { |
71 | "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", | |
72 | "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref", | |
03e97220 | 73 | "pcie_ref_125m", "sata_ref_100m", |
bf221721 | 74 | }; |
2acd1b6f | 75 | |
2acd1b6f SG |
76 | enum mx6q_clks { |
77 | dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m, | |
78 | pll3_pfd0_720m, pll3_pfd1_540m, pll3_pfd2_508m, pll3_pfd3_454m, | |
79 | pll2_198m, pll3_120m, pll3_80m, pll3_60m, twd, step, pll1_sw, | |
80 | periph_pre, periph2_pre, periph_clk2_sel, periph2_clk2_sel, axi_sel, | |
81 | esai_sel, asrc_sel, spdif_sel, gpu2d_axi, gpu3d_axi, gpu2d_core_sel, | |
82 | gpu3d_core_sel, gpu3d_shader_sel, ipu1_sel, ipu2_sel, ldb_di0_sel, | |
83 | ldb_di1_sel, ipu1_di0_pre_sel, ipu1_di1_pre_sel, ipu2_di0_pre_sel, | |
84 | ipu2_di1_pre_sel, ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, | |
85 | ipu2_di1_sel, hsi_tx_sel, pcie_axi_sel, ssi1_sel, ssi2_sel, ssi3_sel, | |
86 | usdhc1_sel, usdhc2_sel, usdhc3_sel, usdhc4_sel, enfc_sel, emi_sel, | |
87 | emi_slow_sel, vdo_axi_sel, vpu_axi_sel, cko1_sel, periph, periph2, | |
88 | periph_clk2, periph2_clk2, ipg, ipg_per, esai_pred, esai_podf, | |
89 | asrc_pred, asrc_podf, spdif_pred, spdif_podf, can_root, ecspi_root, | |
90 | gpu2d_core_podf, gpu3d_core_podf, gpu3d_shader, ipu1_podf, ipu2_podf, | |
91 | ldb_di0_podf, ldb_di1_podf, ipu1_di0_pre, ipu1_di1_pre, ipu2_di0_pre, | |
92 | ipu2_di1_pre, hsi_tx_podf, ssi1_pred, ssi1_podf, ssi2_pred, ssi2_podf, | |
93 | ssi3_pred, ssi3_podf, uart_serial_podf, usdhc1_podf, usdhc2_podf, | |
94 | usdhc3_podf, usdhc4_podf, enfc_pred, enfc_podf, emi_podf, | |
95 | emi_slow_podf, vpu_axi_podf, cko1_podf, axi, mmdc_ch0_axi_podf, | |
96 | mmdc_ch1_axi_podf, arm, ahb, apbh_dma, asrc, can1_ipg, can1_serial, | |
97 | can2_ipg, can2_serial, ecspi1, ecspi2, ecspi3, ecspi4, ecspi5, enet, | |
98 | esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb, | |
99 | hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2, | |
100 | ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi, | |
77ac32ad | 101 | mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, per1_bch, |
2acd1b6f SG |
102 | gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1, |
103 | ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3, | |
104 | usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg, | |
13861701 | 105 | pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg, |
16339464 | 106 | ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, |
a5120e89 | 107 | sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate, |
1fa5007b | 108 | usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow, |
bf221721 | 109 | spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, pll4_audio_div, |
886cda41 | 110 | lvds1_sel, lvds2_sel, lvds1_gate, lvds2_gate, esai_ahb, clk_max |
2acd1b6f SG |
111 | }; |
112 | ||
113 | static struct clk *clk[clk_max]; | |
0e87e043 | 114 | static struct clk_onecell_data clk_data; |
2acd1b6f | 115 | |
b0286f20 | 116 | static enum mx6q_clks const clks_init_on[] __initconst = { |
8202a3ce | 117 | mmdc_ch0_axi, rom, arm, |
b0286f20 RZ |
118 | }; |
119 | ||
7a04092c SH |
120 | static struct clk_div_table clk_enet_ref_table[] = { |
121 | { .val = 0, .div = 20, }, | |
122 | { .val = 1, .div = 10, }, | |
123 | { .val = 2, .div = 5, }, | |
124 | { .val = 3, .div = 4, }, | |
ec9de6cd | 125 | { /* sentinel */ } |
7a04092c SH |
126 | }; |
127 | ||
2df1d026 PZ |
128 | static struct clk_div_table post_div_table[] = { |
129 | { .val = 2, .div = 1, }, | |
130 | { .val = 1, .div = 2, }, | |
131 | { .val = 0, .div = 4, }, | |
ec9de6cd | 132 | { /* sentinel */ } |
2df1d026 PZ |
133 | }; |
134 | ||
135 | static struct clk_div_table video_div_table[] = { | |
136 | { .val = 0, .div = 1, }, | |
137 | { .val = 1, .div = 2, }, | |
138 | { .val = 2, .div = 1, }, | |
139 | { .val = 3, .div = 4, }, | |
ec9de6cd | 140 | { /* sentinel */ } |
2df1d026 PZ |
141 | }; |
142 | ||
886cda41 SG |
143 | static unsigned int share_count_esai; |
144 | ||
53bb71da | 145 | static void __init imx6q_clocks_init(struct device_node *ccm_node) |
2acd1b6f SG |
146 | { |
147 | struct device_node *np; | |
148 | void __iomem *base; | |
876292d6 | 149 | int i; |
a94f8ecb | 150 | int ret; |
2acd1b6f | 151 | |
12aad63c SG |
152 | clk[dummy] = imx_clk_fixed("dummy", 0); |
153 | clk[ckil] = imx_obtain_fixed_clock("ckil", 0); | |
154 | clk[ckih] = imx_obtain_fixed_clock("ckih1", 0); | |
155 | clk[osc] = imx_obtain_fixed_clock("osc", 0); | |
2acd1b6f SG |
156 | |
157 | np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); | |
158 | base = of_iomap(np, 0); | |
159 | WARN_ON(!base); | |
160 | ||
2df1d026 | 161 | /* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */ |
3f75978b | 162 | if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) { |
2df1d026 PZ |
163 | post_div_table[1].div = 1; |
164 | post_div_table[2].div = 1; | |
165 | video_div_table[1].div = 1; | |
166 | video_div_table[2].div = 1; | |
167 | }; | |
168 | ||
2b254693 SH |
169 | /* type name parent_name base div_mask */ |
170 | clk[pll1_sys] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f); | |
171 | clk[pll2_bus] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1); | |
172 | clk[pll3_usb_otg] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3); | |
173 | clk[pll4_audio] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f); | |
174 | clk[pll5_video] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f); | |
175 | clk[pll6_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3); | |
176 | clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3); | |
2acd1b6f | 177 | |
a5120e89 PC |
178 | /* |
179 | * Bit 20 is the reserved and read-only bit, we do this only for: | |
180 | * - Do nothing for usbphy clk_enable/disable | |
181 | * - Keep refcount when do usbphy clk_enable/disable, in that case, | |
182 | * the clk framework may need to enable/disable usbphy's parent | |
183 | */ | |
184 | clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20); | |
185 | clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20); | |
186 | ||
187 | /* | |
188 | * usbphy*_gate needs to be on after system boots up, and software | |
189 | * never needs to control it anymore. | |
190 | */ | |
191 | clk[usbphy1_gate] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6); | |
192 | clk[usbphy2_gate] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6); | |
7571d283 | 193 | |
7a04092c SH |
194 | clk[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5); |
195 | clk[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4); | |
196 | ||
197 | clk[sata_ref_100m] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20); | |
198 | clk[pcie_ref_125m] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19); | |
199 | ||
200 | clk[enet_ref] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, | |
201 | base + 0xe0, 0, 2, 0, clk_enet_ref_table, | |
202 | &imx_ccm_lock); | |
203 | ||
bf221721 SC |
204 | clk[lvds1_sel] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); |
205 | clk[lvds2_sel] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); | |
206 | ||
207 | /* | |
208 | * lvds1_gate and lvds2_gate are pseudo-gates. Both can be | |
209 | * independently configured as clock inputs or outputs. We treat | |
210 | * the "output_enable" bit as a gate, even though it's really just | |
211 | * enabling clock output. | |
212 | */ | |
c2bece3c LS |
213 | clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "lvds1_sel", base + 0x160, 10); |
214 | clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "lvds2_sel", base + 0x160, 11); | |
bf221721 | 215 | |
2acd1b6f SG |
216 | /* name parent_name reg idx */ |
217 | clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); | |
218 | clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); | |
219 | clk[pll2_pfd2_396m] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2); | |
220 | clk[pll3_pfd0_720m] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0); | |
221 | clk[pll3_pfd1_540m] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1); | |
222 | clk[pll3_pfd2_508m] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2); | |
223 | clk[pll3_pfd3_454m] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3); | |
224 | ||
225 | /* name parent_name mult div */ | |
226 | clk[pll2_198m] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2); | |
227 | clk[pll3_120m] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4); | |
228 | clk[pll3_80m] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); | |
229 | clk[pll3_60m] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); | |
230 | clk[twd] = imx_clk_fixed_factor("twd", "arm", 1, 2); | |
231 | ||
2df1d026 | 232 | clk[pll4_post_div] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); |
64990a43 | 233 | clk[pll4_audio_div] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock); |
2df1d026 PZ |
234 | clk[pll5_post_div] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); |
235 | clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); | |
236 | ||
53bb71da | 237 | np = ccm_node; |
2acd1b6f SG |
238 | base = of_iomap(np, 0); |
239 | WARN_ON(!base); | |
9e8147bb SG |
240 | |
241 | imx6q_pm_set_ccm_base(base); | |
2acd1b6f SG |
242 | |
243 | /* name reg shift width parent_names num_parents */ | |
244 | clk[step] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); | |
245 | clk[pll1_sw] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); | |
246 | clk[periph_pre] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); | |
247 | clk[periph2_pre] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); | |
72cd7447 PZ |
248 | clk[periph_clk2_sel] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); |
249 | clk[periph2_clk2_sel] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); | |
2acd1b6f SG |
250 | clk[axi_sel] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels)); |
251 | clk[esai_sel] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); | |
252 | clk[asrc_sel] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); | |
253 | clk[spdif_sel] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels)); | |
254 | clk[gpu2d_axi] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); | |
255 | clk[gpu3d_axi] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); | |
256 | clk[gpu2d_core_sel] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels)); | |
257 | clk[gpu3d_core_sel] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels)); | |
258 | clk[gpu3d_shader_sel] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels)); | |
259 | clk[ipu1_sel] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); | |
260 | clk[ipu2_sel] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); | |
d19dacb7 PZ |
261 | clk[ldb_di0_sel] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); |
262 | clk[ldb_di1_sel] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); | |
4591b132 PZ |
263 | clk[ipu1_di0_pre_sel] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); |
264 | clk[ipu1_di1_pre_sel] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); | |
265 | clk[ipu2_di0_pre_sel] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); | |
266 | clk[ipu2_di1_pre_sel] = imx_clk_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); | |
267 | clk[ipu1_di0_sel] = imx_clk_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT); | |
268 | clk[ipu1_di1_sel] = imx_clk_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT); | |
269 | clk[ipu2_di0_sel] = imx_clk_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT); | |
270 | clk[ipu2_di1_sel] = imx_clk_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT); | |
2acd1b6f SG |
271 | clk[hsi_tx_sel] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels)); |
272 | clk[pcie_axi_sel] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels)); | |
dfd87144 LY |
273 | clk[ssi1_sel] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); |
274 | clk[ssi2_sel] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); | |
275 | clk[ssi3_sel] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); | |
276 | clk[usdhc1_sel] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); | |
277 | clk[usdhc2_sel] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); | |
278 | clk[usdhc3_sel] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); | |
279 | clk[usdhc4_sel] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); | |
2acd1b6f | 280 | clk[enfc_sel] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels)); |
dfd87144 LY |
281 | clk[emi_sel] = imx_clk_fixup_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels), imx_cscmr1_fixup); |
282 | clk[emi_slow_sel] = imx_clk_fixup_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels, ARRAY_SIZE(emi_slow_sels), imx_cscmr1_fixup); | |
2acd1b6f SG |
283 | clk[vdo_axi_sel] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels)); |
284 | clk[vpu_axi_sel] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels)); | |
285 | clk[cko1_sel] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels)); | |
6526bb3c | 286 | clk[cko2_sel] = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels)); |
6cd62235 | 287 | clk[cko] = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels)); |
2acd1b6f SG |
288 | |
289 | /* name reg shift width busy: reg, shift parent_names num_parents */ | |
290 | clk[periph] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels)); | |
291 | clk[periph2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels)); | |
292 | ||
293 | /* name parent_name reg shift width */ | |
294 | clk[periph_clk2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3); | |
295 | clk[periph2_clk2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3); | |
296 | clk[ipg] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2); | |
dfd87144 | 297 | clk[ipg_per] = imx_clk_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup); |
2acd1b6f SG |
298 | clk[esai_pred] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3); |
299 | clk[esai_podf] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3); | |
300 | clk[asrc_pred] = imx_clk_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3); | |
301 | clk[asrc_podf] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3); | |
302 | clk[spdif_pred] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3); | |
303 | clk[spdif_podf] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3); | |
9b3d4237 | 304 | clk[can_root] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6); |
2acd1b6f SG |
305 | clk[ecspi_root] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6); |
306 | clk[gpu2d_core_podf] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3); | |
307 | clk[gpu3d_core_podf] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3); | |
308 | clk[gpu3d_shader] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3); | |
309 | clk[ipu1_podf] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3); | |
310 | clk[ipu2_podf] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3); | |
16339464 | 311 | clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); |
d19dacb7 | 312 | clk[ldb_di0_podf] = imx_clk_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0); |
16339464 | 313 | clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); |
d19dacb7 | 314 | clk[ldb_di1_podf] = imx_clk_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0); |
2acd1b6f SG |
315 | clk[ipu1_di0_pre] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3); |
316 | clk[ipu1_di1_pre] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3); | |
317 | clk[ipu2_di0_pre] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3); | |
318 | clk[ipu2_di1_pre] = imx_clk_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", base + 0x38, 12, 3); | |
319 | clk[hsi_tx_podf] = imx_clk_divider("hsi_tx_podf", "hsi_tx_sel", base + 0x30, 29, 3); | |
320 | clk[ssi1_pred] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3); | |
321 | clk[ssi1_podf] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6); | |
322 | clk[ssi2_pred] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3); | |
323 | clk[ssi2_podf] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6); | |
324 | clk[ssi3_pred] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3); | |
325 | clk[ssi3_podf] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6); | |
326 | clk[uart_serial_podf] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6); | |
327 | clk[usdhc1_podf] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3); | |
328 | clk[usdhc2_podf] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3); | |
329 | clk[usdhc3_podf] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3); | |
330 | clk[usdhc4_podf] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); | |
331 | clk[enfc_pred] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3); | |
332 | clk[enfc_podf] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6); | |
dfd87144 LY |
333 | clk[emi_podf] = imx_clk_fixup_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup); |
334 | clk[emi_slow_podf] = imx_clk_fixup_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup); | |
2acd1b6f SG |
335 | clk[vpu_axi_podf] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3); |
336 | clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3); | |
6526bb3c | 337 | clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3); |
2acd1b6f SG |
338 | |
339 | /* name parent_name reg shift width busy: reg, shift */ | |
340 | clk[axi] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0); | |
341 | clk[mmdc_ch0_axi_podf] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4); | |
342 | clk[mmdc_ch1_axi_podf] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2); | |
343 | clk[arm] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16); | |
344 | clk[ahb] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); | |
345 | ||
346 | /* name parent_name reg shift */ | |
10a81378 | 347 | clk[apbh_dma] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4); |
2acd1b6f SG |
348 | clk[asrc] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6); |
349 | clk[can1_ipg] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14); | |
350 | clk[can1_serial] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16); | |
351 | clk[can2_ipg] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18); | |
352 | clk[can2_serial] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20); | |
353 | clk[ecspi1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0); | |
354 | clk[ecspi2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2); | |
355 | clk[ecspi3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4); | |
356 | clk[ecspi4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6); | |
ee3387f9 IP |
357 | if (cpu_is_imx6dl()) |
358 | /* ecspi5 is replaced with i2c4 on imx6dl & imx6s */ | |
359 | clk[ecspi5] = imx_clk_gate2("i2c4", "ipg_per", base + 0x6c, 8); | |
360 | else | |
361 | clk[ecspi5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8); | |
2acd1b6f | 362 | clk[enet] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10); |
886cda41 SG |
363 | clk[esai] = imx_clk_gate2_shared("esai", "esai_podf", base + 0x6c, 16, &share_count_esai); |
364 | clk[esai_ahb] = imx_clk_gate2_shared("esai_ahb", "ahb", base + 0x6c, 16, &share_count_esai); | |
2acd1b6f SG |
365 | clk[gpt_ipg] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20); |
366 | clk[gpt_ipg_per] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22); | |
2e603ad9 DB |
367 | if (cpu_is_imx6dl()) |
368 | /* | |
369 | * The multiplexer and divider of imx6q clock gpu3d_shader get | |
370 | * redefined/reused as gpu2d_core_sel and gpu2d_core_podf on imx6dl. | |
371 | */ | |
372 | clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu3d_shader", base + 0x6c, 24); | |
373 | else | |
374 | clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24); | |
2acd1b6f SG |
375 | clk[gpu3d_core] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26); |
376 | clk[hdmi_iahb] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0); | |
377 | clk[hdmi_isfr] = imx_clk_gate2("hdmi_isfr", "pll3_pfd1_540m", base + 0x70, 4); | |
378 | clk[i2c1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6); | |
379 | clk[i2c2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8); | |
380 | clk[i2c3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10); | |
381 | clk[iim] = imx_clk_gate2("iim", "ipg", base + 0x70, 12); | |
382 | clk[enfc] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14); | |
97245139 | 383 | clk[vdoa] = imx_clk_gate2("vdoa", "vdo_axi", base + 0x70, 26); |
2acd1b6f SG |
384 | clk[ipu1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0); |
385 | clk[ipu1_di0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2); | |
386 | clk[ipu1_di1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4); | |
387 | clk[ipu2] = imx_clk_gate2("ipu2", "ipu2_podf", base + 0x74, 6); | |
388 | clk[ipu2_di0] = imx_clk_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8); | |
389 | clk[ldb_di0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12); | |
390 | clk[ldb_di1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14); | |
391 | clk[ipu2_di1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10); | |
392 | clk[hsi_tx] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16); | |
fbcb4412 DB |
393 | if (cpu_is_imx6dl()) |
394 | /* | |
395 | * The multiplexer and divider of the imx6q clock gpu2d get | |
396 | * redefined/reused as mlb_sys_sel and mlb_sys_clk_podf on imx6dl. | |
397 | */ | |
398 | clk[mlb] = imx_clk_gate2("mlb", "gpu2d_core_podf", base + 0x74, 18); | |
399 | else | |
400 | clk[mlb] = imx_clk_gate2("mlb", "axi", base + 0x74, 18); | |
2acd1b6f SG |
401 | clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20); |
402 | clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22); | |
403 | clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28); | |
404 | clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30); | |
405 | clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0); | |
77ac32ad | 406 | clk[per1_bch] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12); |
2acd1b6f SG |
407 | clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16); |
408 | clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18); | |
409 | clk[pwm3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20); | |
410 | clk[pwm4] = imx_clk_gate2("pwm4", "ipg_per", base + 0x78, 22); | |
411 | clk[gpmi_bch_apb] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24); | |
412 | clk[gpmi_bch] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26); | |
413 | clk[gpmi_io] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28); | |
414 | clk[gpmi_apb] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30); | |
5ae95aef | 415 | clk[rom] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0); |
2acd1b6f SG |
416 | clk[sata] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4); |
417 | clk[sdma] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); | |
418 | clk[spba] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); | |
1fa5007b | 419 | clk[spdif] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14); |
0987b598 RZ |
420 | clk[ssi1_ipg] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18); |
421 | clk[ssi2_ipg] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20); | |
422 | clk[ssi3_ipg] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22); | |
2acd1b6f SG |
423 | clk[uart_ipg] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24); |
424 | clk[uart_serial] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26); | |
425 | clk[usboh3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); | |
426 | clk[usdhc1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2); | |
427 | clk[usdhc2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); | |
428 | clk[usdhc3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); | |
429 | clk[usdhc4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); | |
9545b2ed | 430 | clk[eim_slow] = imx_clk_gate2("eim_slow", "emi_slow_podf", base + 0x80, 10); |
2acd1b6f SG |
431 | clk[vdo_axi] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12); |
432 | clk[vpu_axi] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14); | |
433 | clk[cko1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7); | |
6526bb3c | 434 | clk[cko2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24); |
2acd1b6f SG |
435 | |
436 | for (i = 0; i < ARRAY_SIZE(clk); i++) | |
437 | if (IS_ERR(clk[i])) | |
438 | pr_err("i.MX6q clk %d: register failed with %ld\n", | |
439 | i, PTR_ERR(clk[i])); | |
440 | ||
0e87e043 SG |
441 | clk_data.clks = clk; |
442 | clk_data.clk_num = ARRAY_SIZE(clk); | |
443 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | |
444 | ||
2acd1b6f SG |
445 | clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0"); |
446 | clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0"); | |
810c0ca8 | 447 | clk_register_clkdev(clk[enet_ref], "enet_ref", NULL); |
2acd1b6f | 448 | |
3f75978b SG |
449 | if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) || |
450 | cpu_is_imx6dl()) { | |
32f3b8da PZ |
451 | clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]); |
452 | clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]); | |
453 | } | |
454 | ||
17b9b3b9 SH |
455 | clk_set_parent(clk[ipu1_di0_pre_sel], clk[pll5_video_div]); |
456 | clk_set_parent(clk[ipu1_di1_pre_sel], clk[pll5_video_div]); | |
457 | clk_set_parent(clk[ipu2_di0_pre_sel], clk[pll5_video_div]); | |
458 | clk_set_parent(clk[ipu2_di1_pre_sel], clk[pll5_video_div]); | |
459 | clk_set_parent(clk[ipu1_di0_sel], clk[ipu1_di0_pre]); | |
460 | clk_set_parent(clk[ipu1_di1_sel], clk[ipu1_di1_pre]); | |
461 | clk_set_parent(clk[ipu2_di0_sel], clk[ipu2_di0_pre]); | |
462 | clk_set_parent(clk[ipu2_di1_sel], clk[ipu2_di1_pre]); | |
463 | ||
cc7887c3 HS |
464 | /* |
465 | * The gpmi needs 100MHz frequency in the EDO/Sync mode, | |
466 | * We can not get the 100MHz from the pll2_pfd0_352m. | |
467 | * So choose pll2_pfd2_396m as enfc_sel's parent. | |
468 | */ | |
469 | clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]); | |
470 | ||
b0286f20 RZ |
471 | for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) |
472 | clk_prepare_enable(clk[clks_init_on[i]]); | |
2acd1b6f | 473 | |
a5120e89 PC |
474 | if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { |
475 | clk_prepare_enable(clk[usbphy1_gate]); | |
476 | clk_prepare_enable(clk[usbphy2_gate]); | |
477 | } | |
478 | ||
a94f8ecb SG |
479 | /* |
480 | * Let's initially set up CLKO with OSC24M, since this configuration | |
481 | * is widely used by imx6q board designs to clock audio codec. | |
482 | */ | |
483 | ret = clk_set_parent(clk[cko2_sel], clk[osc]); | |
484 | if (!ret) | |
485 | ret = clk_set_parent(clk[cko], clk[cko2]); | |
486 | if (ret) | |
487 | pr_warn("failed to set up CLKO: %d\n", ret); | |
488 | ||
4390e622 NC |
489 | /* Audio-related clocks configuration */ |
490 | clk_set_parent(clk[spdif_sel], clk[pll3_pfd3_454m]); | |
491 | ||
74b80313 SC |
492 | /* All existing boards with PCIe use LVDS1 */ |
493 | if (IS_ENABLED(CONFIG_PCI_IMX6)) | |
03e97220 | 494 | clk_set_parent(clk[lvds1_sel], clk[sata_ref_100m]); |
74b80313 | 495 | |
e7c57ecd PZ |
496 | /* Set initial power mode */ |
497 | imx6q_set_lpm(WAIT_CLOCKED); | |
498 | ||
876292d6 | 499 | mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt")); |
2acd1b6f | 500 | } |
53bb71da | 501 | CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init); |