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1f2c5fd5 JL |
1 | /* |
2 | * Copyright 2012-2013 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | */ | |
10 | ||
11 | #include <linux/of_address.h> | |
12 | #include <linux/clk.h> | |
13 | #include <dt-bindings/clock/vf610-clock.h> | |
14 | ||
15 | #include "clk.h" | |
16 | ||
17 | #define CCM_CCR (ccm_base + 0x00) | |
18 | #define CCM_CSR (ccm_base + 0x04) | |
19 | #define CCM_CCSR (ccm_base + 0x08) | |
20 | #define CCM_CACRR (ccm_base + 0x0c) | |
21 | #define CCM_CSCMR1 (ccm_base + 0x10) | |
22 | #define CCM_CSCDR1 (ccm_base + 0x14) | |
23 | #define CCM_CSCDR2 (ccm_base + 0x18) | |
24 | #define CCM_CSCDR3 (ccm_base + 0x1c) | |
25 | #define CCM_CSCMR2 (ccm_base + 0x20) | |
26 | #define CCM_CSCDR4 (ccm_base + 0x24) | |
27 | #define CCM_CLPCR (ccm_base + 0x2c) | |
28 | #define CCM_CISR (ccm_base + 0x30) | |
29 | #define CCM_CIMR (ccm_base + 0x34) | |
30 | #define CCM_CGPR (ccm_base + 0x3c) | |
31 | #define CCM_CCGR0 (ccm_base + 0x40) | |
32 | #define CCM_CCGR1 (ccm_base + 0x44) | |
33 | #define CCM_CCGR2 (ccm_base + 0x48) | |
34 | #define CCM_CCGR3 (ccm_base + 0x4c) | |
35 | #define CCM_CCGR4 (ccm_base + 0x50) | |
36 | #define CCM_CCGR5 (ccm_base + 0x54) | |
37 | #define CCM_CCGR6 (ccm_base + 0x58) | |
38 | #define CCM_CCGR7 (ccm_base + 0x5c) | |
39 | #define CCM_CCGR8 (ccm_base + 0x60) | |
40 | #define CCM_CCGR9 (ccm_base + 0x64) | |
41 | #define CCM_CCGR10 (ccm_base + 0x68) | |
42 | #define CCM_CCGR11 (ccm_base + 0x6c) | |
43 | #define CCM_CMEOR0 (ccm_base + 0x70) | |
44 | #define CCM_CMEOR1 (ccm_base + 0x74) | |
45 | #define CCM_CMEOR2 (ccm_base + 0x78) | |
46 | #define CCM_CMEOR3 (ccm_base + 0x7c) | |
47 | #define CCM_CMEOR4 (ccm_base + 0x80) | |
48 | #define CCM_CMEOR5 (ccm_base + 0x84) | |
49 | #define CCM_CPPDSR (ccm_base + 0x88) | |
50 | #define CCM_CCOWR (ccm_base + 0x8c) | |
51 | #define CCM_CCPGR0 (ccm_base + 0x90) | |
52 | #define CCM_CCPGR1 (ccm_base + 0x94) | |
53 | #define CCM_CCPGR2 (ccm_base + 0x98) | |
54 | #define CCM_CCPGR3 (ccm_base + 0x9c) | |
55 | ||
56 | #define CCM_CCGRx_CGn(n) ((n) * 2) | |
57 | ||
58 | #define PFD_PLL1_BASE (anatop_base + 0x2b0) | |
59 | #define PFD_PLL2_BASE (anatop_base + 0x100) | |
60 | #define PFD_PLL3_BASE (anatop_base + 0xf0) | |
c72c5532 SA |
61 | #define PLL1_CTRL (anatop_base + 0x270) |
62 | #define PLL2_CTRL (anatop_base + 0x30) | |
21231f81 | 63 | #define PLL3_CTRL (anatop_base + 0x10) |
c72c5532 SA |
64 | #define PLL4_CTRL (anatop_base + 0x70) |
65 | #define PLL5_CTRL (anatop_base + 0xe0) | |
66 | #define PLL6_CTRL (anatop_base + 0xa0) | |
21231f81 | 67 | #define PLL7_CTRL (anatop_base + 0x20) |
c72c5532 | 68 | #define ANA_MISC1 (anatop_base + 0x160) |
1f2c5fd5 JL |
69 | |
70 | static void __iomem *anatop_base; | |
71 | static void __iomem *ccm_base; | |
72 | ||
73 | /* sources for multiplexer clocks, this is used multiple times */ | |
b78f1e80 LY |
74 | static const char *fast_sels[] = { "firc", "fxosc", }; |
75 | static const char *slow_sels[] = { "sirc_32k", "sxosc", }; | |
c72c5532 SA |
76 | static const char *pll1_sels[] = { "pll1_sys", "pll1_pfd1", "pll1_pfd2", "pll1_pfd3", "pll1_pfd4", }; |
77 | static const char *pll2_sels[] = { "pll2_bus", "pll2_pfd1", "pll2_pfd2", "pll2_pfd3", "pll2_pfd4", }; | |
78 | static const char *pll_bypass_src_sels[] = { "fast_clk_sel", "lvds1_in", }; | |
79 | static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", }; | |
80 | static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", }; | |
81 | static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", }; | |
82 | static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", }; | |
83 | static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", }; | |
84 | static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", }; | |
85 | static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", }; | |
86 | static const char *sys_sels[] = { "fast_clk_sel", "slow_clk_sel", "pll2_pfd_sel", "pll2_bus", "pll1_pfd_sel", "pll3_usb_otg", }; | |
b78f1e80 LY |
87 | static const char *ddr_sels[] = { "pll2_pfd2", "sys_sel", }; |
88 | static const char *rmii_sels[] = { "enet_ext", "audio_ext", "enet_50m", "enet_25m", }; | |
89 | static const char *enet_ts_sels[] = { "enet_ext", "fxosc", "audio_ext", "usb", "enet_ts", "enet_25m", "enet_50m", }; | |
c72c5532 SA |
90 | static const char *esai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_audio_div", }; |
91 | static const char *sai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_audio_div", }; | |
b78f1e80 | 92 | static const char *nfc_sels[] = { "platform_bus", "pll1_pfd1", "pll3_pfd1", "pll3_pfd3", }; |
c72c5532 SA |
93 | static const char *qspi_sels[] = { "pll3_usb_otg", "pll3_pfd4", "pll2_pfd4", "pll1_pfd4", }; |
94 | static const char *esdhc_sels[] = { "pll3_usb_otg", "pll3_pfd3", "pll1_pfd3", "platform_bus", }; | |
95 | static const char *dcu_sels[] = { "pll1_pfd2", "pll3_usb_otg", }; | |
b78f1e80 | 96 | static const char *gpu_sels[] = { "pll2_pfd2", "pll3_pfd2", }; |
c72c5532 | 97 | static const char *vadc_sels[] = { "pll6_video_div", "pll3_usb_otg_div", "pll3_usb_otg", }; |
1f2c5fd5 | 98 | /* FTM counter clock source, not module clock */ |
b78f1e80 LY |
99 | static const char *ftm_ext_sels[] = {"sirc_128k", "sxosc", "fxosc_half", "audio_ext", }; |
100 | static const char *ftm_fix_sels[] = { "sxosc", "ipg_bus", }; | |
1f2c5fd5 | 101 | |
c72c5532 SA |
102 | |
103 | static struct clk_div_table pll4_audio_div_table[] = { | |
1f2c5fd5 JL |
104 | { .val = 0, .div = 1 }, |
105 | { .val = 1, .div = 2 }, | |
106 | { .val = 2, .div = 6 }, | |
107 | { .val = 3, .div = 8 }, | |
108 | { .val = 4, .div = 10 }, | |
109 | { .val = 5, .div = 12 }, | |
110 | { .val = 6, .div = 14 }, | |
111 | { .val = 7, .div = 16 }, | |
112 | { } | |
113 | }; | |
114 | ||
115 | static struct clk *clk[VF610_CLK_END]; | |
116 | static struct clk_onecell_data clk_data; | |
117 | ||
3b18dd7a SA |
118 | static unsigned int const clks_init_on[] __initconst = { |
119 | VF610_CLK_SYS_BUS, | |
120 | VF610_CLK_DDR_SEL, | |
121 | }; | |
122 | ||
a41820d6 SA |
123 | static struct clk * __init vf610_get_fixed_clock( |
124 | struct device_node *ccm_node, const char *name) | |
125 | { | |
126 | struct clk *clk = of_clk_get_by_name(ccm_node, name); | |
127 | ||
128 | /* Backward compatibility if device tree is missing clks assignments */ | |
129 | if (IS_ERR(clk)) | |
130 | clk = imx_obtain_fixed_clock(name, 0); | |
131 | return clk; | |
132 | }; | |
133 | ||
1f2c5fd5 JL |
134 | static void __init vf610_clocks_init(struct device_node *ccm_node) |
135 | { | |
136 | struct device_node *np; | |
3b18dd7a | 137 | int i; |
1f2c5fd5 JL |
138 | |
139 | clk[VF610_CLK_DUMMY] = imx_clk_fixed("dummy", 0); | |
140 | clk[VF610_CLK_SIRC_128K] = imx_clk_fixed("sirc_128k", 128000); | |
141 | clk[VF610_CLK_SIRC_32K] = imx_clk_fixed("sirc_32k", 32000); | |
142 | clk[VF610_CLK_FIRC] = imx_clk_fixed("firc", 24000000); | |
143 | ||
a41820d6 SA |
144 | clk[VF610_CLK_SXOSC] = vf610_get_fixed_clock(ccm_node, "sxosc"); |
145 | clk[VF610_CLK_FXOSC] = vf610_get_fixed_clock(ccm_node, "fxosc"); | |
146 | clk[VF610_CLK_AUDIO_EXT] = vf610_get_fixed_clock(ccm_node, "audio_ext"); | |
147 | clk[VF610_CLK_ENET_EXT] = vf610_get_fixed_clock(ccm_node, "enet_ext"); | |
1f2c5fd5 | 148 | |
c72c5532 | 149 | /* Clock source from external clock via LVDs PAD */ |
a41820d6 | 150 | clk[VF610_CLK_ANACLK1] = vf610_get_fixed_clock(ccm_node, "anaclk1"); |
c72c5532 | 151 | |
1f2c5fd5 JL |
152 | clk[VF610_CLK_FXOSC_HALF] = imx_clk_fixed_factor("fxosc_half", "fxosc", 1, 2); |
153 | ||
154 | np = of_find_compatible_node(NULL, NULL, "fsl,vf610-anatop"); | |
155 | anatop_base = of_iomap(np, 0); | |
156 | BUG_ON(!anatop_base); | |
157 | ||
158 | np = ccm_node; | |
159 | ccm_base = of_iomap(np, 0); | |
160 | BUG_ON(!ccm_base); | |
161 | ||
162 | clk[VF610_CLK_SLOW_CLK_SEL] = imx_clk_mux("slow_clk_sel", CCM_CCSR, 4, 1, slow_sels, ARRAY_SIZE(slow_sels)); | |
163 | clk[VF610_CLK_FASK_CLK_SEL] = imx_clk_mux("fast_clk_sel", CCM_CCSR, 5, 1, fast_sels, ARRAY_SIZE(fast_sels)); | |
164 | ||
c72c5532 SA |
165 | clk[VF610_CLK_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", PLL1_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); |
166 | clk[VF610_CLK_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", PLL2_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); | |
167 | clk[VF610_CLK_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", PLL3_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); | |
168 | clk[VF610_CLK_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", PLL4_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); | |
169 | clk[VF610_CLK_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", PLL5_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); | |
170 | clk[VF610_CLK_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", PLL6_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); | |
171 | clk[VF610_CLK_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", PLL7_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); | |
172 | ||
173 | clk[VF610_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll1", "pll1_bypass_src", PLL1_CTRL, 0x1); | |
174 | clk[VF610_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", PLL2_CTRL, 0x1); | |
60ad8467 | 175 | clk[VF610_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB_VF610, "pll3", "pll3_bypass_src", PLL3_CTRL, 0x2); |
c72c5532 SA |
176 | clk[VF610_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", PLL4_CTRL, 0x7f); |
177 | clk[VF610_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll5", "pll5_bypass_src", PLL5_CTRL, 0x3); | |
178 | clk[VF610_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_AV, "pll6", "pll6_bypass_src", PLL6_CTRL, 0x7f); | |
60ad8467 | 179 | clk[VF610_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB_VF610, "pll7", "pll7_bypass_src", PLL7_CTRL, 0x2); |
c72c5532 SA |
180 | |
181 | clk[VF610_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", PLL1_CTRL, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); | |
182 | clk[VF610_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", PLL2_CTRL, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); | |
183 | clk[VF610_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", PLL3_CTRL, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); | |
184 | clk[VF610_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", PLL4_CTRL, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT); | |
185 | clk[VF610_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", PLL5_CTRL, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); | |
186 | clk[VF610_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", PLL6_CTRL, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT); | |
187 | clk[VF610_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", PLL7_CTRL, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); | |
188 | ||
189 | /* Do not bypass PLLs initially */ | |
190 | clk_set_parent(clk[VF610_PLL1_BYPASS], clk[VF610_CLK_PLL1]); | |
191 | clk_set_parent(clk[VF610_PLL2_BYPASS], clk[VF610_CLK_PLL2]); | |
192 | clk_set_parent(clk[VF610_PLL3_BYPASS], clk[VF610_CLK_PLL3]); | |
193 | clk_set_parent(clk[VF610_PLL4_BYPASS], clk[VF610_CLK_PLL4]); | |
194 | clk_set_parent(clk[VF610_PLL5_BYPASS], clk[VF610_CLK_PLL5]); | |
195 | clk_set_parent(clk[VF610_PLL6_BYPASS], clk[VF610_CLK_PLL6]); | |
196 | clk_set_parent(clk[VF610_PLL7_BYPASS], clk[VF610_CLK_PLL7]); | |
197 | ||
198 | clk[VF610_CLK_PLL1_SYS] = imx_clk_gate("pll1_sys", "pll1_bypass", PLL1_CTRL, 13); | |
199 | clk[VF610_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", PLL2_CTRL, 13); | |
200 | clk[VF610_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", PLL3_CTRL, 13); | |
201 | clk[VF610_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", PLL4_CTRL, 13); | |
202 | clk[VF610_CLK_PLL5_ENET] = imx_clk_gate("pll5_enet", "pll5_bypass", PLL5_CTRL, 13); | |
203 | clk[VF610_CLK_PLL6_VIDEO] = imx_clk_gate("pll6_video", "pll6_bypass", PLL6_CTRL, 13); | |
204 | clk[VF610_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", PLL7_CTRL, 13); | |
205 | ||
206 | clk[VF610_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", ANA_MISC1, 12, BIT(10)); | |
207 | ||
208 | clk[VF610_CLK_PLL1_PFD1] = imx_clk_pfd("pll1_pfd1", "pll1_sys", PFD_PLL1_BASE, 0); | |
209 | clk[VF610_CLK_PLL1_PFD2] = imx_clk_pfd("pll1_pfd2", "pll1_sys", PFD_PLL1_BASE, 1); | |
210 | clk[VF610_CLK_PLL1_PFD3] = imx_clk_pfd("pll1_pfd3", "pll1_sys", PFD_PLL1_BASE, 2); | |
211 | clk[VF610_CLK_PLL1_PFD4] = imx_clk_pfd("pll1_pfd4", "pll1_sys", PFD_PLL1_BASE, 3); | |
212 | ||
213 | clk[VF610_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1", "pll2_bus", PFD_PLL2_BASE, 0); | |
214 | clk[VF610_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2", "pll2_bus", PFD_PLL2_BASE, 1); | |
215 | clk[VF610_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3", "pll2_bus", PFD_PLL2_BASE, 2); | |
216 | clk[VF610_CLK_PLL2_PFD4] = imx_clk_pfd("pll2_pfd4", "pll2_bus", PFD_PLL2_BASE, 3); | |
217 | ||
218 | clk[VF610_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1", "pll3_usb_otg", PFD_PLL3_BASE, 0); | |
219 | clk[VF610_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2", "pll3_usb_otg", PFD_PLL3_BASE, 1); | |
220 | clk[VF610_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_usb_otg", PFD_PLL3_BASE, 2); | |
221 | clk[VF610_CLK_PLL3_PFD4] = imx_clk_pfd("pll3_pfd4", "pll3_usb_otg", PFD_PLL3_BASE, 3); | |
21231f81 | 222 | |
1f2c5fd5 JL |
223 | clk[VF610_CLK_PLL1_PFD_SEL] = imx_clk_mux("pll1_pfd_sel", CCM_CCSR, 16, 3, pll1_sels, 5); |
224 | clk[VF610_CLK_PLL2_PFD_SEL] = imx_clk_mux("pll2_pfd_sel", CCM_CCSR, 19, 3, pll2_sels, 5); | |
225 | clk[VF610_CLK_SYS_SEL] = imx_clk_mux("sys_sel", CCM_CCSR, 0, 3, sys_sels, ARRAY_SIZE(sys_sels)); | |
226 | clk[VF610_CLK_DDR_SEL] = imx_clk_mux("ddr_sel", CCM_CCSR, 6, 1, ddr_sels, ARRAY_SIZE(ddr_sels)); | |
227 | clk[VF610_CLK_SYS_BUS] = imx_clk_divider("sys_bus", "sys_sel", CCM_CACRR, 0, 3); | |
228 | clk[VF610_CLK_PLATFORM_BUS] = imx_clk_divider("platform_bus", "sys_bus", CCM_CACRR, 3, 3); | |
229 | clk[VF610_CLK_IPG_BUS] = imx_clk_divider("ipg_bus", "platform_bus", CCM_CACRR, 11, 2); | |
230 | ||
c72c5532 SA |
231 | clk[VF610_CLK_PLL3_MAIN_DIV] = imx_clk_divider("pll3_usb_otg_div", "pll3_usb_otg", CCM_CACRR, 20, 1); |
232 | clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_audio_div", "pll4_audio", 0, CCM_CACRR, 6, 3, 0, pll4_audio_div_table, &imx_ccm_lock); | |
233 | clk[VF610_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_video_div", "pll6_video", CCM_CACRR, 21, 1); | |
1f2c5fd5 | 234 | |
c72c5532 SA |
235 | clk[VF610_CLK_USBPHY0] = imx_clk_gate("usbphy0", "pll3_usb_otg", PLL3_CTRL, 6); |
236 | clk[VF610_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll7_usb_host", PLL7_CTRL, 6); | |
21231f81 SA |
237 | |
238 | clk[VF610_CLK_USBC0] = imx_clk_gate2("usbc0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(4)); | |
239 | clk[VF610_CLK_USBC1] = imx_clk_gate2("usbc1", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(4)); | |
1f2c5fd5 JL |
240 | |
241 | clk[VF610_CLK_QSPI0_SEL] = imx_clk_mux("qspi0_sel", CCM_CSCMR1, 22, 2, qspi_sels, 4); | |
242 | clk[VF610_CLK_QSPI0_EN] = imx_clk_gate("qspi0_en", "qspi0_sel", CCM_CSCDR3, 4); | |
243 | clk[VF610_CLK_QSPI0_X4_DIV] = imx_clk_divider("qspi0_x4", "qspi0_en", CCM_CSCDR3, 0, 2); | |
244 | clk[VF610_CLK_QSPI0_X2_DIV] = imx_clk_divider("qspi0_x2", "qspi0_x4", CCM_CSCDR3, 2, 1); | |
245 | clk[VF610_CLK_QSPI0_X1_DIV] = imx_clk_divider("qspi0_x1", "qspi0_x2", CCM_CSCDR3, 3, 1); | |
246 | clk[VF610_CLK_QSPI0] = imx_clk_gate2("qspi0", "qspi0_x1", CCM_CCGR2, CCM_CCGRx_CGn(4)); | |
247 | ||
248 | clk[VF610_CLK_QSPI1_SEL] = imx_clk_mux("qspi1_sel", CCM_CSCMR1, 24, 2, qspi_sels, 4); | |
249 | clk[VF610_CLK_QSPI1_EN] = imx_clk_gate("qspi1_en", "qspi1_sel", CCM_CSCDR3, 12); | |
250 | clk[VF610_CLK_QSPI1_X4_DIV] = imx_clk_divider("qspi1_x4", "qspi1_en", CCM_CSCDR3, 8, 2); | |
251 | clk[VF610_CLK_QSPI1_X2_DIV] = imx_clk_divider("qspi1_x2", "qspi1_x4", CCM_CSCDR3, 10, 1); | |
252 | clk[VF610_CLK_QSPI1_X1_DIV] = imx_clk_divider("qspi1_x1", "qspi1_x2", CCM_CSCDR3, 11, 1); | |
253 | clk[VF610_CLK_QSPI1] = imx_clk_gate2("qspi1", "qspi1_x1", CCM_CCGR8, CCM_CCGRx_CGn(4)); | |
254 | ||
c72c5532 SA |
255 | clk[VF610_CLK_ENET_50M] = imx_clk_fixed_factor("enet_50m", "pll5_enet", 1, 10); |
256 | clk[VF610_CLK_ENET_25M] = imx_clk_fixed_factor("enet_25m", "pll5_enet", 1, 20); | |
1f2c5fd5 JL |
257 | clk[VF610_CLK_ENET_SEL] = imx_clk_mux("enet_sel", CCM_CSCMR2, 4, 2, rmii_sels, 4); |
258 | clk[VF610_CLK_ENET_TS_SEL] = imx_clk_mux("enet_ts_sel", CCM_CSCMR2, 0, 3, enet_ts_sels, 7); | |
259 | clk[VF610_CLK_ENET] = imx_clk_gate("enet", "enet_sel", CCM_CSCDR1, 24); | |
260 | clk[VF610_CLK_ENET_TS] = imx_clk_gate("enet_ts", "enet_ts_sel", CCM_CSCDR1, 23); | |
4f71612e SG |
261 | clk[VF610_CLK_ENET0] = imx_clk_gate2("enet0", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(0)); |
262 | clk[VF610_CLK_ENET1] = imx_clk_gate2("enet1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(1)); | |
1f2c5fd5 JL |
263 | |
264 | clk[VF610_CLK_PIT] = imx_clk_gate2("pit", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(7)); | |
265 | ||
266 | clk[VF610_CLK_UART0] = imx_clk_gate2("uart0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(7)); | |
267 | clk[VF610_CLK_UART1] = imx_clk_gate2("uart1", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(8)); | |
268 | clk[VF610_CLK_UART2] = imx_clk_gate2("uart2", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(9)); | |
269 | clk[VF610_CLK_UART3] = imx_clk_gate2("uart3", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(10)); | |
6f540db7 BD |
270 | clk[VF610_CLK_UART4] = imx_clk_gate2("uart4", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(9)); |
271 | clk[VF610_CLK_UART5] = imx_clk_gate2("uart5", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(10)); | |
1f2c5fd5 JL |
272 | |
273 | clk[VF610_CLK_I2C0] = imx_clk_gate2("i2c0", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(6)); | |
274 | clk[VF610_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(7)); | |
275 | ||
276 | clk[VF610_CLK_DSPI0] = imx_clk_gate2("dspi0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(12)); | |
277 | clk[VF610_CLK_DSPI1] = imx_clk_gate2("dspi1", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(13)); | |
278 | clk[VF610_CLK_DSPI2] = imx_clk_gate2("dspi2", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(12)); | |
279 | clk[VF610_CLK_DSPI3] = imx_clk_gate2("dspi3", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(13)); | |
280 | ||
281 | clk[VF610_CLK_WDT] = imx_clk_gate2("wdt", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(14)); | |
282 | ||
283 | clk[VF610_CLK_ESDHC0_SEL] = imx_clk_mux("esdhc0_sel", CCM_CSCMR1, 16, 2, esdhc_sels, 4); | |
284 | clk[VF610_CLK_ESDHC0_EN] = imx_clk_gate("esdhc0_en", "esdhc0_sel", CCM_CSCDR2, 28); | |
285 | clk[VF610_CLK_ESDHC0_DIV] = imx_clk_divider("esdhc0_div", "esdhc0_en", CCM_CSCDR2, 16, 4); | |
286 | clk[VF610_CLK_ESDHC0] = imx_clk_gate2("eshc0", "esdhc0_div", CCM_CCGR7, CCM_CCGRx_CGn(1)); | |
287 | ||
288 | clk[VF610_CLK_ESDHC1_SEL] = imx_clk_mux("esdhc1_sel", CCM_CSCMR1, 18, 2, esdhc_sels, 4); | |
289 | clk[VF610_CLK_ESDHC1_EN] = imx_clk_gate("esdhc1_en", "esdhc1_sel", CCM_CSCDR2, 29); | |
290 | clk[VF610_CLK_ESDHC1_DIV] = imx_clk_divider("esdhc1_div", "esdhc1_en", CCM_CSCDR2, 20, 4); | |
291 | clk[VF610_CLK_ESDHC1] = imx_clk_gate2("eshc1", "esdhc1_div", CCM_CCGR7, CCM_CCGRx_CGn(2)); | |
292 | ||
293 | /* | |
294 | * ftm_ext_clk and ftm_fix_clk are FTM timer counter's | |
295 | * selectable clock sources, both use a common enable bit | |
296 | * in CCM_CSCDR1, selecting "dummy" clock as parent of | |
297 | * "ftm0_ext_fix" make it serve only for enable/disable. | |
298 | */ | |
299 | clk[VF610_CLK_FTM0_EXT_SEL] = imx_clk_mux("ftm0_ext_sel", CCM_CSCMR2, 6, 2, ftm_ext_sels, 4); | |
300 | clk[VF610_CLK_FTM0_FIX_SEL] = imx_clk_mux("ftm0_fix_sel", CCM_CSCMR2, 14, 1, ftm_fix_sels, 2); | |
301 | clk[VF610_CLK_FTM0_EXT_FIX_EN] = imx_clk_gate("ftm0_ext_fix_en", "dummy", CCM_CSCDR1, 25); | |
302 | clk[VF610_CLK_FTM1_EXT_SEL] = imx_clk_mux("ftm1_ext_sel", CCM_CSCMR2, 8, 2, ftm_ext_sels, 4); | |
303 | clk[VF610_CLK_FTM1_FIX_SEL] = imx_clk_mux("ftm1_fix_sel", CCM_CSCMR2, 15, 1, ftm_fix_sels, 2); | |
304 | clk[VF610_CLK_FTM1_EXT_FIX_EN] = imx_clk_gate("ftm1_ext_fix_en", "dummy", CCM_CSCDR1, 26); | |
305 | clk[VF610_CLK_FTM2_EXT_SEL] = imx_clk_mux("ftm2_ext_sel", CCM_CSCMR2, 10, 2, ftm_ext_sels, 4); | |
306 | clk[VF610_CLK_FTM2_FIX_SEL] = imx_clk_mux("ftm2_fix_sel", CCM_CSCMR2, 16, 1, ftm_fix_sels, 2); | |
307 | clk[VF610_CLK_FTM2_EXT_FIX_EN] = imx_clk_gate("ftm2_ext_fix_en", "dummy", CCM_CSCDR1, 27); | |
308 | clk[VF610_CLK_FTM3_EXT_SEL] = imx_clk_mux("ftm3_ext_sel", CCM_CSCMR2, 12, 2, ftm_ext_sels, 4); | |
309 | clk[VF610_CLK_FTM3_FIX_SEL] = imx_clk_mux("ftm3_fix_sel", CCM_CSCMR2, 17, 1, ftm_fix_sels, 2); | |
310 | clk[VF610_CLK_FTM3_EXT_FIX_EN] = imx_clk_gate("ftm3_ext_fix_en", "dummy", CCM_CSCDR1, 28); | |
311 | ||
312 | /* ftm(n)_clk are FTM module operation clock */ | |
313 | clk[VF610_CLK_FTM0] = imx_clk_gate2("ftm0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(8)); | |
314 | clk[VF610_CLK_FTM1] = imx_clk_gate2("ftm1", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(9)); | |
315 | clk[VF610_CLK_FTM2] = imx_clk_gate2("ftm2", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(8)); | |
316 | clk[VF610_CLK_FTM3] = imx_clk_gate2("ftm3", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(9)); | |
317 | ||
318 | clk[VF610_CLK_DCU0_SEL] = imx_clk_mux("dcu0_sel", CCM_CSCMR1, 28, 1, dcu_sels, 2); | |
319 | clk[VF610_CLK_DCU0_EN] = imx_clk_gate("dcu0_en", "dcu0_sel", CCM_CSCDR3, 19); | |
320 | clk[VF610_CLK_DCU0_DIV] = imx_clk_divider("dcu0_div", "dcu0_en", CCM_CSCDR3, 16, 3); | |
321 | clk[VF610_CLK_DCU0] = imx_clk_gate2("dcu0", "dcu0_div", CCM_CCGR3, CCM_CCGRx_CGn(8)); | |
322 | clk[VF610_CLK_DCU1_SEL] = imx_clk_mux("dcu1_sel", CCM_CSCMR1, 29, 1, dcu_sels, 2); | |
323 | clk[VF610_CLK_DCU1_EN] = imx_clk_gate("dcu1_en", "dcu1_sel", CCM_CSCDR3, 23); | |
324 | clk[VF610_CLK_DCU1_DIV] = imx_clk_divider("dcu1_div", "dcu1_en", CCM_CSCDR3, 20, 3); | |
325 | clk[VF610_CLK_DCU1] = imx_clk_gate2("dcu1", "dcu1_div", CCM_CCGR9, CCM_CCGRx_CGn(8)); | |
326 | ||
327 | clk[VF610_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", CCM_CSCMR1, 20, 2, esai_sels, 4); | |
328 | clk[VF610_CLK_ESAI_EN] = imx_clk_gate("esai_en", "esai_sel", CCM_CSCDR2, 30); | |
329 | clk[VF610_CLK_ESAI_DIV] = imx_clk_divider("esai_div", "esai_en", CCM_CSCDR2, 24, 4); | |
330 | clk[VF610_CLK_ESAI] = imx_clk_gate2("esai", "esai_div", CCM_CCGR4, CCM_CCGRx_CGn(2)); | |
331 | ||
332 | clk[VF610_CLK_SAI0_SEL] = imx_clk_mux("sai0_sel", CCM_CSCMR1, 0, 2, sai_sels, 4); | |
333 | clk[VF610_CLK_SAI0_EN] = imx_clk_gate("sai0_en", "sai0_sel", CCM_CSCDR1, 16); | |
334 | clk[VF610_CLK_SAI0_DIV] = imx_clk_divider("sai0_div", "sai0_en", CCM_CSCDR1, 0, 4); | |
335 | clk[VF610_CLK_SAI0] = imx_clk_gate2("sai0", "sai0_div", CCM_CCGR0, CCM_CCGRx_CGn(15)); | |
336 | ||
337 | clk[VF610_CLK_SAI1_SEL] = imx_clk_mux("sai1_sel", CCM_CSCMR1, 2, 2, sai_sels, 4); | |
338 | clk[VF610_CLK_SAI1_EN] = imx_clk_gate("sai1_en", "sai1_sel", CCM_CSCDR1, 17); | |
339 | clk[VF610_CLK_SAI1_DIV] = imx_clk_divider("sai1_div", "sai1_en", CCM_CSCDR1, 4, 4); | |
340 | clk[VF610_CLK_SAI1] = imx_clk_gate2("sai1", "sai1_div", CCM_CCGR1, CCM_CCGRx_CGn(0)); | |
341 | ||
342 | clk[VF610_CLK_SAI2_SEL] = imx_clk_mux("sai2_sel", CCM_CSCMR1, 4, 2, sai_sels, 4); | |
343 | clk[VF610_CLK_SAI2_EN] = imx_clk_gate("sai2_en", "sai2_sel", CCM_CSCDR1, 18); | |
344 | clk[VF610_CLK_SAI2_DIV] = imx_clk_divider("sai2_div", "sai2_en", CCM_CSCDR1, 8, 4); | |
345 | clk[VF610_CLK_SAI2] = imx_clk_gate2("sai2", "sai2_div", CCM_CCGR1, CCM_CCGRx_CGn(1)); | |
346 | ||
347 | clk[VF610_CLK_SAI3_SEL] = imx_clk_mux("sai3_sel", CCM_CSCMR1, 6, 2, sai_sels, 4); | |
348 | clk[VF610_CLK_SAI3_EN] = imx_clk_gate("sai3_en", "sai3_sel", CCM_CSCDR1, 19); | |
349 | clk[VF610_CLK_SAI3_DIV] = imx_clk_divider("sai3_div", "sai3_en", CCM_CSCDR1, 12, 4); | |
350 | clk[VF610_CLK_SAI3] = imx_clk_gate2("sai3", "sai3_div", CCM_CCGR1, CCM_CCGRx_CGn(2)); | |
351 | ||
352 | clk[VF610_CLK_NFC_SEL] = imx_clk_mux("nfc_sel", CCM_CSCMR1, 12, 2, nfc_sels, 4); | |
353 | clk[VF610_CLK_NFC_EN] = imx_clk_gate("nfc_en", "nfc_sel", CCM_CSCDR2, 9); | |
354 | clk[VF610_CLK_NFC_PRE_DIV] = imx_clk_divider("nfc_pre_div", "nfc_en", CCM_CSCDR3, 13, 3); | |
355 | clk[VF610_CLK_NFC_FRAC_DIV] = imx_clk_divider("nfc_frac_div", "nfc_pre_div", CCM_CSCDR2, 4, 4); | |
356 | clk[VF610_CLK_NFC] = imx_clk_gate2("nfc", "nfc_frac_div", CCM_CCGR10, CCM_CCGRx_CGn(0)); | |
357 | ||
358 | clk[VF610_CLK_GPU_SEL] = imx_clk_mux("gpu_sel", CCM_CSCMR1, 14, 1, gpu_sels, 2); | |
359 | clk[VF610_CLK_GPU_EN] = imx_clk_gate("gpu_en", "gpu_sel", CCM_CSCDR2, 10); | |
360 | clk[VF610_CLK_GPU2D] = imx_clk_gate2("gpu", "gpu_en", CCM_CCGR8, CCM_CCGRx_CGn(15)); | |
361 | ||
362 | clk[VF610_CLK_VADC_SEL] = imx_clk_mux("vadc_sel", CCM_CSCMR1, 8, 2, vadc_sels, 3); | |
363 | clk[VF610_CLK_VADC_EN] = imx_clk_gate("vadc_en", "vadc_sel", CCM_CSCDR1, 22); | |
364 | clk[VF610_CLK_VADC_DIV] = imx_clk_divider("vadc_div", "vadc_en", CCM_CSCDR1, 20, 2); | |
365 | clk[VF610_CLK_VADC_DIV_HALF] = imx_clk_fixed_factor("vadc_div_half", "vadc_div", 1, 2); | |
366 | clk[VF610_CLK_VADC] = imx_clk_gate2("vadc", "vadc_div", CCM_CCGR8, CCM_CCGRx_CGn(7)); | |
367 | ||
368 | clk[VF610_CLK_ADC0] = imx_clk_gate2("adc0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(11)); | |
369 | clk[VF610_CLK_ADC1] = imx_clk_gate2("adc1", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(11)); | |
370 | clk[VF610_CLK_DAC0] = imx_clk_gate2("dac0", "ipg_bus", CCM_CCGR8, CCM_CCGRx_CGn(12)); | |
371 | clk[VF610_CLK_DAC1] = imx_clk_gate2("dac1", "ipg_bus", CCM_CCGR8, CCM_CCGRx_CGn(13)); | |
372 | ||
373 | clk[VF610_CLK_ASRC] = imx_clk_gate2("asrc", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(1)); | |
374 | ||
4349c429 SA |
375 | clk[VF610_CLK_FLEXCAN0_EN] = imx_clk_gate("flexcan0_en", "ipg_bus", CCM_CSCDR2, 11); |
376 | clk[VF610_CLK_FLEXCAN0] = imx_clk_gate2("flexcan0", "flexcan0_en", CCM_CCGR0, CCM_CCGRx_CGn(0)); | |
377 | clk[VF610_CLK_FLEXCAN1_EN] = imx_clk_gate("flexcan1_en", "ipg_bus", CCM_CSCDR2, 12); | |
378 | clk[VF610_CLK_FLEXCAN1] = imx_clk_gate2("flexcan1", "flexcan1_en", CCM_CCGR9, CCM_CCGRx_CGn(4)); | |
1f2c5fd5 | 379 | |
daaff6e9 JL |
380 | clk[VF610_CLK_DMAMUX0] = imx_clk_gate2("dmamux0", "platform_bus", CCM_CCGR0, CCM_CCGRx_CGn(4)); |
381 | clk[VF610_CLK_DMAMUX1] = imx_clk_gate2("dmamux1", "platform_bus", CCM_CCGR0, CCM_CCGRx_CGn(5)); | |
382 | clk[VF610_CLK_DMAMUX2] = imx_clk_gate2("dmamux2", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(1)); | |
383 | clk[VF610_CLK_DMAMUX3] = imx_clk_gate2("dmamux3", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(2)); | |
384 | ||
c2053895 SM |
385 | clk[VF610_CLK_SNVS] = imx_clk_gate2("snvs-rtc", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(7)); |
386 | ||
229be9c1 AS |
387 | imx_check_clocks(clk, ARRAY_SIZE(clk)); |
388 | ||
1f2c5fd5 JL |
389 | clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]); |
390 | clk_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2); | |
391 | clk_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2); | |
392 | clk_set_rate(clk[VF610_CLK_QSPI0_X1_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X2_DIV]) / 2); | |
393 | ||
394 | clk_set_parent(clk[VF610_CLK_QSPI1_SEL], clk[VF610_CLK_PLL1_PFD4]); | |
395 | clk_set_rate(clk[VF610_CLK_QSPI1_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_SEL]) / 2); | |
396 | clk_set_rate(clk[VF610_CLK_QSPI1_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_X4_DIV]) / 2); | |
397 | clk_set_rate(clk[VF610_CLK_QSPI1_X1_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_X2_DIV]) / 2); | |
398 | ||
399 | clk_set_parent(clk[VF610_CLK_SAI0_SEL], clk[VF610_CLK_AUDIO_EXT]); | |
400 | clk_set_parent(clk[VF610_CLK_SAI1_SEL], clk[VF610_CLK_AUDIO_EXT]); | |
401 | clk_set_parent(clk[VF610_CLK_SAI2_SEL], clk[VF610_CLK_AUDIO_EXT]); | |
402 | clk_set_parent(clk[VF610_CLK_SAI3_SEL], clk[VF610_CLK_AUDIO_EXT]); | |
403 | ||
3b18dd7a SA |
404 | for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) |
405 | clk_prepare_enable(clk[clks_init_on[i]]); | |
406 | ||
1f2c5fd5 JL |
407 | /* Add the clocks to provider list */ |
408 | clk_data.clks = clk; | |
409 | clk_data.clk_num = ARRAY_SIZE(clk); | |
410 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | |
411 | } | |
412 | CLK_OF_DECLARE(vf610, "fsl,vf610-ccm", vf610_clocks_init); |