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[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-imx / common.h
CommitLineData
52c543f9 1/*
df595746 2 * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved.
52c543f9
QJ
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_COMMON_H__
12#define __ASM_ARCH_MXC_COMMON_H__
13
7b6d864b
RH
14#include <linux/reboot.h>
15
d48866fe 16struct irq_data;
282b13d0 17struct platform_device;
009e63f8 18struct pt_regs;
30c730f8 19struct clk;
876292d6 20struct device_node;
a1f1c7ef 21enum mxc_cpu_pwr_mode;
e57e4ab5 22struct of_device_id;
282b13d0 23
803648db 24void mx21_map_io(void);
803648db
SG
25void mx27_map_io(void);
26void mx31_map_io(void);
27void mx35_map_io(void);
803648db 28void imx21_init_early(void);
803648db
SG
29void imx27_init_early(void);
30void imx31_init_early(void);
31void imx35_init_early(void);
803648db 32void mxc_init_irq(void __iomem *);
803648db 33void mx21_init_irq(void);
803648db
SG
34void mx27_init_irq(void);
35void mx31_init_irq(void);
36void mx35_init_irq(void);
803648db 37void imx21_soc_init(void);
803648db
SG
38void imx27_soc_init(void);
39void imx31_soc_init(void);
40void imx35_soc_init(void);
803648db 41void epit_timer_init(void __iomem *base, int irq);
803648db 42int mx21_clocks_init(unsigned long lref, unsigned long fref);
803648db
SG
43int mx27_clocks_init(unsigned long fref);
44int mx31_clocks_init(unsigned long fref);
45int mx35_clocks_init(void);
803648db 46struct platform_device *mxc_register_gpio(char *name, int id,
b78d8e59 47 resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
803648db
SG
48void mxc_set_cpu_type(unsigned int type);
49void mxc_restart(enum reboot_mode, const char *);
50void mxc_arch_reset_init(void __iomem *);
6f98cb22 51void imx1_reset_init(void __iomem *);
803648db 52void imx_set_aips(void __iomem *);
e57e4ab5 53void imx_aips_allow_unprivileged_access(const char *compat);
803648db 54int mxc_device_init(void);
bfefdff8 55void imx_set_soc_revision(unsigned int rev);
f1c6f314 56void imx_init_revision_from_anatop(void);
a2887546 57struct device *imx_soc_device_init(void);
05136f08 58void imx6_enable_rbc(bool enable);
14517564 59void imx_gpc_check_dt(void);
05136f08
AH
60void imx_gpc_set_arm_power_in_lpm(bool power_off);
61void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw);
62void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw);
8c4300c2 63void imx25_pm_init(void);
48e076da 64void imx27_pm_init(void);
73d2b4cd 65
41e7daf2
SG
66enum mxc_cpu_pwr_mode {
67 WAIT_CLOCKED, /* wfi only */
68 WAIT_UNCLOCKED, /* WAIT */
69 WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */
70 STOP_POWER_ON, /* just STOP */
71 STOP_POWER_OFF, /* STOP + SRPG */
72};
73
3ac804e3
FE
74enum mx3_cpu_pwr_mode {
75 MX3_RUN,
76 MX3_WAIT,
77 MX3_DOZE,
78 MX3_SLEEP,
79};
80
803648db 81void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode);
b6de943b 82
803648db
SG
83void imx_enable_cpu(int cpu, bool enable);
84void imx_set_cpu_jump(int cpu, void *jump_addr);
85u32 imx_get_cpu_arg(int cpu);
86void imx_set_cpu_arg(int cpu, u32 arg);
69c31b7a 87#ifdef CONFIG_SMP
803648db
SG
88void v7_secondary_startup(void);
89void imx_scu_map_io(void);
90void imx_smp_prepare(void);
13eed989
SG
91#else
92static inline void imx_scu_map_io(void) {}
a1f1c7ef 93static inline void imx_smp_prepare(void) {}
69c31b7a 94#endif
803648db 95void imx_src_init(void);
80c0ecdc 96void imx_gpc_pre_suspend(bool arm_power_off);
803648db
SG
97void imx_gpc_post_resume(void);
98void imx_gpc_mask_all(void);
99void imx_gpc_restore_all(void);
65bb688a
MZ
100void imx_gpc_hwirq_mask(unsigned int hwirq);
101void imx_gpc_hwirq_unmask(unsigned int hwirq);
803648db
SG
102void imx_anatop_init(void);
103void imx_anatop_pre_suspend(void);
104void imx_anatop_post_resume(void);
8fb76a07 105int imx6_set_lpm(enum mxc_cpu_pwr_mode mode);
8765caa5 106void imx6_set_int_mem_clk_lpm(bool enable);
751f7e99 107void imx6sl_set_wait_clk(bool enter);
ec336b28 108int imx_mmdc_get_ddr_type(void);
803648db
SG
109
110void imx_cpu_die(unsigned int cpu);
111int imx_cpu_kill(unsigned int cpu);
e4f2d979 112
c356bdb4
SG
113#ifdef CONFIG_SUSPEND
114void v7_cpu_resume(void);
1579c7b9
MF
115void imx53_suspend(void __iomem *ocram_vbase);
116extern const u32 imx53_suspend_sz;
df595746 117void imx6_suspend(void __iomem *ocram_vbase);
c356bdb4
SG
118#else
119static inline void v7_cpu_resume(void) {}
1579c7b9
MF
120static inline void imx53_suspend(void __iomem *ocram_vbase) {}
121static const u32 imx53_suspend_sz;
c356bdb4
SG
122static inline void imx6_suspend(void __iomem *ocram_vbase) {}
123#endif
124
35e2916f 125void imx6_pm_ccm_init(const char *ccm_compat);
803648db 126void imx6q_pm_init(void);
df595746
AH
127void imx6dl_pm_init(void);
128void imx6sl_pm_init(void);
ff843d62 129void imx6sx_pm_init(void);
ee4a5f83 130void imx6ul_pm_init(void);
df595746 131
28a9f3b0 132#ifdef CONFIG_PM
36b66c3f
SG
133void imx51_pm_init(void);
134void imx53_pm_init(void);
46ec1b26 135#else
36b66c3f
SG
136static inline void imx51_pm_init(void) {}
137static inline void imx53_pm_init(void) {}
46ec1b26
EM
138#endif
139
8321b758 140#ifdef CONFIG_NEON
803648db 141int mx51_neon_fixup(void);
8321b758
SG
142#else
143static inline int mx51_neon_fixup(void) { return 0; }
144#endif
145
e6a07569 146#ifdef CONFIG_CACHE_L2X0
803648db 147void imx_init_l2cache(void);
e6a07569
SG
148#else
149static inline void imx_init_l2cache(void) {}
150#endif
151
75305275
MY
152extern const struct smp_operations imx_smp_ops;
153extern const struct smp_operations ls1021a_smp_ops;
e4f2d979 154
52c543f9 155#endif