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Commit | Line | Data |
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52c543f9 | 1 | /* |
e95dddb3 | 2 | * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved. |
52c543f9 QJ |
3 | */ |
4 | ||
5 | /* | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #ifndef __ASM_ARCH_MXC_COMMON_H__ | |
12 | #define __ASM_ARCH_MXC_COMMON_H__ | |
13 | ||
7b6d864b RH |
14 | #include <linux/reboot.h> |
15 | ||
282b13d0 | 16 | struct platform_device; |
009e63f8 | 17 | struct pt_regs; |
30c730f8 | 18 | struct clk; |
a1f1c7ef | 19 | enum mxc_cpu_pwr_mode; |
282b13d0 | 20 | |
cd4a05f9 SH |
21 | extern void mx1_map_io(void); |
22 | extern void mx21_map_io(void); | |
8c25c36f | 23 | extern void mx25_map_io(void); |
cd4a05f9 SH |
24 | extern void mx27_map_io(void); |
25 | extern void mx31_map_io(void); | |
26 | extern void mx35_map_io(void); | |
a329b48c | 27 | extern void mx51_map_io(void); |
c0abefd3 | 28 | extern void mx53_map_io(void); |
3dac2196 UKK |
29 | extern void imx1_init_early(void); |
30 | extern void imx21_init_early(void); | |
31 | extern void imx25_init_early(void); | |
32 | extern void imx27_init_early(void); | |
97976e22 UKK |
33 | extern void imx31_init_early(void); |
34 | extern void imx35_init_early(void); | |
ab130421 UKK |
35 | extern void imx51_init_early(void); |
36 | extern void imx53_init_early(void); | |
c5aa0ad0 | 37 | extern void mxc_init_irq(void __iomem *); |
a003708a | 38 | extern void tzic_init_irq(void __iomem *); |
c5aa0ad0 SH |
39 | extern void mx1_init_irq(void); |
40 | extern void mx21_init_irq(void); | |
8c25c36f | 41 | extern void mx25_init_irq(void); |
c5aa0ad0 SH |
42 | extern void mx27_init_irq(void); |
43 | extern void mx31_init_irq(void); | |
44 | extern void mx35_init_irq(void); | |
a329b48c | 45 | extern void mx51_init_irq(void); |
c0abefd3 | 46 | extern void mx53_init_irq(void); |
b78d8e59 SG |
47 | extern void imx1_soc_init(void); |
48 | extern void imx21_soc_init(void); | |
49 | extern void imx25_soc_init(void); | |
50 | extern void imx27_soc_init(void); | |
51 | extern void imx31_soc_init(void); | |
52 | extern void imx35_soc_init(void); | |
b78d8e59 | 53 | extern void imx51_soc_init(void); |
8321b758 | 54 | extern void imx51_init_late(void); |
aa96a18d | 55 | extern void imx53_init_late(void); |
2cfb4518 SH |
56 | extern void epit_timer_init(void __iomem *base, int irq); |
57 | extern void mxc_timer_init(void __iomem *, int); | |
30c730f8 | 58 | extern int mx1_clocks_init(unsigned long fref); |
aa3b0a6f | 59 | extern int mx21_clocks_init(unsigned long lref, unsigned long fref); |
fadc0956 | 60 | extern int mx25_clocks_init(void); |
30c730f8 SH |
61 | extern int mx27_clocks_init(unsigned long fref); |
62 | extern int mx31_clocks_init(unsigned long fref); | |
2cb536d1 | 63 | extern int mx35_clocks_init(void); |
a329b48c AK |
64 | extern int mx51_clocks_init(unsigned long ckil, unsigned long osc, |
65 | unsigned long ckih1, unsigned long ckih2); | |
ef4bac55 | 66 | extern int mx25_clocks_init_dt(void); |
9f0749e3 | 67 | extern int mx27_clocks_init_dt(void); |
d2a37b3d | 68 | extern int mx31_clocks_init_dt(void); |
e7fc6ae7 | 69 | extern struct platform_device *mxc_register_gpio(char *name, int id, |
b78d8e59 | 70 | resource_size_t iobase, resource_size_t iosize, int irq, int irq_high); |
198016e1 | 71 | extern void mxc_set_cpu_type(unsigned int type); |
7b6d864b | 72 | extern void mxc_restart(enum reboot_mode, const char *); |
be124c94 | 73 | extern void mxc_arch_reset_init(void __iomem *); |
c1e31d12 | 74 | extern void mxc_arch_reset_init_dt(void); |
c0abefd3 | 75 | extern int mx53_revision(void); |
bb07d751 | 76 | extern void imx_set_aips(void __iomem *); |
69ac71d3 | 77 | extern int mxc_device_init(void); |
bfefdff8 SG |
78 | void imx_set_soc_revision(unsigned int rev); |
79 | unsigned int imx_get_soc_revision(void); | |
f1c6f314 | 80 | void imx_init_revision_from_anatop(void); |
a2887546 | 81 | struct device *imx_soc_device_init(void); |
73d2b4cd | 82 | |
41e7daf2 SG |
83 | enum mxc_cpu_pwr_mode { |
84 | WAIT_CLOCKED, /* wfi only */ | |
85 | WAIT_UNCLOCKED, /* WAIT */ | |
86 | WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */ | |
87 | STOP_POWER_ON, /* just STOP */ | |
88 | STOP_POWER_OFF, /* STOP + SRPG */ | |
89 | }; | |
90 | ||
3ac804e3 FE |
91 | enum mx3_cpu_pwr_mode { |
92 | MX3_RUN, | |
93 | MX3_WAIT, | |
94 | MX3_DOZE, | |
95 | MX3_SLEEP, | |
96 | }; | |
97 | ||
98 | extern void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode); | |
059e58f6 | 99 | extern void imx_print_silicon_rev(const char *cpu, int srev); |
b6de943b SH |
100 | |
101 | void avic_handle_irq(struct pt_regs *); | |
58a92600 | 102 | void tzic_handle_irq(struct pt_regs *); |
b6de943b SH |
103 | |
104 | #define imx1_handle_irq avic_handle_irq | |
105 | #define imx21_handle_irq avic_handle_irq | |
106 | #define imx25_handle_irq avic_handle_irq | |
107 | #define imx27_handle_irq avic_handle_irq | |
108 | #define imx31_handle_irq avic_handle_irq | |
109 | #define imx35_handle_irq avic_handle_irq | |
58a92600 SH |
110 | #define imx51_handle_irq tzic_handle_irq |
111 | #define imx53_handle_irq tzic_handle_irq | |
b6de943b | 112 | |
69c31b7a SG |
113 | extern void imx_enable_cpu(int cpu, bool enable); |
114 | extern void imx_set_cpu_jump(int cpu, void *jump_addr); | |
2f3edfd7 SG |
115 | extern u32 imx_get_cpu_arg(int cpu); |
116 | extern void imx_set_cpu_arg(int cpu, u32 arg); | |
a1f1c7ef | 117 | extern void v7_cpu_resume(void); |
69c31b7a SG |
118 | #ifdef CONFIG_SMP |
119 | extern void v7_secondary_startup(void); | |
13eed989 | 120 | extern void imx_scu_map_io(void); |
a1f1c7ef | 121 | extern void imx_smp_prepare(void); |
e5f9dec8 | 122 | extern void imx_scu_standby_enable(void); |
13eed989 SG |
123 | #else |
124 | static inline void imx_scu_map_io(void) {} | |
a1f1c7ef | 125 | static inline void imx_smp_prepare(void) {} |
e5f9dec8 | 126 | static inline void imx_scu_standby_enable(void) {} |
69c31b7a | 127 | #endif |
13eed989 | 128 | extern void imx_src_init(void); |
0575fb75 | 129 | extern void imx_src_prepare_restart(void); |
13eed989 | 130 | extern void imx_gpc_init(void); |
a1f1c7ef SG |
131 | extern void imx_gpc_pre_suspend(void); |
132 | extern void imx_gpc_post_resume(void); | |
263475d4 AH |
133 | extern void imx_gpc_mask_all(void); |
134 | extern void imx_gpc_restore_all(void); | |
e95dddb3 AH |
135 | extern void imx_anatop_init(void); |
136 | extern void imx_anatop_pre_suspend(void); | |
137 | extern void imx_anatop_post_resume(void); | |
a1f1c7ef | 138 | extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); |
e5f9dec8 | 139 | extern void imx6q_set_chicken_bit(void); |
46ec1b26 | 140 | |
e4f2d979 | 141 | extern void imx_cpu_die(unsigned int cpu); |
83757664 | 142 | extern int imx_cpu_kill(unsigned int cpu); |
e4f2d979 | 143 | |
46ec1b26 EM |
144 | #ifdef CONFIG_PM |
145 | extern void imx6q_pm_init(void); | |
547dd1e0 | 146 | extern void imx5_pm_init(void); |
46ec1b26 EM |
147 | #else |
148 | static inline void imx6q_pm_init(void) {} | |
547dd1e0 | 149 | static inline void imx5_pm_init(void) {} |
46ec1b26 EM |
150 | #endif |
151 | ||
8321b758 SG |
152 | #ifdef CONFIG_NEON |
153 | extern int mx51_neon_fixup(void); | |
154 | #else | |
155 | static inline int mx51_neon_fixup(void) { return 0; } | |
156 | #endif | |
157 | ||
e6a07569 SG |
158 | #ifdef CONFIG_CACHE_L2X0 |
159 | extern void imx_init_l2cache(void); | |
160 | #else | |
161 | static inline void imx_init_l2cache(void) {} | |
162 | #endif | |
163 | ||
e4f2d979 MZ |
164 | extern struct smp_operations imx_smp_ops; |
165 | ||
52c543f9 | 166 | #endif |