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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
d27536c6 JL |
2 | /* |
3 | * MX25 CPU type detection | |
4 | * | |
5 | * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> | |
6 | * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved | |
d27536c6 JL |
7 | */ |
8 | #include <linux/module.h> | |
9 | #include <linux/io.h> | |
8b88f7ef FE |
10 | #include <linux/of.h> |
11 | #include <linux/of_address.h> | |
17c342ae SG |
12 | |
13 | #include "iim.h" | |
50f2de61 | 14 | #include "hardware.h" |
d27536c6 JL |
15 | |
16 | static int mx25_cpu_rev = -1; | |
17 | ||
18 | static int mx25_read_cpu_rev(void) | |
19 | { | |
20 | u32 rev; | |
8b88f7ef FE |
21 | void __iomem *iim_base; |
22 | struct device_node *np; | |
23 | ||
24 | np = of_find_compatible_node(NULL, NULL, "fsl,imx25-iim"); | |
25 | iim_base = of_iomap(np, 0); | |
26 | BUG_ON(!iim_base); | |
27 | rev = readl(iim_base + MXC_IIMSREV); | |
28 | iounmap(iim_base); | |
d27536c6 | 29 | |
d27536c6 JL |
30 | switch (rev) { |
31 | case 0x00: | |
32 | return IMX_CHIP_REVISION_1_0; | |
33 | case 0x01: | |
34 | return IMX_CHIP_REVISION_1_1; | |
35 | default: | |
36 | return IMX_CHIP_REVISION_UNKNOWN; | |
37 | } | |
38 | } | |
39 | ||
40 | int mx25_revision(void) | |
41 | { | |
42 | if (mx25_cpu_rev == -1) | |
43 | mx25_cpu_rev = mx25_read_cpu_rev(); | |
44 | ||
45 | return mx25_cpu_rev; | |
46 | } | |
47 | EXPORT_SYMBOL(mx25_revision); |