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fcaf2036 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
a329b48c | 2 | /* |
b66ff7a2 | 3 | * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. |
a329b48c | 4 | * |
a329b48c AK |
5 | * This file contains the CPU initialization code. |
6 | */ | |
7 | ||
8 | #include <linux/types.h> | |
9 | #include <linux/kernel.h> | |
10 | #include <linux/init.h> | |
5443856c | 11 | #include <linux/module.h> |
ca06679d | 12 | #include <linux/io.h> |
ee18a715 SG |
13 | #include <linux/of.h> |
14 | #include <linux/of_address.h> | |
a329b48c | 15 | |
50f2de61 | 16 | #include "hardware.h" |
22567796 | 17 | #include "common.h" |
50f2de61 | 18 | |
c52c9835 | 19 | static int mx5_cpu_rev = -1; |
5443856c | 20 | |
9ab4650f | 21 | #define IIM_SREV 0x24 |
5443856c | 22 | |
ee18a715 SG |
23 | static u32 imx5_read_srev_reg(const char *compat) |
24 | { | |
25 | void __iomem *iim_base; | |
26 | struct device_node *np; | |
27 | u32 srev; | |
28 | ||
29 | np = of_find_compatible_node(NULL, NULL, compat); | |
30 | iim_base = of_iomap(np, 0); | |
31 | WARN_ON(!iim_base); | |
32 | ||
33 | srev = readl(iim_base + IIM_SREV) & 0xff; | |
34 | ||
35 | iounmap(iim_base); | |
36 | ||
37 | return srev; | |
38 | } | |
39 | ||
9ab4650f | 40 | static int get_mx51_srev(void) |
5443856c | 41 | { |
ee18a715 | 42 | u32 rev = imx5_read_srev_reg("fsl,imx51-iim"); |
5443856c | 43 | |
c52c9835 JL |
44 | switch (rev) { |
45 | case 0x0: | |
9ab4650f | 46 | return IMX_CHIP_REVISION_2_0; |
c52c9835 | 47 | case 0x10: |
9ab4650f | 48 | return IMX_CHIP_REVISION_3_0; |
c52c9835 JL |
49 | default: |
50 | return IMX_CHIP_REVISION_UNKNOWN; | |
51 | } | |
5443856c SH |
52 | } |
53 | ||
54 | /* | |
55 | * Returns: | |
56 | * the silicon revision of the cpu | |
5443856c SH |
57 | */ |
58 | int mx51_revision(void) | |
59 | { | |
c52c9835 JL |
60 | if (mx5_cpu_rev == -1) |
61 | mx5_cpu_rev = get_mx51_srev(); | |
5443856c | 62 | |
c52c9835 | 63 | return mx5_cpu_rev; |
5443856c SH |
64 | } |
65 | EXPORT_SYMBOL(mx51_revision); | |
66 | ||
33d7c5c1 AK |
67 | #ifdef CONFIG_NEON |
68 | ||
69 | /* | |
70 | * All versions of the silicon before Rev. 3 have broken NEON implementations. | |
71 | * Dependent on link order - so the assumption is that vfp_init is called | |
72 | * before us. | |
73 | */ | |
8321b758 | 74 | int __init mx51_neon_fixup(void) |
33d7c5c1 | 75 | { |
ca06679d FE |
76 | if (mx51_revision() < IMX_CHIP_REVISION_3_0 && |
77 | (elf_hwcap & HWCAP_NEON)) { | |
33d7c5c1 AK |
78 | elf_hwcap &= ~HWCAP_NEON; |
79 | pr_info("Turning off NEON support, detected broken NEON implementation\n"); | |
80 | } | |
81 | return 0; | |
82 | } | |
83 | ||
33d7c5c1 AK |
84 | #endif |
85 | ||
9ab4650f DN |
86 | static int get_mx53_srev(void) |
87 | { | |
ee18a715 | 88 | u32 rev = imx5_read_srev_reg("fsl,imx53-iim"); |
9ab4650f | 89 | |
503e1639 RZ |
90 | switch (rev) { |
91 | case 0x0: | |
9ab4650f | 92 | return IMX_CHIP_REVISION_1_0; |
503e1639 | 93 | case 0x2: |
9ab4650f | 94 | return IMX_CHIP_REVISION_2_0; |
503e1639 RZ |
95 | case 0x3: |
96 | return IMX_CHIP_REVISION_2_1; | |
97 | default: | |
98 | return IMX_CHIP_REVISION_UNKNOWN; | |
99 | } | |
9ab4650f DN |
100 | } |
101 | ||
b66ff7a2 DN |
102 | /* |
103 | * Returns: | |
104 | * the silicon revision of the cpu | |
b66ff7a2 DN |
105 | */ |
106 | int mx53_revision(void) | |
107 | { | |
c52c9835 JL |
108 | if (mx5_cpu_rev == -1) |
109 | mx5_cpu_rev = get_mx53_srev(); | |
b66ff7a2 | 110 | |
c52c9835 | 111 | return mx5_cpu_rev; |
b66ff7a2 DN |
112 | } |
113 | EXPORT_SYMBOL(mx53_revision); | |
26b754f9 FE |
114 | |
115 | #define ARM_GPC 0x4 | |
116 | #define DBGEN BIT(16) | |
117 | ||
118 | /* | |
119 | * This enables the DBGEN bit in ARM_GPC register, which is | |
120 | * required for accessing some performance counter features. | |
121 | * Technically it is only required while perf is used, but to | |
122 | * keep the source code simple we just enable it all the time | |
123 | * when the kernel configuration allows using the feature. | |
124 | */ | |
125 | void __init imx5_pmu_init(void) | |
126 | { | |
127 | void __iomem *tigerp_base; | |
128 | struct device_node *np; | |
129 | u32 gpc; | |
130 | ||
131 | if (!IS_ENABLED(CONFIG_ARM_PMU)) | |
132 | return; | |
133 | ||
134 | np = of_find_compatible_node(NULL, NULL, "arm,cortex-a8-pmu"); | |
135 | if (!np) | |
136 | return; | |
137 | ||
138 | if (!of_property_read_bool(np, "secure-reg-access")) | |
139 | goto exit; | |
140 | ||
141 | of_node_put(np); | |
142 | ||
143 | np = of_find_compatible_node(NULL, NULL, "fsl,imx51-tigerp"); | |
144 | if (!np) | |
145 | return; | |
146 | ||
147 | tigerp_base = of_iomap(np, 0); | |
148 | if (!tigerp_base) | |
149 | goto exit; | |
150 | ||
151 | gpc = readl_relaxed(tigerp_base + ARM_GPC); | |
152 | gpc |= DBGEN; | |
153 | writel_relaxed(gpc, tigerp_base + ARM_GPC); | |
154 | iounmap(tigerp_base); | |
155 | exit: | |
156 | of_node_put(np); | |
157 | ||
158 | } |