[mirror_ubuntu-jammy-kernel.git] / arch / arm / mach-imx / cpuidle-imx6sx.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2014 Freescale Semiconductor, Inc.
 */

#include <linux/cpuidle.h>
#include <linux/cpu_pm.h>
#include <linux/module.h>
#include <asm/cacheflush.h>
#include <asm/cpuidle.h>
#include <asm/suspend.h>

#include "common.h"
#include "cpuidle.h"

static int imx6sx_idle_finish(unsigned long val)
{
	/*
	 * for Cortex-A7 which has an internal L2
	 * cache, need to flush it before powering
	 * down ARM platform, since flushing L1 cache
	 * here again has very small overhead, compared
	 * to adding conditional code for L2 cache type,
	 * just call flush_cache_all() is fine.
	 */
	flush_cache_all();
	cpu_do_idle();

	return 0;
}

static int imx6sx_enter_wait(struct cpuidle_device *dev,
			    struct cpuidle_driver *drv, int index)
{
	imx6_set_lpm(WAIT_UNCLOCKED);

	switch (index) {
	case 1:
		cpu_do_idle();
		break;
	case 2:
		imx6_enable_rbc(true);
		imx_gpc_set_arm_power_in_lpm(true);
		imx_set_cpu_jump(0, v7_cpu_resume);
		/* Need to notify there is a cpu pm operation. */
		cpu_pm_enter();
		cpu_cluster_pm_enter();

		cpu_suspend(0, imx6sx_idle_finish);

		cpu_cluster_pm_exit();
		cpu_pm_exit();
		imx_gpc_set_arm_power_in_lpm(false);
		imx6_enable_rbc(false);
		break;
	default:
		break;
	}

	imx6_set_lpm(WAIT_CLOCKED);

	return index;
}

static struct cpuidle_driver imx6sx_cpuidle_driver = {
	.name = "imx6sx_cpuidle",
	.owner = THIS_MODULE,
	.states = {
		/* WFI */
		ARM_CPUIDLE_WFI_STATE,
		/* WAIT */
		{
			.exit_latency = 50,
			.target_residency = 75,
			.flags = CPUIDLE_FLAG_TIMER_STOP,
			.enter = imx6sx_enter_wait,
			.name = "WAIT",
			.desc = "Clock off",
		},
		/* WAIT + ARM power off  */
		{
			/*
			 * ARM gating 31us * 5 + RBC clear 65us
			 * and some margin for SW execution, here set it
			 * to 300us.
			 */
			.exit_latency = 300,
			.target_residency = 500,
			.flags = CPUIDLE_FLAG_TIMER_STOP,
			.enter = imx6sx_enter_wait,
			.name = "LOW-POWER-IDLE",
			.desc = "ARM power off",
		},
	},
	.state_count = 3,
	.safe_state_index = 0,
};

int __init imx6sx_cpuidle_init(void)
{
	imx6_set_int_mem_clk_lpm(true);
	imx6_enable_rbc(false);
	imx_gpc_set_l2_mem_power_in_lpm(false);
	/*
	 * set ARM power up/down timing to the fastest,
	 * sw2iso and sw can be set to one 32K cycle = 31us
	 * except for power up sw2iso which need to be
	 * larger than LDO ramp up time.
	 */
	imx_gpc_set_arm_power_up_timing(0xf, 1);
	imx_gpc_set_arm_power_down_timing(1, 1);

	return cpuidle_register(&imx6sx_cpuidle_driver, NULL);
}
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
05136f08 AH	2	/*
05136f08 AH	3	* Copyright (C) 2014 Freescale Semiconductor, Inc.
05136f08 AH	4	*/
	5
	6	#include <linux/cpuidle.h>
	7	#include <linux/cpu_pm.h>
	8	#include <linux/module.h>
547e8f52	9	#include <asm/cacheflush.h>
05136f08	10	#include <asm/cpuidle.h>
05136f08 AH	11	#include <asm/suspend.h>
	12
	13	#include "common.h"
	14	#include "cpuidle.h"
	15
	16	static int imx6sx_idle_finish(unsigned long val)
	17	{
547e8f52 AH	18	/*
	19	* for Cortex-A7 which has an internal L2
	20	* cache, need to flush it before powering
	21	* down ARM platform, since flushing L1 cache
	22	* here again has very small overhead, compared
	23	* to adding conditional code for L2 cache type,
	24	* just call flush_cache_all() is fine.
	25	*/
	26	flush_cache_all();
05136f08 AH	27	cpu_do_idle();
	28
	29	return 0;
	30	}
	31
	32	static int imx6sx_enter_wait(struct cpuidle_device *dev,
	33	struct cpuidle_driver *drv, int index)
	34	{
8fb76a07	35	imx6_set_lpm(WAIT_UNCLOCKED);
05136f08 AH	36
	37	switch (index) {
	38	case 1:
	39	cpu_do_idle();
	40	break;
	41	case 2:
	42	imx6_enable_rbc(true);
	43	imx_gpc_set_arm_power_in_lpm(true);
	44	imx_set_cpu_jump(0, v7_cpu_resume);
	45	/* Need to notify there is a cpu pm operation. */
	46	cpu_pm_enter();
	47	cpu_cluster_pm_enter();
	48
	49	cpu_suspend(0, imx6sx_idle_finish);
	50
	51	cpu_cluster_pm_exit();
	52	cpu_pm_exit();
	53	imx_gpc_set_arm_power_in_lpm(false);
	54	imx6_enable_rbc(false);
	55	break;
	56	default:
	57	break;
	58	}
	59
8fb76a07	60	imx6_set_lpm(WAIT_CLOCKED);
05136f08 AH	61
	62	return index;
	63	}
	64
	65	static struct cpuidle_driver imx6sx_cpuidle_driver = {
	66	.name = "imx6sx_cpuidle",
	67	.owner = THIS_MODULE,
	68	.states = {
	69	/* WFI */
	70	ARM_CPUIDLE_WFI_STATE,
	71	/* WAIT */
	72	{
	73	.exit_latency = 50,
	74	.target_residency = 75,
c8aeb7df	75	.flags = CPUIDLE_FLAG_TIMER_STOP,
05136f08 AH	76	.enter = imx6sx_enter_wait,
	77	.name = "WAIT",
	78	.desc = "Clock off",
	79	},
	80	/* WAIT + ARM power off */
	81	{
	82	/*
	83	* ARM gating 31us * 5 + RBC clear 65us
	84	* and some margin for SW execution, here set it
	85	* to 300us.
	86	*/
	87	.exit_latency = 300,
	88	.target_residency = 500,
49a1a99c	89	.flags = CPUIDLE_FLAG_TIMER_STOP,
05136f08 AH	90	.enter = imx6sx_enter_wait,
	91	.name = "LOW-POWER-IDLE",
	92	.desc = "ARM power off",
	93	},
	94	},
	95	.state_count = 3,
	96	.safe_state_index = 0,
	97	};
	98
	99	int __init imx6sx_cpuidle_init(void)
	100	{
6ae44aa6	101	imx6_set_int_mem_clk_lpm(true);
05136f08	102	imx6_enable_rbc(false);
e7fa1fb3	103	imx_gpc_set_l2_mem_power_in_lpm(false);
05136f08 AH	104	/*
	105	* set ARM power up/down timing to the fastest,
	106	* sw2iso and sw can be set to one 32K cycle = 31us
	107	* except for power up sw2iso which need to be
	108	* larger than LDO ramp up time.
	109	*/
1e434b70	110	imx_gpc_set_arm_power_up_timing(0xf, 1);
05136f08 AH	111	imx_gpc_set_arm_power_down_timing(1, 1);
	112
	113	return cpuidle_register(&imx6sx_cpuidle_driver, NULL);
	114	}