[mirror_ubuntu-bionic-kernel.git] / arch / arm / mach-imx / irq.c

/*
 *  linux/arch/arm/mach-imx/irq.c
 *
 *  Copyright (C) 1999 ARM Limited
 *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 *  03/03/2004   Sascha Hauer <sascha@saschahauer.de>
 *               Copied from the motorola bsp package and added gpio demux
 *               interrupt handler
 */

#include <linux/init.h>
#include <linux/list.h>
#include <linux/timer.h>

#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/io.h>

#include <asm/mach/irq.h>

/*
 *
 * We simply use the ENABLE DISABLE registers inside of the IMX
 * to turn on/off specific interrupts.  FIXME- We should
 * also add support for the accelerated interrupt controller
 * by putting offets to irq jump code in the appropriate
 * places.
 *
 */

#define INTENNUM_OFF              0x8
#define INTDISNUM_OFF             0xC

#define VA_AITC_BASE              IO_ADDRESS(IMX_AITC_BASE)
#define IMX_AITC_INTDISNUM       (VA_AITC_BASE + INTDISNUM_OFF)
#define IMX_AITC_INTENNUM        (VA_AITC_BASE + INTENNUM_OFF)

#if 0
#define DEBUG_IRQ(fmt...)	printk(fmt)
#else
#define DEBUG_IRQ(fmt...)	do { } while (0)
#endif

static void
imx_mask_irq(unsigned int irq)
{
	__raw_writel(irq, IMX_AITC_INTDISNUM);
}

static void
imx_unmask_irq(unsigned int irq)
{
	__raw_writel(irq, IMX_AITC_INTENNUM);
}

static int
imx_gpio_irq_type(unsigned int _irq, unsigned int type)
{
	unsigned int irq_type = 0, irq, reg, bit;

	irq = _irq - IRQ_GPIOA(0);
	reg = irq >> 5;
	bit = 1 << (irq % 32);

	if (type == IRQT_PROBE) {
		/* Don't mess with enabled GPIOs using preconfigured edges or
		   GPIOs set to alternate function during probe */
		/* TODO: support probe */
//              if ((GPIO_IRQ_rising_edge[idx] | GPIO_IRQ_falling_edge[idx]) &
//                  GPIO_bit(gpio))
//                      return 0;
//              if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2)))
//                      return 0;
//              type = __IRQT_RISEDGE | __IRQT_FALEDGE;
	}

	GIUS(reg) |= bit;
	DDIR(reg) &= ~(bit);

	DEBUG_IRQ("setting type of irq %d to ", _irq);

	if (type & __IRQT_RISEDGE) {
		DEBUG_IRQ("rising edges\n");
		irq_type = 0x0;
	}
	if (type & __IRQT_FALEDGE) {
		DEBUG_IRQ("falling edges\n");
		irq_type = 0x1;
	}
	if (type & __IRQT_LOWLVL) {
		DEBUG_IRQ("low level\n");
		irq_type = 0x3;
	}
	if (type & __IRQT_HIGHLVL) {
		DEBUG_IRQ("high level\n");
		irq_type = 0x2;
	}

	if (irq % 32 < 16) {
		ICR1(reg) = (ICR1(reg) & ~(0x3 << ((irq % 16) * 2))) |
		    (irq_type << ((irq % 16) * 2));
	} else {
		ICR2(reg) = (ICR2(reg) & ~(0x3 << ((irq % 16) * 2))) |
		    (irq_type << ((irq % 16) * 2));
	}

	return 0;

}

static void
imx_gpio_ack_irq(unsigned int irq)
{
	DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, irq);
	ISR(IRQ_TO_REG(irq)) = 1 << ((irq - IRQ_GPIOA(0)) % 32);
}

static void
imx_gpio_mask_irq(unsigned int irq)
{
	DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, irq);
	IMR(IRQ_TO_REG(irq)) &= ~( 1 << ((irq - IRQ_GPIOA(0)) % 32));
}

static void
imx_gpio_unmask_irq(unsigned int irq)
{
	DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, irq);
	IMR(IRQ_TO_REG(irq)) |= 1 << ((irq - IRQ_GPIOA(0)) % 32);
}

static void
imx_gpio_handler(unsigned int mask, unsigned int irq,
                 struct irqdesc *desc)
{
	desc = irq_desc + irq;
	while (mask) {
		if (mask & 1) {
			DEBUG_IRQ("handling irq %d\n", irq);
			desc_handle_irq(irq, desc);
		}
		irq++;
		desc++;
		mask >>= 1;
	}
}

static void
imx_gpioa_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
{
	unsigned int mask, irq;

	mask = ISR(0);
	irq = IRQ_GPIOA(0);
	imx_gpio_handler(mask, irq, desc);
}

static void
imx_gpiob_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
{
	unsigned int mask, irq;

	mask = ISR(1);
	irq = IRQ_GPIOB(0);
	imx_gpio_handler(mask, irq, desc);
}

static void
imx_gpioc_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
{
	unsigned int mask, irq;

	mask = ISR(2);
	irq = IRQ_GPIOC(0);
	imx_gpio_handler(mask, irq, desc);
}

static void
imx_gpiod_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
{
	unsigned int mask, irq;

	mask = ISR(3);
	irq = IRQ_GPIOD(0);
	imx_gpio_handler(mask, irq, desc);
}

static struct irq_chip imx_internal_chip = {
	.name = "MPU",
	.ack = imx_mask_irq,
	.mask = imx_mask_irq,
	.unmask = imx_unmask_irq,
};

static struct irq_chip imx_gpio_chip = {
	.name = "GPIO",
	.ack = imx_gpio_ack_irq,
	.mask = imx_gpio_mask_irq,
	.unmask = imx_gpio_unmask_irq,
	.set_type = imx_gpio_irq_type,
};

void __init
imx_init_irq(void)
{
	unsigned int irq;

	DEBUG_IRQ("Initializing imx interrupts\n");

	/* Mask all interrupts initially */
	IMR(0) = 0;
	IMR(1) = 0;
	IMR(2) = 0;
	IMR(3) = 0;

	for (irq = 0; irq < IMX_IRQS; irq++) {
		set_irq_chip(irq, &imx_internal_chip);
		set_irq_handler(irq, do_level_IRQ);
		set_irq_flags(irq, IRQF_VALID);
	}

	for (irq = IRQ_GPIOA(0); irq < IRQ_GPIOD(32); irq++) {
		set_irq_chip(irq, &imx_gpio_chip);
		set_irq_handler(irq, do_edge_IRQ);
		set_irq_flags(irq, IRQF_VALID);
	}

	set_irq_chained_handler(GPIO_INT_PORTA, imx_gpioa_demux_handler);
	set_irq_chained_handler(GPIO_INT_PORTB, imx_gpiob_demux_handler);
	set_irq_chained_handler(GPIO_INT_PORTC, imx_gpioc_demux_handler);
	set_irq_chained_handler(GPIO_INT_PORTD, imx_gpiod_demux_handler);

	/* Disable all interrupts initially. */
	/* In IMX this is done in the bootloader. */
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-imx/irq.c
	3	*
	4	* Copyright (C) 1999 ARM Limited
	5	* Copyright (C) 2002 Shane Nay (shane@minirl.com)
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*
	21	* 03/03/2004 Sascha Hauer <sascha@saschahauer.de>
	22	* Copied from the motorola bsp package and added gpio demux
	23	* interrupt handler
	24	*/
	25
	26	#include <linux/init.h>
	27	#include <linux/list.h>
	28	#include <linux/timer.h>
	29
	30	#include <asm/hardware.h>
	31	#include <asm/irq.h>
	32	#include <asm/io.h>
	33
	34	#include <asm/mach/irq.h>
	35
	36	/*
	37	*
	38	* We simply use the ENABLE DISABLE registers inside of the IMX
	39	* to turn on/off specific interrupts. FIXME- We should
	40	* also add support for the accelerated interrupt controller
	41	* by putting offets to irq jump code in the appropriate
	42	* places.
	43	*
	44	*/
	45
	46	#define INTENNUM_OFF 0x8
	47	#define INTDISNUM_OFF 0xC
	48
	49	#define VA_AITC_BASE IO_ADDRESS(IMX_AITC_BASE)
	50	#define IMX_AITC_INTDISNUM (VA_AITC_BASE + INTDISNUM_OFF)
	51	#define IMX_AITC_INTENNUM (VA_AITC_BASE + INTENNUM_OFF)
	52
	53	#if 0
	54	#define DEBUG_IRQ(fmt...) printk(fmt)
	55	#else
	56	#define DEBUG_IRQ(fmt...) do { } while (0)
	57	#endif
	58
	59	static void
	60	imx_mask_irq(unsigned int irq)
	61	{
	62	__raw_writel(irq, IMX_AITC_INTDISNUM);
	63	}
	64
65	static void
66	imx_unmask_irq(unsigned int irq)
67	{
68	__raw_writel(irq, IMX_AITC_INTENNUM);
69	}
70
71	static int
72	imx_gpio_irq_type(unsigned int _irq, unsigned int type)
73	{
74	unsigned int irq_type = 0, irq, reg, bit;
75
76	irq = _irq - IRQ_GPIOA(0);
77	reg = irq >> 5;
78	bit = 1 << (irq % 32);
79
80	if (type == IRQT_PROBE) {
81	/* Don't mess with enabled GPIOs using preconfigured edges or
82	GPIOs set to alternate function during probe */
83	/* TODO: support probe */
84	// if ((GPIO_IRQ_rising_edge[idx] \| GPIO_IRQ_falling_edge[idx]) &
85	// GPIO_bit(gpio))
86	// return 0;
87	// if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2)))
88	// return 0;
89	// type = __IRQT_RISEDGE \| __IRQT_FALEDGE;
90	}
91
92	GIUS(reg) \|= bit;
93	DDIR(reg) &= ~(bit);
94
95	DEBUG_IRQ("setting type of irq %d to ", _irq);
96
97	if (type & __IRQT_RISEDGE) {
98	DEBUG_IRQ("rising edges\n");
99	irq_type = 0x0;
100	}
101	if (type & __IRQT_FALEDGE) {
102	DEBUG_IRQ("falling edges\n");
103	irq_type = 0x1;
104	}
105	if (type & __IRQT_LOWLVL) {
106	DEBUG_IRQ("low level\n");
107	irq_type = 0x3;
108	}
109	if (type & __IRQT_HIGHLVL) {
110	DEBUG_IRQ("high level\n");
111	irq_type = 0x2;
112	}
113
114	if (irq % 32 < 16) {
115	ICR1(reg) = (ICR1(reg) & ~(0x3 << ((irq % 16) * 2))) \|
116	(irq_type << ((irq % 16) * 2));
117	} else {
118	ICR2(reg) = (ICR2(reg) & ~(0x3 << ((irq % 16) * 2))) \|
119	(irq_type << ((irq % 16) * 2));
120	}
121
122	return 0;
123
124	}
125
126	static void
127	imx_gpio_ack_irq(unsigned int irq)
128	{
129	DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, irq);
e2f04e18	130	ISR(IRQ_TO_REG(irq)) = 1 << ((irq - IRQ_GPIOA(0)) % 32);
1da177e4 LT	131	}
	132
	133	static void
	134	imx_gpio_mask_irq(unsigned int irq)
	135	{
	136	DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, irq);
	137	IMR(IRQ_TO_REG(irq)) &= ~( 1 << ((irq - IRQ_GPIOA(0)) % 32));
	138	}
	139
	140	static void
	141	imx_gpio_unmask_irq(unsigned int irq)
	142	{
	143	DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, irq);
	144	IMR(IRQ_TO_REG(irq)) \|= 1 << ((irq - IRQ_GPIOA(0)) % 32);
	145	}
	146
	147	static void
	148	imx_gpio_handler(unsigned int mask, unsigned int irq,
0cd61b68	149	struct irqdesc *desc)
1da177e4 LT	150	{
	151	desc = irq_desc + irq;
	152	while (mask) {
	153	if (mask & 1) {
	154	DEBUG_IRQ("handling irq %d\n", irq);
0cd61b68	155	desc_handle_irq(irq, desc);
1da177e4 LT	156	}
	157	irq++;
	158	desc++;
	159	mask >>= 1;
	160	}
	161	}
	162
	163	static void
0cd61b68	164	imx_gpioa_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
1da177e4 LT	165	{
	166	unsigned int mask, irq;
	167
	168	mask = ISR(0);
	169	irq = IRQ_GPIOA(0);
0cd61b68	170	imx_gpio_handler(mask, irq, desc);
1da177e4 LT	171	}
	172
	173	static void
0cd61b68	174	imx_gpiob_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
1da177e4 LT	175	{
	176	unsigned int mask, irq;
	177
	178	mask = ISR(1);
	179	irq = IRQ_GPIOB(0);
0cd61b68	180	imx_gpio_handler(mask, irq, desc);
1da177e4 LT	181	}
	182
	183	static void
0cd61b68	184	imx_gpioc_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
1da177e4 LT	185	{
	186	unsigned int mask, irq;
	187
	188	mask = ISR(2);
	189	irq = IRQ_GPIOC(0);
0cd61b68	190	imx_gpio_handler(mask, irq, desc);
1da177e4 LT	191	}
	192
	193	static void
0cd61b68	194	imx_gpiod_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
1da177e4 LT	195	{
	196	unsigned int mask, irq;
	197
	198	mask = ISR(3);
	199	irq = IRQ_GPIOD(0);
0cd61b68	200	imx_gpio_handler(mask, irq, desc);
1da177e4 LT	201	}
1da177e4 LT	202
38c677cb DB	203	static struct irq_chip imx_internal_chip = {
38c677cb DB	204	.name = "MPU",
1da177e4 LT	205	.ack = imx_mask_irq,
	206	.mask = imx_mask_irq,
	207	.unmask = imx_unmask_irq,
	208	};
	209
38c677cb DB	210	static struct irq_chip imx_gpio_chip = {
38c677cb DB	211	.name = "GPIO",
1da177e4 LT	212	.ack = imx_gpio_ack_irq,
	213	.mask = imx_gpio_mask_irq,
	214	.unmask = imx_gpio_unmask_irq,
7801907b	215	.set_type = imx_gpio_irq_type,
1da177e4 LT	216	};
	217
	218	void __init
	219	imx_init_irq(void)
	220	{
	221	unsigned int irq;
	222
	223	DEBUG_IRQ("Initializing imx interrupts\n");
	224
	225	/* Mask all interrupts initially */
	226	IMR(0) = 0;
	227	IMR(1) = 0;
	228	IMR(2) = 0;
	229	IMR(3) = 0;
	230
	231	for (irq = 0; irq < IMX_IRQS; irq++) {
	232	set_irq_chip(irq, &imx_internal_chip);
	233	set_irq_handler(irq, do_level_IRQ);
	234	set_irq_flags(irq, IRQF_VALID);
	235	}
	236
	237	for (irq = IRQ_GPIOA(0); irq < IRQ_GPIOD(32); irq++) {
	238	set_irq_chip(irq, &imx_gpio_chip);
	239	set_irq_handler(irq, do_edge_IRQ);
	240	set_irq_flags(irq, IRQF_VALID);
	241	}
	242
	243	set_irq_chained_handler(GPIO_INT_PORTA, imx_gpioa_demux_handler);
	244	set_irq_chained_handler(GPIO_INT_PORTB, imx_gpiob_demux_handler);
	245	set_irq_chained_handler(GPIO_INT_PORTC, imx_gpioc_demux_handler);
	246	set_irq_chained_handler(GPIO_INT_PORTD, imx_gpiod_demux_handler);
	247
	248	/* Disable all interrupts initially. */
	249	/* In IMX this is done in the bootloader. */
	250	}