[mirror_ubuntu-hirsute-kernel.git] / arch / arm / mach-imx / mach-imx6q.c

/*
 * Copyright 2011-2013 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/cpu.h>
#include <linux/delay.h>
#include <linux/export.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/pm_opp.h>
#include <linux/pci.h>
#include <linux/phy.h>
#include <linux/reboot.h>
#include <linux/regmap.h>
#include <linux/micrel_phy.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/system_misc.h>

#include "common.h"
#include "cpuidle.h"
#include "hardware.h"

/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
static int ksz9021rn_phy_fixup(struct phy_device *phydev)
{
	if (IS_BUILTIN(CONFIG_PHYLIB)) {
		/* min rx data delay */
		phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
			0x8000 | MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW);
		phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000);

		/* max rx/tx clock delay, min rx/tx control delay */
		phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
			0x8000 | MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW);
		phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xf0f0);
		phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
			MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW);
	}

	return 0;
}

static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val)
{
	phy_write(dev, 0x0d, device);
	phy_write(dev, 0x0e, reg);
	phy_write(dev, 0x0d, (1 << 14) | device);
	phy_write(dev, 0x0e, val);
}

static int ksz9031rn_phy_fixup(struct phy_device *dev)
{
	/*
	 * min rx data delay, max rx/tx clock delay,
	 * min rx/tx control delay
	 */
	mmd_write_reg(dev, 2, 4, 0);
	mmd_write_reg(dev, 2, 5, 0);
	mmd_write_reg(dev, 2, 8, 0x003ff);

	return 0;
}

/*
 * fixup for PLX PEX8909 bridge to configure GPIO1-7 as output High
 * as they are used for slots1-7 PERST#
 */
static void ventana_pciesw_early_fixup(struct pci_dev *dev)
{
	u32 dw;

	if (!of_machine_is_compatible("gw,ventana"))
		return;

	if (dev->devfn != 0)
		return;

	pci_read_config_dword(dev, 0x62c, &dw);
	dw |= 0xaaa8; // GPIO1-7 outputs
	pci_write_config_dword(dev, 0x62c, dw);

	pci_read_config_dword(dev, 0x644, &dw);
	dw |= 0xfe;   // GPIO1-7 output high
	pci_write_config_dword(dev, 0x644, dw);

	msleep(100);
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609, ventana_pciesw_early_fixup);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8606, ventana_pciesw_early_fixup);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8604, ventana_pciesw_early_fixup);

static int ar8031_phy_fixup(struct phy_device *dev)
{
	u16 val;

	/* To enable AR8031 output a 125MHz clk from CLK_25M */
	phy_write(dev, 0xd, 0x7);
	phy_write(dev, 0xe, 0x8016);
	phy_write(dev, 0xd, 0x4007);

	val = phy_read(dev, 0xe);
	val &= 0xffe3;
	val |= 0x18;
	phy_write(dev, 0xe, val);

	/* introduce tx clock delay */
	phy_write(dev, 0x1d, 0x5);
	val = phy_read(dev, 0x1e);
	val |= 0x0100;
	phy_write(dev, 0x1e, val);

	return 0;
}

#define PHY_ID_AR8031	0x004dd074

static int ar8035_phy_fixup(struct phy_device *dev)
{
	u16 val;

	/* Ar803x phy SmartEEE feature cause link status generates glitch,
	 * which cause ethernet link down/up issue, so disable SmartEEE
	 */
	phy_write(dev, 0xd, 0x3);
	phy_write(dev, 0xe, 0x805d);
	phy_write(dev, 0xd, 0x4003);

	val = phy_read(dev, 0xe);
	phy_write(dev, 0xe, val & ~(1 << 8));

	/*
	 * Enable 125MHz clock from CLK_25M on the AR8031.  This
	 * is fed in to the IMX6 on the ENET_REF_CLK (V22) pad.
	 * Also, introduce a tx clock delay.
	 *
	 * This is the same as is the AR8031 fixup.
	 */
	ar8031_phy_fixup(dev);

	/*check phy power*/
	val = phy_read(dev, 0x0);
	if (val & BMCR_PDOWN)
		phy_write(dev, 0x0, val & ~BMCR_PDOWN);

	return 0;
}

#define PHY_ID_AR8035 0x004dd072

static void __init imx6q_enet_phy_init(void)
{
	if (IS_BUILTIN(CONFIG_PHYLIB)) {
		phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
				ksz9021rn_phy_fixup);
		phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK,
				ksz9031rn_phy_fixup);
		phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffef,
				ar8031_phy_fixup);
		phy_register_fixup_for_uid(PHY_ID_AR8035, 0xffffffef,
				ar8035_phy_fixup);
	}
}

static void __init imx6q_1588_init(void)
{
	struct device_node *np;
	struct clk *ptp_clk;
	struct clk *enet_ref;
	struct regmap *gpr;
	u32 clksel;

	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-fec");
	if (!np) {
		pr_warn("%s: failed to find fec node\n", __func__);
		return;
	}

	ptp_clk = of_clk_get(np, 2);
	if (IS_ERR(ptp_clk)) {
		pr_warn("%s: failed to get ptp clock\n", __func__);
		goto put_node;
	}

	enet_ref = clk_get_sys(NULL, "enet_ref");
	if (IS_ERR(enet_ref)) {
		pr_warn("%s: failed to get enet clock\n", __func__);
		goto put_ptp_clk;
	}

	/*
	 * If enet_ref from ANATOP/CCM is the PTP clock source, we need to
	 * set bit IOMUXC_GPR1[21].  Or the PTP clock must be from pad
	 * (external OSC), and we need to clear the bit.
	 */
	clksel = clk_is_match(ptp_clk, enet_ref) ?
				IMX6Q_GPR1_ENET_CLK_SEL_ANATOP :
				IMX6Q_GPR1_ENET_CLK_SEL_PAD;
	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
	if (!IS_ERR(gpr))
		regmap_update_bits(gpr, IOMUXC_GPR1,
				IMX6Q_GPR1_ENET_CLK_SEL_MASK,
				clksel);
	else
		pr_err("failed to find fsl,imx6q-iomuxc-gpr regmap\n");

	clk_put(enet_ref);
put_ptp_clk:
	clk_put(ptp_clk);
put_node:
	of_node_put(np);
}

static void __init imx6q_axi_init(void)
{
	struct regmap *gpr;
	unsigned int mask;

	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
	if (!IS_ERR(gpr)) {
		/*
		 * Enable the cacheable attribute of VPU and IPU
		 * AXI transactions.
		 */
		mask = IMX6Q_GPR4_VPU_WR_CACHE_SEL |
			IMX6Q_GPR4_VPU_RD_CACHE_SEL |
			IMX6Q_GPR4_VPU_P_WR_CACHE_VAL |
			IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK |
			IMX6Q_GPR4_IPU_WR_CACHE_CTL |
			IMX6Q_GPR4_IPU_RD_CACHE_CTL;
		regmap_update_bits(gpr, IOMUXC_GPR4, mask, mask);

		/* Increase IPU read QoS priority */
		regmap_update_bits(gpr, IOMUXC_GPR6,
				IMX6Q_GPR6_IPU1_ID00_RD_QOS_MASK |
				IMX6Q_GPR6_IPU1_ID01_RD_QOS_MASK,
				(0xf << 16) | (0x7 << 20));
		regmap_update_bits(gpr, IOMUXC_GPR7,
				IMX6Q_GPR7_IPU2_ID00_RD_QOS_MASK |
				IMX6Q_GPR7_IPU2_ID01_RD_QOS_MASK,
				(0xf << 16) | (0x7 << 20));
	} else {
		pr_warn("failed to find fsl,imx6q-iomuxc-gpr regmap\n");
	}
}

static void __init imx6q_init_machine(void)
{
	struct device *parent;

	if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
		imx_print_silicon_rev("i.MX6QP", IMX_CHIP_REVISION_1_0);
	else
		imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
				imx_get_soc_revision());

	parent = imx_soc_device_init();
	if (parent == NULL)
		pr_warn("failed to initialize soc device\n");

	imx6q_enet_phy_init();

	of_platform_default_populate(NULL, NULL, parent);

	imx_anatop_init();
	cpu_is_imx6q() ?  imx6q_pm_init() : imx6dl_pm_init();
	imx6q_1588_init();
	imx6q_axi_init();
}

static void __init imx6q_init_late(void)
{
	/*
	 * WAIT mode is broken on imx6 Dual/Quad revision 1.0 and 1.1 so
	 * there is no point to run cpuidle on them.
	 *
	 * It does work on imx6 Solo/DualLite starting from 1.1
	 */
	if ((cpu_is_imx6q() && imx_get_soc_revision() > IMX_CHIP_REVISION_1_1) ||
	    (cpu_is_imx6dl() && imx_get_soc_revision() > IMX_CHIP_REVISION_1_0))
		imx6q_cpuidle_init();

	if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ))
		platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);
}

static void __init imx6q_map_io(void)
{
	debug_ll_io_init();
	imx_scu_map_io();
}

static void __init imx6q_init_irq(void)
{
	imx_gpc_check_dt();
	imx_init_revision_from_anatop();
	imx_init_l2cache();
	imx_src_init();
	irqchip_init();
	imx6_pm_ccm_init("fsl,imx6q-ccm");
}

static const char * const imx6q_dt_compat[] __initconst = {
	"fsl,imx6dl",
	"fsl,imx6q",
	"fsl,imx6qp",
	NULL,
};

DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)")
	.l2c_aux_val 	= 0,
	.l2c_aux_mask	= ~0,
	.smp		= smp_ops(imx_smp_ops),
	.map_io		= imx6q_map_io,
	.init_irq	= imx6q_init_irq,
	.init_machine	= imx6q_init_machine,
	.init_late      = imx6q_init_late,
	.dt_compat	= imx6q_dt_compat,
MACHINE_END
Commit	Line	Data
13eed989	1	/*
e95dddb3	2	* Copyright 2011-2013 Freescale Semiconductor, Inc.
13eed989 SG	3	* Copyright 2011 Linaro Ltd.
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
a258561d RZ	13	#include <linux/clk.h>
a258561d RZ	14	#include <linux/clkdev.h>
96574a6d	15	#include <linux/cpu.h>
4bb1d09f	16	#include <linux/delay.h>
b9d18dc3	17	#include <linux/export.h>
13eed989	18	#include <linux/init.h>
0575fb75	19	#include <linux/io.h>
13eed989	20	#include <linux/irq.h>
0529e315	21	#include <linux/irqchip.h>
13eed989	22	#include <linux/of.h>
0575fb75	23	#include <linux/of_address.h>
13eed989 SG	24	#include <linux/of_irq.h>
13eed989 SG	25	#include <linux/of_platform.h>
e4db1c74	26	#include <linux/pm_opp.h>
4bb1d09f	27	#include <linux/pci.h>
477fce49	28	#include <linux/phy.h>
7b6d864b	29	#include <linux/reboot.h>
baa64151	30	#include <linux/regmap.h>
477fce49	31	#include <linux/micrel_phy.h>
baa64151	32	#include <linux/mfd/syscon.h>
6d6fc501	33	#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
13eed989	34	#include <asm/mach/arch.h>
3e549a69	35	#include <asm/mach/map.h>
9f97da78	36	#include <asm/system_misc.h>
13eed989	37
e3372474	38	#include "common.h"
e29248c9	39	#include "cpuidle.h"
50f2de61	40	#include "hardware.h"
b9d18dc3	41
477fce49 RZ	42	/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
	43	static int ksz9021rn_phy_fixup(struct phy_device *phydev)
	44	{
9f9ba0fd	45	if (IS_BUILTIN(CONFIG_PHYLIB)) {
ef441806	46	/* min rx data delay */
dc76a1ad DN	47	phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
	48	0x8000 \| MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW);
	49	phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000);
477fce49	50
ef441806	51	/* max rx/tx clock delay, min rx/tx control delay */
dc76a1ad DN	52	phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
	53	0x8000 \| MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW);
	54	phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xf0f0);
	55	phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
	56	MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW);
ef441806	57	}
477fce49 RZ	58
	59	return 0;
	60	}
	61
dbf6719a	62	static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val)
a258561d	63	{
dbf6719a SH	64	phy_write(dev, 0x0d, device);
	65	phy_write(dev, 0x0e, reg);
	66	phy_write(dev, 0x0d, (1 << 14) \| device);
	67	phy_write(dev, 0x0e, val);
a258561d RZ	68	}
a258561d RZ	69
dbf6719a	70	static int ksz9031rn_phy_fixup(struct phy_device *dev)
071dea50	71	{
dbf6719a SH	72	/*
	73	* min rx data delay, max rx/tx clock delay,
	74	* min rx/tx control delay
	75	*/
	76	mmd_write_reg(dev, 2, 4, 0);
	77	mmd_write_reg(dev, 2, 5, 0);
	78	mmd_write_reg(dev, 2, 8, 0x003ff);
	79
	80	return 0;
071dea50 RZ	81	}
071dea50 RZ	82
4bb1d09f TH	83	/*
	84	* fixup for PLX PEX8909 bridge to configure GPIO1-7 as output High
	85	* as they are used for slots1-7 PERST#
	86	*/
	87	static void ventana_pciesw_early_fixup(struct pci_dev *dev)
	88	{
	89	u32 dw;
	90
	91	if (!of_machine_is_compatible("gw,ventana"))
	92	return;
	93
	94	if (dev->devfn != 0)
	95	return;
	96
	97	pci_read_config_dword(dev, 0x62c, &dw);
	98	dw \|= 0xaaa8; // GPIO1-7 outputs
	99	pci_write_config_dword(dev, 0x62c, dw);
	100
	101	pci_read_config_dword(dev, 0x644, &dw);
	102	dw \|= 0xfe; // GPIO1-7 output high
	103	pci_write_config_dword(dev, 0x644, dw);
	104
	105	msleep(100);
	106	}
	107	DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609, ventana_pciesw_early_fixup);
	108	DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8606, ventana_pciesw_early_fixup);
	109	DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8604, ventana_pciesw_early_fixup);
	110
12da4844	111	static int ar8031_phy_fixup(struct phy_device *dev)
e7eccc7e	112	{
12da4844 SH	113	u16 val;
	114
	115	/* To enable AR8031 output a 125MHz clk from CLK_25M */
	116	phy_write(dev, 0xd, 0x7);
	117	phy_write(dev, 0xe, 0x8016);
	118	phy_write(dev, 0xd, 0x4007);
	119
	120	val = phy_read(dev, 0xe);
	121	val &= 0xffe3;
	122	val \|= 0x18;
	123	phy_write(dev, 0xe, val);
	124
	125	/* introduce tx clock delay */
	126	phy_write(dev, 0x1d, 0x5);
	127	val = phy_read(dev, 0x1e);
	128	val \|= 0x0100;
	129	phy_write(dev, 0x1e, val);
	130
	131	return 0;
e7eccc7e NC	132	}
e7eccc7e NC	133
12da4844 SH	134	#define PHY_ID_AR8031 0x004dd074
12da4844 SH	135
208d7baf RK	136	static int ar8035_phy_fixup(struct phy_device *dev)
	137	{
	138	u16 val;
	139
	140	/* Ar803x phy SmartEEE feature cause link status generates glitch,
	141	* which cause ethernet link down/up issue, so disable SmartEEE
	142	*/
	143	phy_write(dev, 0xd, 0x3);
	144	phy_write(dev, 0xe, 0x805d);
	145	phy_write(dev, 0xd, 0x4003);
	146
	147	val = phy_read(dev, 0xe);
	148	phy_write(dev, 0xe, val & ~(1 << 8));
	149
	150	/*
	151	* Enable 125MHz clock from CLK_25M on the AR8031. This
	152	* is fed in to the IMX6 on the ENET_REF_CLK (V22) pad.
	153	* Also, introduce a tx clock delay.
	154	*
	155	* This is the same as is the AR8031 fixup.
	156	*/
	157	ar8031_phy_fixup(dev);
	158
	159	/check phy power/
	160	val = phy_read(dev, 0x0);
	161	if (val & BMCR_PDOWN)
	162	phy_write(dev, 0x0, val & ~BMCR_PDOWN);
	163
	164	return 0;
	165	}
	166
	167	#define PHY_ID_AR8035 0x004dd072
	168
14078291	169	static void __init imx6q_enet_phy_init(void)
e7eccc7e	170	{
14078291	171	if (IS_BUILTIN(CONFIG_PHYLIB)) {
ef441806	172	phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
071dea50	173	ksz9021rn_phy_fixup);
dbf6719a SH	174	phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK,
dbf6719a SH	175	ksz9031rn_phy_fixup);
4edd601c	176	phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffef,
12da4844	177	ar8031_phy_fixup);
208d7baf RK	178	phy_register_fixup_for_uid(PHY_ID_AR8035, 0xffffffef,
208d7baf RK	179	ar8035_phy_fixup);
14078291	180	}
e7eccc7e NC	181	}
e7eccc7e NC	182
d6e0d9fc FL	183	static void __init imx6q_1588_init(void)
d6e0d9fc FL	184	{
810c0ca8 SG	185	struct device_node *np;
	186	struct clk *ptp_clk;
	187	struct clk *enet_ref;
d6e0d9fc	188	struct regmap *gpr;
810c0ca8	189	u32 clksel;
d6e0d9fc	190
810c0ca8 SG	191	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-fec");
	192	if (!np) {
	193	pr_warn("%s: failed to find fec node\n", __func__);
	194	return;
	195	}
	196
	197	ptp_clk = of_clk_get(np, 2);
	198	if (IS_ERR(ptp_clk)) {
	199	pr_warn("%s: failed to get ptp clock\n", __func__);
	200	goto put_node;
	201	}
	202
	203	enet_ref = clk_get_sys(NULL, "enet_ref");
	204	if (IS_ERR(enet_ref)) {
	205	pr_warn("%s: failed to get enet clock\n", __func__);
	206	goto put_ptp_clk;
	207	}
	208
	209	/*
	210	* If enet_ref from ANATOP/CCM is the PTP clock source, we need to
	211	* set bit IOMUXC_GPR1[21]. Or the PTP clock must be from pad
	212	* (external OSC), and we need to clear the bit.
	213	*/
a51139fd SG	214	clksel = clk_is_match(ptp_clk, enet_ref) ?
	215	IMX6Q_GPR1_ENET_CLK_SEL_ANATOP :
	216	IMX6Q_GPR1_ENET_CLK_SEL_PAD;
d6e0d9fc FL	217	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
d6e0d9fc FL	218	if (!IS_ERR(gpr))
6d6fc501 PZ	219	regmap_update_bits(gpr, IOMUXC_GPR1,
6d6fc501 PZ	220	IMX6Q_GPR1_ENET_CLK_SEL_MASK,
810c0ca8	221	clksel);
d6e0d9fc	222	else
ac4bbb45	223	pr_err("failed to find fsl,imx6q-iomuxc-gpr regmap\n");
d6e0d9fc	224
810c0ca8 SG	225	clk_put(enet_ref);
	226	put_ptp_clk:
	227	clk_put(ptp_clk);
	228	put_node:
	229	of_node_put(np);
d6e0d9fc	230	}
396bf1c2	231
7ea653ef PZ	232	static void __init imx6q_axi_init(void)
	233	{
	234	struct regmap *gpr;
	235	unsigned int mask;
	236
	237	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
	238	if (!IS_ERR(gpr)) {
	239	/*
	240	* Enable the cacheable attribute of VPU and IPU
	241	* AXI transactions.
	242	*/
	243	mask = IMX6Q_GPR4_VPU_WR_CACHE_SEL \|
	244	IMX6Q_GPR4_VPU_RD_CACHE_SEL \|
	245	IMX6Q_GPR4_VPU_P_WR_CACHE_VAL \|
	246	IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK \|
	247	IMX6Q_GPR4_IPU_WR_CACHE_CTL \|
	248	IMX6Q_GPR4_IPU_RD_CACHE_CTL;
	249	regmap_update_bits(gpr, IOMUXC_GPR4, mask, mask);
	250
	251	/* Increase IPU read QoS priority */
	252	regmap_update_bits(gpr, IOMUXC_GPR6,
	253	IMX6Q_GPR6_IPU1_ID00_RD_QOS_MASK \|
	254	IMX6Q_GPR6_IPU1_ID01_RD_QOS_MASK,
	255	(0xf << 16) \| (0x7 << 20));
	256	regmap_update_bits(gpr, IOMUXC_GPR7,
	257	IMX6Q_GPR7_IPU2_ID00_RD_QOS_MASK \|
	258	IMX6Q_GPR7_IPU2_ID01_RD_QOS_MASK,
	259	(0xf << 16) \| (0x7 << 20));
	260	} else {
	261	pr_warn("failed to find fsl,imx6q-iomuxc-gpr regmap\n");
	262	}
	263	}
	264
13eed989 SG	265	static void __init imx6q_init_machine(void)
13eed989 SG	266	{
a2887546 SG	267	struct device *parent;
a2887546 SG	268
c5a890a4 BP	269	if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
	270	imx_print_silicon_rev("i.MX6QP", IMX_CHIP_REVISION_1_0);
	271	else
	272	imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
	273	imx_get_soc_revision());
4d9d18a5	274
a2887546 SG	275	parent = imx_soc_device_init();
	276	if (parent == NULL)
	277	pr_warn("failed to initialize soc device\n");
	278
14078291	279	imx6q_enet_phy_init();
477fce49	280
435ebcbc	281	of_platform_default_populate(NULL, NULL, parent);
13eed989	282
e95dddb3	283	imx_anatop_init();
df595746	284	cpu_is_imx6q() ? imx6q_pm_init() : imx6dl_pm_init();
d6e0d9fc	285	imx6q_1588_init();
7ea653ef	286	imx6q_axi_init();
13eed989 SG	287	}
13eed989 SG	288
b9d18dc3 RL	289	static void __init imx6q_init_late(void)
b9d18dc3 RL	290	{
e5f9dec8	291	/*
6879452a LC	292	* WAIT mode is broken on imx6 Dual/Quad revision 1.0 and 1.1 so
	293	* there is no point to run cpuidle on them.
	294	*
	295	* It does work on imx6 Solo/DualLite starting from 1.1
e5f9dec8	296	*/
6879452a LC	297	if ((cpu_is_imx6q() && imx_get_soc_revision() > IMX_CHIP_REVISION_1_1) \|\|
6879452a LC	298	(cpu_is_imx6dl() && imx_get_soc_revision() > IMX_CHIP_REVISION_1_0))
e5f9dec8	299	imx6q_cpuidle_init();
96574a6d	300
8e2b04b0 FE	301	if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ))
8e2b04b0 FE	302	platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);
b9d18dc3 RL	303	}
b9d18dc3 RL	304
13eed989 SG	305	static void __init imx6q_map_io(void)
13eed989 SG	306	{
3e549a69	307	debug_ll_io_init();
13eed989 SG	308	imx_scu_map_io();
	309	}
	310
13eed989 SG	311	static void __init imx6q_init_irq(void)
13eed989 SG	312	{
14517564	313	imx_gpc_check_dt();
f1c6f314	314	imx_init_revision_from_anatop();
e6a07569	315	imx_init_l2cache();
13eed989	316	imx_src_init();
0529e315	317	irqchip_init();
35e2916f	318	imx6_pm_ccm_init("fsl,imx6q-ccm");
13eed989 SG	319	}
13eed989 SG	320
8756dd92	321	static const char * const imx6q_dt_compat[] __initconst = {
3c03a2fe	322	"fsl,imx6dl",
3f8976d9	323	"fsl,imx6q",
c5a890a4	324	"fsl,imx6qp",
13eed989 SG	325	NULL,
	326	};
	327
3c03a2fe	328	DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)")
510aca64 AS	329	.l2c_aux_val = 0,
510aca64 AS	330	.l2c_aux_mask = ~0,
e4f2d979	331	.smp = smp_ops(imx_smp_ops),
13eed989 SG	332	.map_io = imx6q_map_io,
13eed989 SG	333	.init_irq = imx6q_init_irq,
13eed989	334	.init_machine = imx6q_init_machine,
b9d18dc3	335	.init_late = imx6q_init_late,
13eed989 SG	336	.dt_compat = imx6q_dt_compat,
13eed989 SG	337	MACHINE_END