[mirror_ubuntu-hirsute-kernel.git] / arch / arm / mach-imx / mach-imx6q.c

/*
 * Copyright 2011-2013 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <linux/clocksource.h>
#include <linux/cpu.h>
#include <linux/delay.h>
#include <linux/export.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/opp.h>
#include <linux/phy.h>
#include <linux/reboot.h>
#include <linux/regmap.h>
#include <linux/micrel_phy.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/system_misc.h>

#include "common.h"
#include "cpuidle.h"
#include "hardware.h"

static u32 chip_revision;

int imx6q_revision(void)
{
	return chip_revision;
}

static void __init imx6q_init_revision(void)
{
	u32 rev = imx_anatop_get_digprog();

	switch (rev & 0xff) {
	case 0:
		chip_revision = IMX_CHIP_REVISION_1_0;
		break;
	case 1:
		chip_revision = IMX_CHIP_REVISION_1_1;
		break;
	case 2:
		chip_revision = IMX_CHIP_REVISION_1_2;
		break;
	default:
		chip_revision = IMX_CHIP_REVISION_UNKNOWN;
	}

	mxc_set_cpu_type(rev >> 16 & 0xff);
}

static void imx6q_restart(enum reboot_mode mode, const char *cmd)
{
	struct device_node *np;
	void __iomem *wdog_base;

	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt");
	wdog_base = of_iomap(np, 0);
	if (!wdog_base)
		goto soft;

	imx_src_prepare_restart();

	/* enable wdog */
	writew_relaxed(1 << 2, wdog_base);
	/* write twice to ensure the request will not get ignored */
	writew_relaxed(1 << 2, wdog_base);

	/* wait for reset to assert ... */
	mdelay(500);

	pr_err("Watchdog reset failed to assert reset\n");

	/* delay to allow the serial port to show the message */
	mdelay(50);

soft:
	/* we'll take a jump through zero as a poor second */
	soft_restart(0);
}

/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
static int ksz9021rn_phy_fixup(struct phy_device *phydev)
{
	if (IS_BUILTIN(CONFIG_PHYLIB)) {
		/* min rx data delay */
		phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
			0x8000 | MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW);
		phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000);

		/* max rx/tx clock delay, min rx/tx control delay */
		phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
			0x8000 | MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW);
		phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xf0f0);
		phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
			MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW);
	}

	return 0;
}

static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val)
{
	phy_write(dev, 0x0d, device);
	phy_write(dev, 0x0e, reg);
	phy_write(dev, 0x0d, (1 << 14) | device);
	phy_write(dev, 0x0e, val);
}

static int ksz9031rn_phy_fixup(struct phy_device *dev)
{
	/*
	 * min rx data delay, max rx/tx clock delay,
	 * min rx/tx control delay
	 */
	mmd_write_reg(dev, 2, 4, 0);
	mmd_write_reg(dev, 2, 5, 0);
	mmd_write_reg(dev, 2, 8, 0x003ff);

	return 0;
}

static int ar8031_phy_fixup(struct phy_device *dev)
{
	u16 val;

	/* To enable AR8031 output a 125MHz clk from CLK_25M */
	phy_write(dev, 0xd, 0x7);
	phy_write(dev, 0xe, 0x8016);
	phy_write(dev, 0xd, 0x4007);

	val = phy_read(dev, 0xe);
	val &= 0xffe3;
	val |= 0x18;
	phy_write(dev, 0xe, val);

	/* introduce tx clock delay */
	phy_write(dev, 0x1d, 0x5);
	val = phy_read(dev, 0x1e);
	val |= 0x0100;
	phy_write(dev, 0x1e, val);

	return 0;
}

#define PHY_ID_AR8031	0x004dd074

static void __init imx6q_enet_phy_init(void)
{
	if (IS_BUILTIN(CONFIG_PHYLIB)) {
		phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
				ksz9021rn_phy_fixup);
		phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK,
				ksz9031rn_phy_fixup);
		phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
				ar8031_phy_fixup);
	}
}

static void __init imx6q_1588_init(void)
{
	struct regmap *gpr;

	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
	if (!IS_ERR(gpr))
		regmap_update_bits(gpr, IOMUXC_GPR1,
				IMX6Q_GPR1_ENET_CLK_SEL_MASK,
				IMX6Q_GPR1_ENET_CLK_SEL_ANATOP);
	else
		pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");

}

static void __init imx6q_init_machine(void)
{
	imx6q_enet_phy_init();

	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);

	imx_anatop_init();
	imx6q_pm_init();
	imx6q_1588_init();
}

#define OCOTP_CFG3			0x440
#define OCOTP_CFG3_SPEED_SHIFT		16
#define OCOTP_CFG3_SPEED_1P2GHZ		0x3

static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev)
{
	struct device_node *np;
	void __iomem *base;
	u32 val;

	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
	if (!np) {
		pr_warn("failed to find ocotp node\n");
		return;
	}

	base = of_iomap(np, 0);
	if (!base) {
		pr_warn("failed to map ocotp\n");
		goto put_node;
	}

	val = readl_relaxed(base + OCOTP_CFG3);
	val >>= OCOTP_CFG3_SPEED_SHIFT;
	if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ)
		if (opp_disable(cpu_dev, 1200000000))
			pr_warn("failed to disable 1.2 GHz OPP\n");

put_node:
	of_node_put(np);
}

static void __init imx6q_opp_init(void)
{
	struct device_node *np;
	struct device *cpu_dev = get_cpu_device(0);

	if (!cpu_dev) {
		pr_warn("failed to get cpu0 device\n");
		return;
	}
	np = of_node_get(cpu_dev->of_node);
	if (!np) {
		pr_warn("failed to find cpu0 node\n");
		return;
	}

	if (of_init_opp_table(cpu_dev)) {
		pr_warn("failed to init OPP table\n");
		goto put_node;
	}

	imx6q_opp_check_1p2ghz(cpu_dev);

put_node:
	of_node_put(np);
}

static struct platform_device imx6q_cpufreq_pdev = {
	.name = "imx6q-cpufreq",
};

static void __init imx6q_init_late(void)
{
	/*
	 * WAIT mode is broken on TO 1.0 and 1.1, so there is no point
	 * to run cpuidle on them.
	 */
	if (imx6q_revision() > IMX_CHIP_REVISION_1_1)
		imx6q_cpuidle_init();

	if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {
		imx6q_opp_init();
		platform_device_register(&imx6q_cpufreq_pdev);
	}
}

static void __init imx6q_map_io(void)
{
	debug_ll_io_init();
	imx_scu_map_io();
}

static void __init imx6q_init_irq(void)
{
	imx6q_init_revision();
	imx_init_l2cache();
	imx_src_init();
	imx_gpc_init();
	irqchip_init();
}

static void __init imx6q_timer_init(void)
{
	of_clk_init(NULL);
	clocksource_of_init();
	imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
			      imx6q_revision());
}

static const char *imx6q_dt_compat[] __initdata = {
	"fsl,imx6dl",
	"fsl,imx6q",
	NULL,
};

DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)")
	.smp		= smp_ops(imx_smp_ops),
	.map_io		= imx6q_map_io,
	.init_irq	= imx6q_init_irq,
	.init_time	= imx6q_timer_init,
	.init_machine	= imx6q_init_machine,
	.init_late      = imx6q_init_late,
	.dt_compat	= imx6q_dt_compat,
	.restart	= imx6q_restart,
MACHINE_END
Commit	Line	Data
13eed989	1	/*
e95dddb3	2	* Copyright 2011-2013 Freescale Semiconductor, Inc.
13eed989 SG	3	* Copyright 2011 Linaro Ltd.
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
a258561d	13	#include <linux/clk.h>
53bb71da	14	#include <linux/clk-provider.h>
a258561d	15	#include <linux/clkdev.h>
da4a686a	16	#include <linux/clocksource.h>
96574a6d	17	#include <linux/cpu.h>
0575fb75	18	#include <linux/delay.h>
b9d18dc3	19	#include <linux/export.h>
13eed989	20	#include <linux/init.h>
0575fb75	21	#include <linux/io.h>
13eed989	22	#include <linux/irq.h>
0529e315	23	#include <linux/irqchip.h>
13eed989	24	#include <linux/of.h>
0575fb75	25	#include <linux/of_address.h>
13eed989 SG	26	#include <linux/of_irq.h>
13eed989 SG	27	#include <linux/of_platform.h>
96574a6d	28	#include <linux/opp.h>
477fce49	29	#include <linux/phy.h>
7b6d864b	30	#include <linux/reboot.h>
baa64151	31	#include <linux/regmap.h>
477fce49	32	#include <linux/micrel_phy.h>
baa64151	33	#include <linux/mfd/syscon.h>
6d6fc501	34	#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
13eed989	35	#include <asm/mach/arch.h>
3e549a69	36	#include <asm/mach/map.h>
9f97da78	37	#include <asm/system_misc.h>
13eed989	38
e3372474	39	#include "common.h"
e29248c9	40	#include "cpuidle.h"
50f2de61	41	#include "hardware.h"
b9d18dc3	42
3c03a2fe	43	static u32 chip_revision;
b29b3e6f	44
b1a3582d	45	int imx6q_revision(void)
b29b3e6f	46	{
3c03a2fe SG	47	return chip_revision;
3c03a2fe SG	48	}
b29b3e6f	49
3c03a2fe SG	50	static void __init imx6q_init_revision(void)
	51	{
	52	u32 rev = imx_anatop_get_digprog();
b29b3e6f SG	53
	54	switch (rev & 0xff) {
	55	case 0:
3c03a2fe SG	56	chip_revision = IMX_CHIP_REVISION_1_0;
3c03a2fe SG	57	break;
b29b3e6f	58	case 1:
3c03a2fe SG	59	chip_revision = IMX_CHIP_REVISION_1_1;
3c03a2fe SG	60	break;
b29b3e6f	61	case 2:
3c03a2fe SG	62	chip_revision = IMX_CHIP_REVISION_1_2;
3c03a2fe SG	63	break;
b29b3e6f	64	default:
3c03a2fe	65	chip_revision = IMX_CHIP_REVISION_UNKNOWN;
b29b3e6f	66	}
3c03a2fe SG	67
3c03a2fe SG	68	mxc_set_cpu_type(rev >> 16 & 0xff);
b29b3e6f SG	69	}
b29b3e6f SG	70
7b6d864b	71	static void imx6q_restart(enum reboot_mode mode, const char *cmd)
0575fb75 SG	72	{
	73	struct device_node *np;
	74	void __iomem *wdog_base;
	75
	76	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt");
	77	wdog_base = of_iomap(np, 0);
	78	if (!wdog_base)
	79	goto soft;
	80
	81	imx_src_prepare_restart();
	82
	83	/* enable wdog */
	84	writew_relaxed(1 << 2, wdog_base);
	85	/* write twice to ensure the request will not get ignored */
	86	writew_relaxed(1 << 2, wdog_base);
	87
	88	/* wait for reset to assert ... */
	89	mdelay(500);
	90
	91	pr_err("Watchdog reset failed to assert reset\n");
	92
	93	/* delay to allow the serial port to show the message */
	94	mdelay(50);
	95
	96	soft:
	97	/* we'll take a jump through zero as a poor second */
	98	soft_restart(0);
	99	}
	100
477fce49 RZ	101	/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
	102	static int ksz9021rn_phy_fixup(struct phy_device *phydev)
	103	{
9f9ba0fd	104	if (IS_BUILTIN(CONFIG_PHYLIB)) {
ef441806	105	/* min rx data delay */
dc76a1ad DN	106	phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
	107	0x8000 \| MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW);
	108	phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000);
477fce49	109
ef441806	110	/* max rx/tx clock delay, min rx/tx control delay */
dc76a1ad DN	111	phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
	112	0x8000 \| MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW);
	113	phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xf0f0);
	114	phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
	115	MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW);
ef441806	116	}
477fce49 RZ	117
	118	return 0;
	119	}
	120
dbf6719a	121	static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val)
a258561d	122	{
dbf6719a SH	123	phy_write(dev, 0x0d, device);
	124	phy_write(dev, 0x0e, reg);
	125	phy_write(dev, 0x0d, (1 << 14) \| device);
	126	phy_write(dev, 0x0e, val);
a258561d RZ	127	}
a258561d RZ	128
dbf6719a	129	static int ksz9031rn_phy_fixup(struct phy_device *dev)
071dea50	130	{
dbf6719a SH	131	/*
	132	* min rx data delay, max rx/tx clock delay,
	133	* min rx/tx control delay
	134	*/
	135	mmd_write_reg(dev, 2, 4, 0);
	136	mmd_write_reg(dev, 2, 5, 0);
	137	mmd_write_reg(dev, 2, 8, 0x003ff);
	138
	139	return 0;
071dea50 RZ	140	}
071dea50 RZ	141
12da4844	142	static int ar8031_phy_fixup(struct phy_device *dev)
e7eccc7e	143	{
12da4844 SH	144	u16 val;
	145
	146	/* To enable AR8031 output a 125MHz clk from CLK_25M */
	147	phy_write(dev, 0xd, 0x7);
	148	phy_write(dev, 0xe, 0x8016);
	149	phy_write(dev, 0xd, 0x4007);
	150
	151	val = phy_read(dev, 0xe);
	152	val &= 0xffe3;
	153	val \|= 0x18;
	154	phy_write(dev, 0xe, val);
	155
	156	/* introduce tx clock delay */
	157	phy_write(dev, 0x1d, 0x5);
	158	val = phy_read(dev, 0x1e);
	159	val \|= 0x0100;
	160	phy_write(dev, 0x1e, val);
	161
	162	return 0;
e7eccc7e NC	163	}
e7eccc7e NC	164
12da4844 SH	165	#define PHY_ID_AR8031 0x004dd074
12da4844 SH	166
14078291	167	static void __init imx6q_enet_phy_init(void)
e7eccc7e	168	{
14078291	169	if (IS_BUILTIN(CONFIG_PHYLIB)) {
ef441806	170	phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
071dea50	171	ksz9021rn_phy_fixup);
dbf6719a SH	172	phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK,
dbf6719a SH	173	ksz9031rn_phy_fixup);
12da4844 SH	174	phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
12da4844 SH	175	ar8031_phy_fixup);
14078291	176	}
e7eccc7e NC	177	}
e7eccc7e NC	178
d6e0d9fc FL	179	static void __init imx6q_1588_init(void)
	180	{
	181	struct regmap *gpr;
	182
	183	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
	184	if (!IS_ERR(gpr))
6d6fc501 PZ	185	regmap_update_bits(gpr, IOMUXC_GPR1,
	186	IMX6Q_GPR1_ENET_CLK_SEL_MASK,
	187	IMX6Q_GPR1_ENET_CLK_SEL_ANATOP);
d6e0d9fc FL	188	else
	189	pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
	190
	191	}
396bf1c2	192
13eed989 SG	193	static void __init imx6q_init_machine(void)
13eed989 SG	194	{
14078291	195	imx6q_enet_phy_init();
477fce49	196
13eed989 SG	197	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
13eed989 SG	198
e95dddb3	199	imx_anatop_init();
13eed989	200	imx6q_pm_init();
d6e0d9fc	201	imx6q_1588_init();
13eed989 SG	202	}
13eed989 SG	203
96574a6d SG	204	#define OCOTP_CFG3 0x440
	205	#define OCOTP_CFG3_SPEED_SHIFT 16
	206	#define OCOTP_CFG3_SPEED_1P2GHZ 0x3
	207
	208	static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev)
	209	{
	210	struct device_node *np;
	211	void __iomem *base;
	212	u32 val;
	213
	214	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
	215	if (!np) {
	216	pr_warn("failed to find ocotp node\n");
	217	return;
	218	}
	219
	220	base = of_iomap(np, 0);
	221	if (!base) {
	222	pr_warn("failed to map ocotp\n");
	223	goto put_node;
	224	}
	225
	226	val = readl_relaxed(base + OCOTP_CFG3);
	227	val >>= OCOTP_CFG3_SPEED_SHIFT;
	228	if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ)
	229	if (opp_disable(cpu_dev, 1200000000))
	230	pr_warn("failed to disable 1.2 GHz OPP\n");
	231
	232	put_node:
	233	of_node_put(np);
	234	}
	235
b494b48d	236	static void __init imx6q_opp_init(void)
96574a6d SG	237	{
96574a6d SG	238	struct device_node *np;
b494b48d	239	struct device *cpu_dev = get_cpu_device(0);
96574a6d	240
b494b48d SH	241	if (!cpu_dev) {
	242	pr_warn("failed to get cpu0 device\n");
	243	return;
	244	}
cdc58d60	245	np = of_node_get(cpu_dev->of_node);
96574a6d SG	246	if (!np) {
	247	pr_warn("failed to find cpu0 node\n");
	248	return;
	249	}
	250
96574a6d SG	251	if (of_init_opp_table(cpu_dev)) {
	252	pr_warn("failed to init OPP table\n");
	253	goto put_node;
	254	}
	255
	256	imx6q_opp_check_1p2ghz(cpu_dev);
	257
	258	put_node:
	259	of_node_put(np);
	260	}
	261
f8c11b2b	262	static struct platform_device imx6q_cpufreq_pdev = {
96574a6d SG	263	.name = "imx6q-cpufreq",
	264	};
	265
b9d18dc3 RL	266	static void __init imx6q_init_late(void)
b9d18dc3 RL	267	{
e5f9dec8 SG	268	/*
	269	* WAIT mode is broken on TO 1.0 and 1.1, so there is no point
	270	* to run cpuidle on them.
	271	*/
	272	if (imx6q_revision() > IMX_CHIP_REVISION_1_1)
	273	imx6q_cpuidle_init();
96574a6d SG	274
96574a6d SG	275	if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {
b494b48d	276	imx6q_opp_init();
96574a6d SG	277	platform_device_register(&imx6q_cpufreq_pdev);
96574a6d SG	278	}
b9d18dc3 RL	279	}
b9d18dc3 RL	280
13eed989 SG	281	static void __init imx6q_map_io(void)
13eed989 SG	282	{
3e549a69	283	debug_ll_io_init();
13eed989 SG	284	imx_scu_map_io();
	285	}
	286
13eed989 SG	287	static void __init imx6q_init_irq(void)
13eed989 SG	288	{
3c03a2fe	289	imx6q_init_revision();
e6a07569	290	imx_init_l2cache();
13eed989 SG	291	imx_src_init();
13eed989 SG	292	imx_gpc_init();
0529e315	293	irqchip_init();
13eed989 SG	294	}
	295
	296	static void __init imx6q_timer_init(void)
	297	{
53bb71da	298	of_clk_init(NULL);
da4a686a	299	clocksource_of_init();
3c03a2fe SG	300	imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
3c03a2fe SG	301	imx6q_revision());
13eed989 SG	302	}
13eed989 SG	303
13eed989	304	static const char *imx6q_dt_compat[] __initdata = {
3c03a2fe	305	"fsl,imx6dl",
3f8976d9	306	"fsl,imx6q",
13eed989 SG	307	NULL,
	308	};
	309
3c03a2fe	310	DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)")
e4f2d979	311	.smp = smp_ops(imx_smp_ops),
13eed989 SG	312	.map_io = imx6q_map_io,
13eed989 SG	313	.init_irq = imx6q_init_irq,
6bb27d73	314	.init_time = imx6q_timer_init,
13eed989	315	.init_machine = imx6q_init_machine,
b9d18dc3	316	.init_late = imx6q_init_late,
13eed989	317	.dt_compat = imx6q_dt_compat,
0575fb75	318	.restart = imx6q_restart,
13eed989	319	MACHINE_END