[mirror_ubuntu-jammy-kernel.git] / arch / arm / mach-imx / mach-imx6ul.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2015 Freescale Semiconductor, Inc.
 */
#include <linux/irqchip.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include <linux/micrel_phy.h>
#include <linux/of_platform.h>
#include <linux/phy.h>
#include <linux/regmap.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>

#include "common.h"
#include "cpuidle.h"

static void __init imx6ul_enet_clk_init(void)
{
	struct regmap *gpr;

	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
	if (!IS_ERR(gpr))
		regmap_update_bits(gpr, IOMUXC_GPR1, IMX6UL_GPR1_ENET_CLK_DIR,
				   IMX6UL_GPR1_ENET_CLK_OUTPUT);
	else
		pr_err("failed to find fsl,imx6ul-iomux-gpr regmap\n");

}

static int ksz8081_phy_fixup(struct phy_device *dev)
{
	if (dev && dev->interface == PHY_INTERFACE_MODE_MII) {
		phy_write(dev, 0x1f, 0x8110);
		phy_write(dev, 0x16, 0x201);
	} else if (dev && dev->interface == PHY_INTERFACE_MODE_RMII) {
		phy_write(dev, 0x1f, 0x8190);
		phy_write(dev, 0x16, 0x202);
	}

	return 0;
}

static void __init imx6ul_enet_phy_init(void)
{
	if (IS_BUILTIN(CONFIG_PHYLIB))
		phy_register_fixup_for_uid(PHY_ID_KSZ8081, MICREL_PHY_ID_MASK,
					   ksz8081_phy_fixup);
}

static inline void imx6ul_enet_init(void)
{
	imx6ul_enet_clk_init();
	imx6ul_enet_phy_init();
}

static void __init imx6ul_init_machine(void)
{
	struct device *parent;

	parent = imx_soc_device_init();
	if (parent == NULL)
		pr_warn("failed to initialize soc device\n");

	of_platform_default_populate(NULL, NULL, parent);
	imx6ul_enet_init();
	imx_anatop_init();
	imx6ul_pm_init();
}

static void __init imx6ul_init_irq(void)
{
	imx_init_revision_from_anatop();
	imx_src_init();
	irqchip_init();
	imx6_pm_ccm_init("fsl,imx6ul-ccm");
}

static void __init imx6ul_init_late(void)
{
	imx6sx_cpuidle_init();

	if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ))
		platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);
}

static const char * const imx6ul_dt_compat[] __initconst = {
	"fsl,imx6ul",
	"fsl,imx6ull",
	NULL,
};

DT_MACHINE_START(IMX6UL, "Freescale i.MX6 Ultralite (Device Tree)")
	.init_irq	= imx6ul_init_irq,
	.init_machine	= imx6ul_init_machine,
	.init_late	= imx6ul_init_late,
	.dt_compat	= imx6ul_dt_compat,
MACHINE_END
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
022d0716 FL	2	/*
022d0716 FL	3	* Copyright (C) 2015 Freescale Semiconductor, Inc.
022d0716 FL	4	*/
022d0716 FL	5	#include <linux/irqchip.h>
709bc065 FD	6	#include <linux/mfd/syscon.h>
	7	#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
	8	#include <linux/micrel_phy.h>
022d0716	9	#include <linux/of_platform.h>
709bc065 FD	10	#include <linux/phy.h>
709bc065 FD	11	#include <linux/regmap.h>
022d0716 FL	12	#include <asm/mach/arch.h>
	13	#include <asm/mach/map.h>
	14
	15	#include "common.h"
547e8f52	16	#include "cpuidle.h"
022d0716	17
709bc065 FD	18	static void __init imx6ul_enet_clk_init(void)
	19	{
	20	struct regmap *gpr;
	21
	22	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
	23	if (!IS_ERR(gpr))
	24	regmap_update_bits(gpr, IOMUXC_GPR1, IMX6UL_GPR1_ENET_CLK_DIR,
	25	IMX6UL_GPR1_ENET_CLK_OUTPUT);
	26	else
	27	pr_err("failed to find fsl,imx6ul-iomux-gpr regmap\n");
	28
	29	}
	30
	31	static int ksz8081_phy_fixup(struct phy_device *dev)
	32	{
	33	if (dev && dev->interface == PHY_INTERFACE_MODE_MII) {
	34	phy_write(dev, 0x1f, 0x8110);
	35	phy_write(dev, 0x16, 0x201);
	36	} else if (dev && dev->interface == PHY_INTERFACE_MODE_RMII) {
	37	phy_write(dev, 0x1f, 0x8190);
	38	phy_write(dev, 0x16, 0x202);
	39	}
	40
	41	return 0;
	42	}
	43
	44	static void __init imx6ul_enet_phy_init(void)
	45	{
6be4b0da	46	if (IS_BUILTIN(CONFIG_PHYLIB))
20c15226	47	phy_register_fixup_for_uid(PHY_ID_KSZ8081, MICREL_PHY_ID_MASK,
6be4b0da	48	ksz8081_phy_fixup);
709bc065 FD	49	}
	50
	51	static inline void imx6ul_enet_init(void)
	52	{
	53	imx6ul_enet_clk_init();
	54	imx6ul_enet_phy_init();
	55	}
	56
022d0716 FL	57	static void __init imx6ul_init_machine(void)
	58	{
	59	struct device *parent;
	60
	61	parent = imx_soc_device_init();
	62	if (parent == NULL)
	63	pr_warn("failed to initialize soc device\n");
	64
cfee6b58	65	of_platform_default_populate(NULL, NULL, parent);
709bc065	66	imx6ul_enet_init();
022d0716	67	imx_anatop_init();
ee4a5f83	68	imx6ul_pm_init();
022d0716 FL	69	}
	70
	71	static void __init imx6ul_init_irq(void)
	72	{
	73	imx_init_revision_from_anatop();
	74	imx_src_init();
	75	irqchip_init();
ee4a5f83	76	imx6_pm_ccm_init("fsl,imx6ul-ccm");
022d0716 FL	77	}
022d0716 FL	78
7f730819 BP	79	static void __init imx6ul_init_late(void)
7f730819 BP	80	{
547e8f52 AH	81	imx6sx_cpuidle_init();
547e8f52 AH	82
7f730819 BP	83	if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ))
	84	platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);
	85	}
	86
5d484175	87	static const char * const imx6ul_dt_compat[] __initconst = {
022d0716	88	"fsl,imx6ul",
75b832fe	89	"fsl,imx6ull",
022d0716 FL	90	NULL,
	91	};
	92
	93	DT_MACHINE_START(IMX6UL, "Freescale i.MX6 Ultralite (Device Tree)")
	94	.init_irq = imx6ul_init_irq,
	95	.init_machine = imx6ul_init_machine,
7f730819	96	.init_late = imx6ul_init_late,
022d0716 FL	97	.dt_compat = imx6ul_dt_compat,
022d0716 FL	98	MACHINE_END