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Commit | Line | Data |
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80eedae6 JB |
1 | /* |
2 | * Copyright (C) 2000 Deep Blue Solutions Ltd | |
3 | * Copyright (C) 2002 Shane Nay (shane@minirl.com) | |
4 | * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
80eedae6 | 15 | */ |
2f8163ba | 16 | #include <linux/gpio.h> |
80eedae6 JB |
17 | #include <linux/platform_device.h> |
18 | #include <linux/mtd/mtd.h> | |
19 | #include <linux/mtd/map.h> | |
20 | #include <linux/mtd/partitions.h> | |
21 | #include <linux/mtd/physmap.h> | |
c981214a | 22 | #include <linux/i2c.h> |
60c24dc7 | 23 | #include <linux/irq.h> |
a09e64fb RK |
24 | #include <mach/common.h> |
25 | #include <mach/hardware.h> | |
80eedae6 JB |
26 | #include <asm/mach-types.h> |
27 | #include <asm/mach/arch.h> | |
28 | #include <asm/mach/time.h> | |
29 | #include <asm/mach/map.h> | |
e835d88e | 30 | #include <mach/iomux-mx27.h> |
80eedae6 | 31 | |
0e7a29a8 | 32 | #include "devices-imx27.h" |
7e90534a | 33 | |
1faeaab2 UKK |
34 | /* |
35 | * Base address of PBC controller, CS4 | |
36 | */ | |
37 | #define PBC_BASE_ADDRESS 0xf4300000 | |
38 | #define PBC_REG_ADDR(offset) (void __force __iomem *) \ | |
39 | (PBC_BASE_ADDRESS + (offset)) | |
40 | ||
41 | /* When the PBC address connection is fixed in h/w, defined as 1 */ | |
42 | #define PBC_ADDR_SH 0 | |
43 | ||
44 | /* Offsets for the PBC Controller register */ | |
45 | /* | |
46 | * PBC Board version register offset | |
47 | */ | |
48 | #define PBC_VERSION_REG PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH) | |
49 | /* | |
50 | * PBC Board control register 1 set address. | |
51 | */ | |
52 | #define PBC_BCTRL1_SET_REG PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH) | |
53 | /* | |
54 | * PBC Board control register 1 clear address. | |
55 | */ | |
56 | #define PBC_BCTRL1_CLEAR_REG PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH) | |
57 | ||
58 | /* PBC Board Control Register 1 bit definitions */ | |
59 | #define PBC_BCTRL1_LCDON 0x0800 /* Enable the LCD */ | |
60 | ||
61 | /* to determine the correct external crystal reference */ | |
62 | #define CKIH_27MHZ_BIT_SET (1 << 3) | |
63 | ||
6c80ee51 | 64 | static const int mx27ads_pins[] __initconst = { |
c1a6f123 | 65 | /* UART0 */ |
80eedae6 JB |
66 | PE12_PF_UART1_TXD, |
67 | PE13_PF_UART1_RXD, | |
68 | PE14_PF_UART1_CTS, | |
c1a6f123 VB |
69 | PE15_PF_UART1_RTS, |
70 | /* UART1 */ | |
80eedae6 JB |
71 | PE3_PF_UART2_CTS, |
72 | PE4_PF_UART2_RTS, | |
73 | PE6_PF_UART2_TXD, | |
c1a6f123 VB |
74 | PE7_PF_UART2_RXD, |
75 | /* UART2 */ | |
80eedae6 JB |
76 | PE8_PF_UART3_TXD, |
77 | PE9_PF_UART3_RXD, | |
78 | PE10_PF_UART3_CTS, | |
c1a6f123 VB |
79 | PE11_PF_UART3_RTS, |
80 | /* UART3 */ | |
80eedae6 JB |
81 | PB26_AF_UART4_RTS, |
82 | PB28_AF_UART4_TXD, | |
83 | PB29_AF_UART4_CTS, | |
c1a6f123 VB |
84 | PB31_AF_UART4_RXD, |
85 | /* UART4 */ | |
80eedae6 JB |
86 | PB18_AF_UART5_TXD, |
87 | PB19_AF_UART5_RXD, | |
88 | PB20_AF_UART5_CTS, | |
c1a6f123 VB |
89 | PB21_AF_UART5_RTS, |
90 | /* UART5 */ | |
80eedae6 JB |
91 | PB10_AF_UART6_TXD, |
92 | PB12_AF_UART6_CTS, | |
93 | PB11_AF_UART6_RXD, | |
c1a6f123 VB |
94 | PB13_AF_UART6_RTS, |
95 | /* FEC */ | |
80eedae6 JB |
96 | PD0_AIN_FEC_TXD0, |
97 | PD1_AIN_FEC_TXD1, | |
98 | PD2_AIN_FEC_TXD2, | |
99 | PD3_AIN_FEC_TXD3, | |
100 | PD4_AOUT_FEC_RX_ER, | |
101 | PD5_AOUT_FEC_RXD1, | |
102 | PD6_AOUT_FEC_RXD2, | |
103 | PD7_AOUT_FEC_RXD3, | |
104 | PD8_AF_FEC_MDIO, | |
105 | PD9_AIN_FEC_MDC, | |
106 | PD10_AOUT_FEC_CRS, | |
107 | PD11_AOUT_FEC_TX_CLK, | |
108 | PD12_AOUT_FEC_RXD0, | |
109 | PD13_AOUT_FEC_RX_DV, | |
ccfe30a7 | 110 | PD14_AOUT_FEC_RX_CLK, |
80eedae6 JB |
111 | PD15_AOUT_FEC_COL, |
112 | PD16_AIN_FEC_TX_ER, | |
c1a6f123 | 113 | PF23_AIN_FEC_TX_EN, |
c981214a VB |
114 | /* I2C2 */ |
115 | PC5_PF_I2C2_SDA, | |
116 | PC6_PF_I2C2_SCL, | |
11cda13d VB |
117 | /* FB */ |
118 | PA5_PF_LSCLK, | |
119 | PA6_PF_LD0, | |
120 | PA7_PF_LD1, | |
121 | PA8_PF_LD2, | |
122 | PA9_PF_LD3, | |
123 | PA10_PF_LD4, | |
124 | PA11_PF_LD5, | |
125 | PA12_PF_LD6, | |
126 | PA13_PF_LD7, | |
127 | PA14_PF_LD8, | |
128 | PA15_PF_LD9, | |
129 | PA16_PF_LD10, | |
130 | PA17_PF_LD11, | |
131 | PA18_PF_LD12, | |
132 | PA19_PF_LD13, | |
133 | PA20_PF_LD14, | |
134 | PA21_PF_LD15, | |
135 | PA22_PF_LD16, | |
136 | PA23_PF_LD17, | |
137 | PA24_PF_REV, | |
138 | PA25_PF_CLS, | |
139 | PA26_PF_PS, | |
140 | PA27_PF_SPL_SPR, | |
141 | PA28_PF_HSYNC, | |
142 | PA29_PF_VSYNC, | |
143 | PA30_PF_CONTRAST, | |
144 | PA31_PF_OE_ACD, | |
9366d8f6 VB |
145 | /* OWIRE */ |
146 | PE16_AF_OWIRE, | |
60c24dc7 VB |
147 | /* SDHC1*/ |
148 | PE18_PF_SD1_D0, | |
149 | PE19_PF_SD1_D1, | |
150 | PE20_PF_SD1_D2, | |
151 | PE21_PF_SD1_D3, | |
152 | PE22_PF_SD1_CMD, | |
153 | PE23_PF_SD1_CLK, | |
154 | /* SDHC2*/ | |
155 | PB4_PF_SD2_D0, | |
156 | PB5_PF_SD2_D1, | |
157 | PB6_PF_SD2_D2, | |
158 | PB7_PF_SD2_D3, | |
159 | PB8_PF_SD2_CMD, | |
160 | PB9_PF_SD2_CLK, | |
80eedae6 JB |
161 | }; |
162 | ||
0e7a29a8 UKK |
163 | static const struct mxc_nand_platform_data |
164 | mx27ads_nand_board_info __initconst = { | |
8d4fd258 VB |
165 | .width = 1, |
166 | .hw_ecc = 1, | |
167 | }; | |
168 | ||
c1a6f123 VB |
169 | /* ADS's NOR flash */ |
170 | static struct physmap_flash_data mx27ads_flash_data = { | |
171 | .width = 2, | |
172 | }; | |
173 | ||
174 | static struct resource mx27ads_flash_resource = { | |
175 | .start = 0xc0000000, | |
176 | .end = 0xc0000000 + 0x02000000 - 1, | |
177 | .flags = IORESOURCE_MEM, | |
178 | ||
179 | }; | |
180 | ||
181 | static struct platform_device mx27ads_nor_mtd_device = { | |
182 | .name = "physmap-flash", | |
183 | .id = 0, | |
184 | .dev = { | |
185 | .platform_data = &mx27ads_flash_data, | |
186 | }, | |
187 | .num_resources = 1, | |
188 | .resource = &mx27ads_flash_resource, | |
189 | }; | |
190 | ||
c6987159 | 191 | static const struct imxi2c_platform_data mx27ads_i2c1_data __initconst = { |
c981214a VB |
192 | .bitrate = 100000, |
193 | }; | |
194 | ||
195 | static struct i2c_board_info mx27ads_i2c_devices[] = { | |
196 | }; | |
197 | ||
11cda13d VB |
198 | void lcd_power(int on) |
199 | { | |
200 | if (on) | |
201 | __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_SET_REG); | |
202 | else | |
203 | __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG); | |
204 | } | |
205 | ||
343684ff SH |
206 | static struct imx_fb_videomode mx27ads_modes[] = { |
207 | { | |
208 | .mode = { | |
209 | .name = "Sharp-LQ035Q7", | |
210 | .refresh = 60, | |
211 | .xres = 240, | |
212 | .yres = 320, | |
213 | .pixclock = 188679, /* in ps (5.3MHz) */ | |
214 | .hsync_len = 1, | |
215 | .left_margin = 9, | |
216 | .right_margin = 16, | |
217 | .vsync_len = 1, | |
218 | .upper_margin = 7, | |
219 | .lower_margin = 9, | |
220 | }, | |
221 | .bpp = 16, | |
222 | .pcr = 0xFB008BC0, | |
223 | }, | |
224 | }; | |
11cda13d | 225 | |
ad851bff | 226 | static const struct imx_fb_platform_data mx27ads_fb_data __initconst = { |
343684ff SH |
227 | .mode = mx27ads_modes, |
228 | .num_modes = ARRAY_SIZE(mx27ads_modes), | |
11cda13d VB |
229 | |
230 | /* | |
231 | * - HSYNC active high | |
232 | * - VSYNC active high | |
233 | * - clk notenabled while idle | |
234 | * - clock inverted | |
235 | * - data not inverted | |
236 | * - data enable low active | |
237 | * - enable sharp mode | |
238 | */ | |
11cda13d VB |
239 | .pwmr = 0x00A903FF, |
240 | .lscr1 = 0x00120300, | |
241 | .dmacr = 0x00020010, | |
242 | ||
243 | .lcd_power = lcd_power, | |
244 | }; | |
245 | ||
60c24dc7 VB |
246 | static int mx27ads_sdhc1_init(struct device *dev, irq_handler_t detect_irq, |
247 | void *data) | |
248 | { | |
249 | return request_irq(IRQ_GPIOE(21), detect_irq, IRQF_TRIGGER_RISING, | |
250 | "sdhc1-card-detect", data); | |
251 | } | |
252 | ||
253 | static int mx27ads_sdhc2_init(struct device *dev, irq_handler_t detect_irq, | |
254 | void *data) | |
255 | { | |
256 | return request_irq(IRQ_GPIOB(7), detect_irq, IRQF_TRIGGER_RISING, | |
257 | "sdhc2-card-detect", data); | |
258 | } | |
259 | ||
260 | static void mx27ads_sdhc1_exit(struct device *dev, void *data) | |
261 | { | |
262 | free_irq(IRQ_GPIOE(21), data); | |
263 | } | |
264 | ||
265 | static void mx27ads_sdhc2_exit(struct device *dev, void *data) | |
266 | { | |
267 | free_irq(IRQ_GPIOB(7), data); | |
268 | } | |
269 | ||
9d3d945a | 270 | static const struct imxmmc_platform_data sdhc1_pdata __initconst = { |
60c24dc7 VB |
271 | .init = mx27ads_sdhc1_init, |
272 | .exit = mx27ads_sdhc1_exit, | |
273 | }; | |
274 | ||
9d3d945a | 275 | static const struct imxmmc_platform_data sdhc2_pdata __initconst = { |
60c24dc7 VB |
276 | .init = mx27ads_sdhc2_init, |
277 | .exit = mx27ads_sdhc2_exit, | |
278 | }; | |
279 | ||
c1a6f123 VB |
280 | static struct platform_device *platform_devices[] __initdata = { |
281 | &mx27ads_nor_mtd_device, | |
c1a6f123 | 282 | }; |
80eedae6 | 283 | |
d5dac4a6 UKK |
284 | static const struct imxuart_platform_data uart_pdata __initconst = { |
285 | .flags = IMXUART_HAVE_RTSCTS, | |
80eedae6 JB |
286 | }; |
287 | ||
288 | static void __init mx27ads_board_init(void) | |
289 | { | |
b78d8e59 SG |
290 | imx27_soc_init(); |
291 | ||
c1a6f123 VB |
292 | mxc_gpio_setup_multiple_pins(mx27ads_pins, ARRAY_SIZE(mx27ads_pins), |
293 | "mx27ads"); | |
80eedae6 | 294 | |
d5dac4a6 UKK |
295 | imx27_add_imx_uart0(&uart_pdata); |
296 | imx27_add_imx_uart1(&uart_pdata); | |
297 | imx27_add_imx_uart2(&uart_pdata); | |
298 | imx27_add_imx_uart3(&uart_pdata); | |
299 | imx27_add_imx_uart4(&uart_pdata); | |
300 | imx27_add_imx_uart5(&uart_pdata); | |
0e7a29a8 | 301 | imx27_add_mxc_nand(&mx27ads_nand_board_info); |
c981214a VB |
302 | |
303 | /* only the i2c master 1 is used on this CPU card */ | |
304 | i2c_register_board_info(1, mx27ads_i2c_devices, | |
305 | ARRAY_SIZE(mx27ads_i2c_devices)); | |
77a406da | 306 | imx27_add_imx_i2c(1, &mx27ads_i2c1_data); |
ad851bff | 307 | imx27_add_imx_fb(&mx27ads_fb_data); |
9d3d945a UKK |
308 | imx27_add_mxc_mmc(0, &sdhc1_pdata); |
309 | imx27_add_mxc_mmc(1, &sdhc2_pdata); | |
80eedae6 | 310 | |
6bd96f3c | 311 | imx27_add_fec(NULL); |
80eedae6 | 312 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); |
ae71a562 | 313 | imx27_add_mxc_w1(NULL); |
80eedae6 JB |
314 | } |
315 | ||
316 | static void __init mx27ads_timer_init(void) | |
317 | { | |
318 | unsigned long fref = 26000000; | |
319 | ||
320 | if ((__raw_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0) | |
321 | fref = 27000000; | |
322 | ||
30c730f8 | 323 | mx27_clocks_init(fref); |
80eedae6 JB |
324 | } |
325 | ||
058b7a6f | 326 | static struct sys_timer mx27ads_timer = { |
80eedae6 JB |
327 | .init = mx27ads_timer_init, |
328 | }; | |
329 | ||
330 | static struct map_desc mx27ads_io_desc[] __initdata = { | |
331 | { | |
332 | .virtual = PBC_BASE_ADDRESS, | |
3f35d1f5 | 333 | .pfn = __phys_to_pfn(MX27_CS4_BASE_ADDR), |
80eedae6 JB |
334 | .length = SZ_1M, |
335 | .type = MT_DEVICE, | |
336 | }, | |
337 | }; | |
338 | ||
058b7a6f | 339 | static void __init mx27ads_map_io(void) |
80eedae6 | 340 | { |
cd4a05f9 | 341 | mx27_map_io(); |
80eedae6 JB |
342 | iotable_init(mx27ads_io_desc, ARRAY_SIZE(mx27ads_io_desc)); |
343 | } | |
344 | ||
345 | MACHINE_START(MX27ADS, "Freescale i.MX27ADS") | |
346 | /* maintainer: Freescale Semiconductor, Inc. */ | |
3dac2196 UKK |
347 | .boot_params = MX27_PHYS_OFFSET + 0x100, |
348 | .map_io = mx27ads_map_io, | |
349 | .init_early = imx27_init_early, | |
350 | .init_irq = mx27_init_irq, | |
351 | .timer = &mx27ads_timer, | |
352 | .init_machine = mx27ads_board_init, | |
80eedae6 | 353 | MACHINE_END |