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UBUNTU: Ubuntu-4.15.0-96.97
[mirror_ubuntu-bionic-kernel.git] / arch / arm / mach-imx / mach-mx31_3ds.c
CommitLineData
1553a1ec
FE		 1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
1553a1ec
FE		 13 */
14
a2ef4562 15#include <linux/delay.h>
b7f080cf 16#include <linux/dma-mapping.h>
1553a1ec
FE		 17#include <linux/types.h>
18#include <linux/init.h>
19#include <linux/clk.h>
20#include <linux/irq.h>
135cad36 21#include <linux/gpio.h>
2b0c3677 22#include <linux/platform_device.h>
ae7a3f13
AP		 23#include <linux/mfd/mc13783.h>
24#include <linux/spi/spi.h>
e42010e0 25#include <linux/spi/l4f00242t03.h>
ae7a3f13 26#include <linux/regulator/machine.h>
1c50e672
FE		 27#include <linux/usb/otg.h>
28#include <linux/usb/ulpi.h>
1553a1ec 29
1553a1ec
FE		 30#include <asm/mach-types.h>
31#include <asm/mach/arch.h>
32#include <asm/mach/time.h>
33#include <asm/memory.h>
34#include <asm/mach/map.h>
a2ceeef5 35
3ed0bcb4 36#include "3ds_debugboard.h"
e3372474 37#include "common.h"
a2ceeef5 38#include "devices-imx31.h"
641dfe8b 39#include "ehci.h"
50f2de61 40#include "hardware.h"
267dd34c 41#include "iomux-mx3.h"
39ef6340 42#include "ulpi.h"
1553a1ec 43
11a332ad 44static int mx31_3ds_pins[] = {
153fa1d8 45 /* UART1 */
63d97667
VL		 46 MX31_PIN_CTS1__CTS1,
47 MX31_PIN_RTS1__RTS1,
48 MX31_PIN_TXD1__TXD1,
135cad36
ML		 49 MX31_PIN_RXD1__RXD1,
50 IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
e42010e0 51 /*SPI0*/
b2a08e3e
FE		 52 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_ALT1),
53 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_ALT1),
a1ac4424
AP		 54 /* SPI 1 */
55 MX31_PIN_CSPI2_SCLK__SCLK,
56 MX31_PIN_CSPI2_MOSI__MOSI,
57 MX31_PIN_CSPI2_MISO__MISO,
58 MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
59 MX31_PIN_CSPI2_SS0__SS0,
60 MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */
ae7a3f13
AP		 61 /* MC13783 IRQ */
62 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO),
a2ef4562
ML		 63 /* USB OTG reset */
64 IOMUX_MODE(MX31_PIN_USB_PWR, IOMUX_CONFIG_GPIO),
65 /* USB OTG */
66 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
67 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
68 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
69 MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
70 MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
71 MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
72 MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
73 MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
74 MX31_PIN_USBOTG_CLK__USBOTG_CLK,
75 MX31_PIN_USBOTG_DIR__USBOTG_DIR,
76 MX31_PIN_USBOTG_NXT__USBOTG_NXT,
77 MX31_PIN_USBOTG_STP__USBOTG_STP,
54c1f636
AP		 78 /*Keyboard*/
79 MX31_PIN_KEY_ROW0_KEY_ROW0,
80 MX31_PIN_KEY_ROW1_KEY_ROW1,
81 MX31_PIN_KEY_ROW2_KEY_ROW2,
82 MX31_PIN_KEY_COL0_KEY_COL0,
83 MX31_PIN_KEY_COL1_KEY_COL1,
84 MX31_PIN_KEY_COL2_KEY_COL2,
85 MX31_PIN_KEY_COL3_KEY_COL3,
0d95b75e
FE		 86 /* USB Host 2 */
87 IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
88 IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
89 IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
90 IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
91 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
92 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
93 IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT1),
94 IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT1),
95 IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT1),
96 IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT1),
97 IOMUX_MODE(MX31_PIN_IOIS16, IOMUX_CONFIG_ALT1),
98 IOMUX_MODE(MX31_PIN_PC_RW_B, IOMUX_CONFIG_ALT1),
99 /* USB Host2 reset */
100 IOMUX_MODE(MX31_PIN_USB_BYP, IOMUX_CONFIG_GPIO),
3d943024
FE		 101 /* I2C1 */
102 MX31_PIN_I2C_CLK__I2C1_SCL,
103 MX31_PIN_I2C_DAT__I2C1_SDA,
0ce88b34
AP		 104 /* SDHC1 */
105 MX31_PIN_SD1_DATA3__SD1_DATA3,
106 MX31_PIN_SD1_DATA2__SD1_DATA2,
107 MX31_PIN_SD1_DATA1__SD1_DATA1,
108 MX31_PIN_SD1_DATA0__SD1_DATA0,
109 MX31_PIN_SD1_CLK__SD1_CLK,
110 MX31_PIN_SD1_CMD__SD1_CMD,
111 MX31_PIN_GPIO3_1__GPIO3_1, /* Card detect */
112 MX31_PIN_GPIO3_0__GPIO3_0, /* OE */
e42010e0
AP		 113 /* Framebuffer */
114 MX31_PIN_LD0__LD0,
115 MX31_PIN_LD1__LD1,
116 MX31_PIN_LD2__LD2,
117 MX31_PIN_LD3__LD3,
118 MX31_PIN_LD4__LD4,
119 MX31_PIN_LD5__LD5,
120 MX31_PIN_LD6__LD6,
121 MX31_PIN_LD7__LD7,
122 MX31_PIN_LD8__LD8,
123 MX31_PIN_LD9__LD9,
124 MX31_PIN_LD10__LD10,
125 MX31_PIN_LD11__LD11,
126 MX31_PIN_LD12__LD12,
127 MX31_PIN_LD13__LD13,
128 MX31_PIN_LD14__LD14,
129 MX31_PIN_LD15__LD15,
130 MX31_PIN_LD16__LD16,
131 MX31_PIN_LD17__LD17,
132 MX31_PIN_VSYNC3__VSYNC3,
133 MX31_PIN_HSYNC__HSYNC,
134 MX31_PIN_FPSHIFT__FPSHIFT,
135 MX31_PIN_CONTRAST__CONTRAST,
5fb86e5d
PR		 136 /* SSI */
137 MX31_PIN_STXD4__STXD4,
138 MX31_PIN_SRXD4__SRXD4,
139 MX31_PIN_SCK4__SCK4,
140 MX31_PIN_SFS4__SFS4,
164f7b52
AP		 141};
142
e42010e0
AP		 143/*
144 * FB support
145 */
146static const struct fb_videomode fb_modedb[] = {
147 { /* 480x640 @ 60 Hz */
148 .name = "Epson-VGA",
149 .refresh = 60,
150 .xres = 480,
151 .yres = 640,
152 .pixclock = 41701,
153 .left_margin = 20,
154 .right_margin = 41,
155 .upper_margin = 10,
156 .lower_margin = 5,
157 .hsync_len = 20,
158 .vsync_len = 10,
159 .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
160 .vmode = FB_VMODE_NONINTERLACED,
161 .flag = 0,
162 },
163};
164
afa77ef3 165static struct mx3fb_platform_data mx3fb_pdata __initdata = {
e42010e0
AP		 166 .name = "Epson-VGA",
167 .mode = fb_modedb,
168 .num_modes = ARRAY_SIZE(fb_modedb),
169};
170
171/* LCD */
172static struct l4f00242t03_pdata mx31_3ds_l4f00242t03_pdata = {
173 .reset_gpio = IOMUX_TO_GPIO(MX31_PIN_LCS1),
174 .data_enable_gpio = IOMUX_TO_GPIO(MX31_PIN_SER_RS),
0ce88b34
AP		 175};
176
177/*
178 * Support for SD card slot in personality board
179 */
180#define MX31_3DS_GPIO_SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)
181#define MX31_3DS_GPIO_SDHC1_BE IOMUX_TO_GPIO(MX31_PIN_GPIO3_0)
182
183static struct gpio mx31_3ds_sdhc1_gpios[] = {
184 { MX31_3DS_GPIO_SDHC1_CD, GPIOF_IN, "sdhc1-card-detect" },
185 { MX31_3DS_GPIO_SDHC1_BE, GPIOF_OUT_INIT_LOW, "sdhc1-bus-en" },
186};
187
188static int mx31_3ds_sdhc1_init(struct device *dev,
189 irq_handler_t detect_irq,
190 void *data)
191{
192 int ret;
193
194 ret = gpio_request_array(mx31_3ds_sdhc1_gpios,
195 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
196 if (ret) {
75fd32b8 197 pr_warn("Unable to request the SD/MMC GPIOs.\n");
0ce88b34
AP		 198 return ret;
199 }
200
ed175343 201 ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)),
4c1dd3e5 202 detect_irq,
0ce88b34
AP		 203 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
204 "sdhc1-detect", data);
205 if (ret) {
75fd32b8 206 pr_warn("Unable to request the SD/MMC card-detect IRQ.\n");
0ce88b34
AP		 207 goto gpio_free;
208 }
209
210 return 0;
211
212gpio_free:
213 gpio_free_array(mx31_3ds_sdhc1_gpios,
214 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
215 return ret;
216}
217
218static void mx31_3ds_sdhc1_exit(struct device *dev, void *data)
219{
ed175343 220 free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)), data);
0ce88b34
AP		 221 gpio_free_array(mx31_3ds_sdhc1_gpios,
222 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
223}
224
225static void mx31_3ds_sdhc1_setpower(struct device *dev, unsigned int vdd)
226{
227 /*
228 * While the voltage stuff is done by the driver, activate the
229 * Buffer Enable Pin only if there is a card in slot to fix the card
230 * voltage issue caused by bi-directional chip TXB0108 on 3Stack.
231 * Done here because at this stage we have for sure a debounced value
232 * of the presence of the card, showed by the value of vdd.
233 * 7 == ilog2(MMC_VDD_165_195)
234 */
235 if (vdd > 7)
236 gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 1);
237 else
238 gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 0);
239}
240
241static struct imxmmc_platform_data sdhc1_pdata = {
242 .init = mx31_3ds_sdhc1_init,
243 .exit = mx31_3ds_sdhc1_exit,
244 .setpower = mx31_3ds_sdhc1_setpower,
54c1f636
AP		 245};
246
247/*
248 * Matrix keyboard
249 */
250
251static const uint32_t mx31_3ds_keymap[] = {
252 KEY(0, 0, KEY_UP),
253 KEY(0, 1, KEY_DOWN),
254 KEY(1, 0, KEY_RIGHT),
255 KEY(1, 1, KEY_LEFT),
256 KEY(1, 2, KEY_ENTER),
257 KEY(2, 0, KEY_F6),
258 KEY(2, 1, KEY_F8),
259 KEY(2, 2, KEY_F9),
260 KEY(2, 3, KEY_F10),
261};
262
d690b4c4 263static const struct matrix_keymap_data mx31_3ds_keymap_data __initconst = {
54c1f636
AP		 264 .keymap = mx31_3ds_keymap,
265 .keymap_size = ARRAY_SIZE(mx31_3ds_keymap),
ae7a3f13
AP		 266};
267
268/* Regulators */
269static struct regulator_init_data pwgtx_init = {
270 .constraints = {
271 .boot_on = 1,
272 .always_on = 1,
273 },
274};
275
0d95b75e
FE		 276static struct regulator_init_data gpo_init = {
277 .constraints = {
278 .boot_on = 1,
279 .always_on = 1,
280 }
281};
282
0ce88b34 283static struct regulator_consumer_supply vmmc2_consumers[] = {
7f917a8d 284 REGULATOR_SUPPLY("vmmc", "imx31-mmc.0"),
0ce88b34
AP		 285};
286
287static struct regulator_init_data vmmc2_init = {
288 .constraints = {
289 .min_uV = 3000000,
290 .max_uV = 3000000,
291 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
292 REGULATOR_CHANGE_STATUS,
293 },
294 .num_consumer_supplies = ARRAY_SIZE(vmmc2_consumers),
295 .consumer_supplies = vmmc2_consumers,
296};
297
e42010e0 298static struct regulator_consumer_supply vmmc1_consumers[] = {
0556dc34 299 REGULATOR_SUPPLY("vcore", "spi0.0"),
e42010e0
AP		 300};
301
302static struct regulator_init_data vmmc1_init = {
303 .constraints = {
304 .min_uV = 2800000,
305 .max_uV = 2800000,
306 .apply_uV = 1,
307 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
308 REGULATOR_CHANGE_STATUS,
309 },
310 .num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers),
311 .consumer_supplies = vmmc1_consumers,
312};
313
314static struct regulator_consumer_supply vgen_consumers[] = {
0556dc34 315 REGULATOR_SUPPLY("vdd", "spi0.0"),
e42010e0
AP		 316};
317
318static struct regulator_init_data vgen_init = {
319 .constraints = {
320 .min_uV = 1800000,
321 .max_uV = 1800000,
322 .apply_uV = 1,
323 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
324 REGULATOR_CHANGE_STATUS,
325 },
326 .num_consumer_supplies = ARRAY_SIZE(vgen_consumers),
327 .consumer_supplies = vgen_consumers,
328};
329
5836372e 330static struct mc13xxx_regulator_init_data mx31_3ds_regulators[] = {
ae7a3f13 331 {
57c78e35 332 .id = MC13783_REG_PWGT1SPI, /* Power Gate for ARM core. */
ae7a3f13
AP		 333 .init_data = &pwgtx_init,
334 }, {
57c78e35 335 .id = MC13783_REG_PWGT2SPI, /* Power Gate for L2 Cache. */
ae7a3f13 336 .init_data = &pwgtx_init,
0d95b75e
FE		 337 }, {
338
c97b7393 339 .id = MC13783_REG_GPO1, /* Turn on 1.8V */
0d95b75e
FE		 340 .init_data = &gpo_init,
341 }, {
c97b7393 342 .id = MC13783_REG_GPO3, /* Turn on 3.3V */
0d95b75e 343 .init_data = &gpo_init,
0ce88b34
AP		 344 }, {
345 .id = MC13783_REG_VMMC2, /* Power MMC/SD, WiFi/Bluetooth. */
346 .init_data = &vmmc2_init,
e42010e0
AP		 347 }, {
348 .id = MC13783_REG_VMMC1, /* Power LCD, CMOS, FM, GPS, Accel. */
349 .init_data = &vmmc1_init,
350 }, {
351 .id = MC13783_REG_VGEN, /* Power LCD */
352 .init_data = &vgen_init,
ae7a3f13
AP		 353 },
354};
355
356/* MC13783 */
5fb86e5d
PR		 357static struct mc13xxx_codec_platform_data mx31_3ds_codec = {
358 .dac_ssi_port = MC13783_SSI1_PORT,
359 .adc_ssi_port = MC13783_SSI1_PORT,
360};
361
4ec1b54c
AS		 362static struct mc13xxx_platform_data mc13783_pdata = {
363 .regulators = {
364 .regulators = mx31_3ds_regulators,
365 .num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
366 },
5fb86e5d
PR		 367 .codec = &mx31_3ds_codec,
368 .flags = MC13XXX_USE_TOUCHSCREEN | MC13XXX_USE_RTC | MC13XXX_USE_CODEC,
369
370};
371
372static struct imx_ssi_platform_data mx31_3ds_ssi_pdata = {
373 .flags = IMX_SSI_DMA | IMX_SSI_NET,
a1ac4424
AP		 374};
375
376/* SPI */
e42010e0 377static int spi0_internal_chipselect[] = {
901f26bc
GU		 378 MXC_SPI_CS(0),
379 MXC_SPI_CS(1),
e42010e0
AP		 380 MXC_SPI_CS(2),
381};
382
383static const struct spi_imx_master spi0_pdata __initconst = {
384 .chipselect = spi0_internal_chipselect,
385 .num_chipselect = ARRAY_SIZE(spi0_internal_chipselect),
386};
387
a1ac4424
AP		 388static int spi1_internal_chipselect[] = {
389 MXC_SPI_CS(0),
901f26bc 390 MXC_SPI_CS(1),
a1ac4424
AP		 391 MXC_SPI_CS(2),
392};
393
06606ff1 394static const struct spi_imx_master spi1_pdata __initconst = {
a1ac4424
AP		 395 .chipselect = spi1_internal_chipselect,
396 .num_chipselect = ARRAY_SIZE(spi1_internal_chipselect),
63d97667
VL		 397};
398
ae7a3f13
AP		 399static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
400 {
401 .modalias = "mc13783",
402 .max_speed_hz = 1000000,
403 .bus_num = 1,
901f26bc 404 .chip_select = 2, /* SS2 */
ae7a3f13 405 .platform_data = &mc13783_pdata,
ed175343 406 /* irq number is run-time assigned */
ae7a3f13 407 .mode = SPI_CS_HIGH,
e42010e0
AP		 408 }, {
409 .modalias = "l4f00242t03",
410 .max_speed_hz = 5000000,
411 .bus_num = 0,
901f26bc 412 .chip_select = 2, /* SS2 */
e42010e0 413 .platform_data = &mx31_3ds_l4f00242t03_pdata,
ae7a3f13
AP		 414 },
415};
416
a1b67b95
AP		 417/*
418 * NAND Flash
419 */
a2ceeef5
UKK		 420static const struct mxc_nand_platform_data
421mx31_3ds_nand_board_info __initconst = {
a1b67b95
AP		 422 .width = 1,
423 .hw_ecc = 1,
5328ecbb 424#ifdef CONFIG_MACH_MX31_3DS_MXC_NAND_USE_BBT
a1b67b95
AP		 425 .flash_bbt = 1,
426#endif
427};
428
a2ef4562
ML		 429/*
430 * USB OTG
431 */
432
433#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
434 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
435
436#define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR)
0d95b75e 437#define USBH2_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_BYP)
a2ef4562 438
41f63475 439static int mx31_3ds_usbotg_init(void)
a2ef4562 440{
41f63475
FE		 441 int err;
442
a2ef4562
ML		 443 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
444 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
445 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
446 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
447 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
448 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
449 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
450 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
451 mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
452 mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
453 mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
454 mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
455
41f63475
FE		 456 err = gpio_request(USBOTG_RST_B, "otgusb-reset");
457 if (err) {
458 pr_err("Failed to request the USB OTG reset gpio\n");
459 return err;
460 }
461
462 err = gpio_direction_output(USBOTG_RST_B, 0);
463 if (err) {
464 pr_err("Failed to drive the USB OTG reset gpio\n");
465 goto usbotg_free_reset;
466 }
467
a2ef4562
ML		 468 mdelay(1);
469 gpio_set_value(USBOTG_RST_B, 1);
41f63475
FE		 470 return 0;
471
472usbotg_free_reset:
473 gpio_free(USBOTG_RST_B);
474 return err;
a2ef4562
ML		 475}
476
4bd597b6
SH		 477static int mx31_3ds_otg_init(struct platform_device *pdev)
478{
479 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
480}
481
482static int mx31_3ds_host2_init(struct platform_device *pdev)
0d95b75e
FE		 483{
484 int err;
485
486 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
487 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
488 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
489 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
490 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
491 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
492 mxc_iomux_set_pad(MX31_PIN_PC_VS2, USB_PAD_CFG);
493 mxc_iomux_set_pad(MX31_PIN_PC_BVD1, USB_PAD_CFG);
494 mxc_iomux_set_pad(MX31_PIN_PC_BVD2, USB_PAD_CFG);
495 mxc_iomux_set_pad(MX31_PIN_PC_RST, USB_PAD_CFG);
496 mxc_iomux_set_pad(MX31_PIN_IOIS16, USB_PAD_CFG);
497 mxc_iomux_set_pad(MX31_PIN_PC_RW_B, USB_PAD_CFG);
498
499 err = gpio_request(USBH2_RST_B, "usbh2-reset");
500 if (err) {
501 pr_err("Failed to request the USB Host 2 reset gpio\n");
502 return err;
503 }
504
505 err = gpio_direction_output(USBH2_RST_B, 0);
506 if (err) {
507 pr_err("Failed to drive the USB Host 2 reset gpio\n");
508 goto usbotg_free_reset;
509 }
510
511 mdelay(1);
512 gpio_set_value(USBH2_RST_B, 1);
4bd597b6
SH		 513
514 mdelay(10);
515
516 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
0d95b75e
FE		 517
518usbotg_free_reset:
519 gpio_free(USBH2_RST_B);
520 return err;
521}
522
1c50e672 523static struct mxc_usbh_platform_data otg_pdata __initdata = {
4bd597b6 524 .init = mx31_3ds_otg_init,
1c50e672 525 .portsc = MXC_EHCI_MODE_ULPI,
1c50e672 526};
0d95b75e
FE		 527
528static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
529 .init = mx31_3ds_host2_init,
530 .portsc = MXC_EHCI_MODE_ULPI,
0d95b75e 531};
1c50e672 532
9e1dde33 533static const struct fsl_usb2_platform_data usbotg_pdata __initconst = {
a2ef4562
ML		 534 .operating_mode = FSL_USB2_DR_DEVICE,
535 .phy_mode = FSL_USB2_PHY_ULPI,
536};
537
33a264dd 538static bool otg_mode_host __initdata;
1c50e672
FE		 539
540static int __init mx31_3ds_otg_mode(char *options)
541{
542 if (!strcmp(options, "host"))
33a264dd 543 otg_mode_host = true;
1c50e672 544 else if (!strcmp(options, "device"))
33a264dd 545 otg_mode_host = false;
1c50e672
FE		 546 else
547 pr_info("otg_mode neither \"host\" nor \"device\". "
548 "Defaulting to device\n");
33a264dd 549 return 1;
1c50e672
FE		 550}
551__setup("otg_mode=", mx31_3ds_otg_mode);
552
16cf5c41 553static const struct imxuart_platform_data uart_pdata __initconst = {
153fa1d8
ML		 554 .flags = IMXUART_HAVE_RTSCTS,
555};
1553a1ec 556
3d943024
FE		 557static const struct imxi2c_platform_data mx31_3ds_i2c0_data __initconst = {
558 .bitrate = 100000,
559};
560
e134fb2b 561static void __init mx31_3ds_init(void)
1553a1ec 562{
b78d8e59
SG		 563 imx31_soc_init();
564
b2a08e3e
FE		 565 /* Configure SPI1 IOMUX */
566 mxc_iomux_set_gpr(MUX_PGP_CSPI_BB, true);
567
11a332ad
AP		 568 mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
569 "mx31_3ds");
153fa1d8 570
16cf5c41 571 imx31_add_imx_uart0(&uart_pdata);
a2ceeef5 572 imx31_add_mxc_nand(&mx31_3ds_nand_board_info);
ae7a3f13 573
4a74bddc 574 imx31_add_spi_imx1(&spi1_pdata);
ce689b0d
VZ		 575
576 imx31_add_imx_keypad(&mx31_3ds_keymap_data);
577
578 imx31_add_imx2_wdt();
579 imx31_add_imx_i2c0(&mx31_3ds_i2c0_data);
580
581 imx31_add_spi_imx0(&spi0_pdata);
582 imx31_add_ipu_core();
583 imx31_add_mx3_sdc_fb(&mx3fb_pdata);
584
585 imx31_add_imx_ssi(0, &mx31_3ds_ssi_pdata);
586
587 imx_add_platform_device("imx_mc13783", 0, NULL, 0, NULL, 0);
588}
589
590static void __init mx31_3ds_late(void)
591{
ed175343 592 mx31_3ds_spi_devs[0].irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
ae7a3f13 593 spi_register_board_info(mx31_3ds_spi_devs,
ce689b0d 594 ARRAY_SIZE(mx31_3ds_spi_devs));
135cad36 595
a2ef4562 596 mx31_3ds_usbotg_init();
1c50e672 597 if (otg_mode_host) {
48f6b099
SH		 598 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
599 ULPI_OTG_DRVVBUS_EXT);
600 if (otg_pdata.otg)
601 imx31_add_mxc_ehci_otg(&otg_pdata);
1c50e672 602 }
48f6b099
SH		 603 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
604 ULPI_OTG_DRVVBUS_EXT);
605 if (usbh2_pdata.otg)
606 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
607
1c50e672
FE		 608 if (!otg_mode_host)
609 imx31_add_fsl_usb2_udc(&usbotg_pdata);
a2ef4562 610
ed4a7fb0 611 if (mxc_expio_init(MX31_CS5_BASE_ADDR, IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)))
b8be7b9a 612 printk(KERN_WARNING "Init of the debug board failed, all "
ce689b0d 613 "devices on the debug board are unusable.\n");
e42010e0 614
ce689b0d 615 imx31_add_mxc_mmc(0, &sdhc1_pdata);
1553a1ec
FE		 616}
617
11a332ad 618static void __init mx31_3ds_timer_init(void)
1553a1ec 619{
30c730f8 620 mx31_clocks_init(26000000);
1553a1ec
FE		 621}
622
1553a1ec
FE		 623MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
624 /* Maintainer: Freescale Semiconductor, Inc. */
dc8f1907 625 .atag_offset = 0x100,
97976e22
UKK		 626 .map_io = mx31_map_io,
627 .init_early = imx31_init_early,
628 .init_irq = mx31_init_irq,
6bb27d73 629 .init_time = mx31_3ds_timer_init,
e134fb2b 630 .init_machine = mx31_3ds_init,
ce689b0d 631 .init_late = mx31_3ds_late,
65ea7884 632 .restart = mxc_restart,
1553a1ec 633MACHINE_END
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