[mirror_ubuntu-eoan-kernel.git] / arch / arm / mach-imx / mach-mx31lite.c

/*
 *  Copyright (C) 2000 Deep Blue Solutions Ltd
 *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
 *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 *  Copyright (C) 2009 Daniel Mack <daniel@caiaq.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/types.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/memory.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/moduleparam.h>
#include <linux/smsc911x.h>
#include <linux/mfd/mc13783.h>
#include <linux/spi/spi.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <linux/mtd/physmap.h>
#include <linux/delay.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/fixed.h>

#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <asm/page.h>
#include <asm/setup.h>

#include "board-mx31lite.h"
#include "common.h"
#include "devices-imx31.h"
#include "ehci.h"
#include "hardware.h"
#include "iomux-mx3.h"
#include "ulpi.h"

/*
 * This file contains the module-specific initialization routines.
 */

static unsigned int mx31lite_pins[] = {
	/* LAN9117 IRQ pin */
	IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO),
	/* SPI 1 */
	MX31_PIN_CSPI2_SCLK__SCLK,
	MX31_PIN_CSPI2_MOSI__MOSI,
	MX31_PIN_CSPI2_MISO__MISO,
	MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
	MX31_PIN_CSPI2_SS0__SS0,
	MX31_PIN_CSPI2_SS1__SS1,
	MX31_PIN_CSPI2_SS2__SS2,
};

static const struct mxc_nand_platform_data
mx31lite_nand_board_info __initconst  = {
	.width = 1,
	.hw_ecc = 1,
};

static struct smsc911x_platform_config smsc911x_config = {
	.irq_polarity	= SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
	.irq_type	= SMSC911X_IRQ_TYPE_PUSH_PULL,
	.flags		= SMSC911X_USE_16BIT,
};

static struct resource smsc911x_resources[] = {
	{
		.start		= MX31_CS4_BASE_ADDR,
		.end		= MX31_CS4_BASE_ADDR + 0x100,
		.flags		= IORESOURCE_MEM,
	}, {
		/* irq number is run-time assigned */
		.flags		= IORESOURCE_IRQ,
	},
};

static struct platform_device smsc911x_device = {
	.name		= "smsc911x",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(smsc911x_resources),
	.resource	= smsc911x_resources,
	.dev		= {
		.platform_data = &smsc911x_config,
	},
};

/*
 * SPI
 *
 * The MC13783 is the only hard-wired SPI device on the module.
 */

static int spi_internal_chipselect[] = {
	MXC_SPI_CS(0),
};

static const struct spi_imx_master spi1_pdata __initconst = {
	.chipselect	= spi_internal_chipselect,
	.num_chipselect	= ARRAY_SIZE(spi_internal_chipselect),
};

static struct mc13xxx_platform_data mc13783_pdata __initdata = {
	.flags = MC13XXX_USE_RTC,
};

static struct spi_board_info mc13783_spi_dev __initdata = {
	.modalias       = "mc13783",
	.max_speed_hz   = 1000000,
	.bus_num	= 1,
	.chip_select    = 0,
	.platform_data  = &mc13783_pdata,
	/* irq number is run-time assigned */
};

/*
 * USB
 */

#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
			PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)

static int usbh2_init(struct platform_device *pdev)
{
	int pins[] = {
		MX31_PIN_USBH2_DATA0__USBH2_DATA0,
		MX31_PIN_USBH2_DATA1__USBH2_DATA1,
		MX31_PIN_USBH2_CLK__USBH2_CLK,
		MX31_PIN_USBH2_DIR__USBH2_DIR,
		MX31_PIN_USBH2_NXT__USBH2_NXT,
		MX31_PIN_USBH2_STP__USBH2_STP,
	};

	mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H2");

	mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);

	mxc_iomux_set_gpr(MUX_PGP_UH2, true);

	/* chip select */
	mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO),
				"USBH2_CS");
	gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS");
	gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0);

	mdelay(10);

	return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
}

static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
	.init   = usbh2_init,
	.portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
};

/*
 * NOR flash
 */

static struct physmap_flash_data nor_flash_data = {
	.width  = 2,
};

static struct resource nor_flash_resource = {
	.start  = 0xa0000000,
	.end    = 0xa1ffffff,
	.flags  = IORESOURCE_MEM,
};

static struct platform_device physmap_flash_device = {
	.name   = "physmap-flash",
	.id     = 0,
	.dev    = {
		.platform_data  = &nor_flash_data,
	},
	.resource = &nor_flash_resource,
	.num_resources = 1,
};


/*
 * This structure defines the MX31 memory map.
 */
static struct map_desc mx31lite_io_desc[] __initdata = {
	{
		.virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT,
		.pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
		.length = MX31_CS4_SIZE,
		.type = MT_DEVICE
	}
};

/*
 * Set up static virtual mappings.
 */
void __init mx31lite_map_io(void)
{
	mx31_map_io();
	iotable_init(mx31lite_io_desc, ARRAY_SIZE(mx31lite_io_desc));
}

static int mx31lite_baseboard;
core_param(mx31lite_baseboard, mx31lite_baseboard, int, 0444);

static struct regulator_consumer_supply dummy_supplies[] = {
	REGULATOR_SUPPLY("vdd33a", "smsc911x"),
	REGULATOR_SUPPLY("vddvario", "smsc911x"),
};

static void __init mx31lite_init(void)
{
	int ret;

	imx31_soc_init();

	switch (mx31lite_baseboard) {
	case MX31LITE_NOBOARD:
		break;
	case MX31LITE_DB:
		mx31lite_db_init();
		break;
	default:
		printk(KERN_ERR "Illegal mx31lite_baseboard type %d\n",
				mx31lite_baseboard);
	}

	mxc_iomux_setup_multiple_pins(mx31lite_pins, ARRAY_SIZE(mx31lite_pins),
				      "mx31lite");

	/* NOR and NAND flash */
	platform_device_register(&physmap_flash_device);
	imx31_add_mxc_nand(&mx31lite_nand_board_info);

	imx31_add_spi_imx1(&spi1_pdata);
	mc13783_spi_dev.irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
	spi_register_board_info(&mc13783_spi_dev, 1);

	/* USB */
	usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
			ULPI_OTG_DRVVBUS_EXT);
	if (usbh2_pdata.otg)
		imx31_add_mxc_ehci_hs(2, &usbh2_pdata);

	regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));

	/* SMSC9117 IRQ pin */
	ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq");
	if (ret)
		pr_warning("could not get LAN irq gpio\n");
	else {
		gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_SFS6));
		smsc911x_resources[1].start =
			gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SFS6));
		smsc911x_resources[1].end =
			gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SFS6));
		platform_device_register(&smsc911x_device);
	}
}

static void __init mx31lite_timer_init(void)
{
	mx31_clocks_init(26000000);
}

MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
	/* Maintainer: Freescale Semiconductor, Inc. */
	.atag_offset = 0x100,
	.map_io = mx31lite_map_io,
	.init_early = imx31_init_early,
	.init_irq = mx31_init_irq,
	.init_time	= mx31lite_timer_init,
	.init_machine = mx31lite_init,
	.restart	= mxc_restart,
MACHINE_END
Commit	Line	Data
9a4cd7a5 DM	1	/*
	2	* Copyright (C) 2000 Deep Blue Solutions Ltd
	3	* Copyright (C) 2002 Shane Nay (shane@minirl.com)
	4	* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
84677d11	5	* Copyright (C) 2009 Daniel Mack <daniel@caiaq.de>
9a4cd7a5 DM	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
9a4cd7a5 DM	16	*/
	17
	18	#include <linux/types.h>
	19	#include <linux/init.h>
	20	#include <linux/kernel.h>
	21	#include <linux/memory.h>
3211705f ML	22	#include <linux/platform_device.h>
3211705f ML	23	#include <linux/gpio.h>
9e907416	24	#include <linux/moduleparam.h>
3211705f	25	#include <linux/smsc911x.h>
84677d11 DM	26	#include <linux/mfd/mc13783.h>
84677d11 DM	27	#include <linux/spi/spi.h>
a050c8e9 DM	28	#include <linux/usb/otg.h>
a050c8e9 DM	29	#include <linux/usb/ulpi.h>
6d3e6601	30	#include <linux/mtd/physmap.h>
4bd597b6	31	#include <linux/delay.h>
da21d4dc FE	32	#include <linux/regulator/machine.h>
da21d4dc FE	33	#include <linux/regulator/fixed.h>
9a4cd7a5	34
9a4cd7a5 DM	35	#include <asm/mach-types.h>
9a4cd7a5 DM	36	#include <asm/mach/arch.h>
9e8a30dc	37	#include <asm/mach/time.h>
9a4cd7a5	38	#include <asm/mach/map.h>
9a4cd7a5 DM	39	#include <asm/page.h>
9a4cd7a5 DM	40	#include <asm/setup.h>
84677d11	41
3ed0bcb4	42	#include "board-mx31lite.h"
e3372474	43	#include "common.h"
a2ceeef5	44	#include "devices-imx31.h"
641dfe8b	45	#include "ehci.h"
50f2de61	46	#include "hardware.h"
267dd34c	47	#include "iomux-mx3.h"
39ef6340	48	#include "ulpi.h"
9a4cd7a5 DM	49
9a4cd7a5 DM	50	/*
b7d91a62	51	* This file contains the module-specific initialization routines.
9a4cd7a5 DM	52	*/
9a4cd7a5 DM	53
a854b8ab	54	static unsigned int mx31lite_pins[] = {
3211705f ML	55	/* LAN9117 IRQ pin */
3211705f ML	56	IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO),
84677d11 DM	57	/* SPI 1 */
	58	MX31_PIN_CSPI2_SCLK__SCLK,
	59	MX31_PIN_CSPI2_MOSI__MOSI,
	60	MX31_PIN_CSPI2_MISO__MISO,
	61	MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
	62	MX31_PIN_CSPI2_SS0__SS0,
	63	MX31_PIN_CSPI2_SS1__SS1,
	64	MX31_PIN_CSPI2_SS2__SS2,
a854b8ab ML	65	};
a854b8ab ML	66
a2ceeef5 UKK	67	static const struct mxc_nand_platform_data
a2ceeef5 UKK	68	mx31lite_nand_board_info __initconst = {
183c7fff ML	69	.width = 1,
	70	.hw_ecc = 1,
	71	};
	72
3211705f ML	73	static struct smsc911x_platform_config smsc911x_config = {
	74	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
	75	.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
	76	.flags = SMSC911X_USE_16BIT,
	77	};
	78
	79	static struct resource smsc911x_resources[] = {
3f4f54b4	80	{
f568dd7f UKK	81	.start = MX31_CS4_BASE_ADDR,
f568dd7f UKK	82	.end = MX31_CS4_BASE_ADDR + 0x100,
3211705f	83	.flags = IORESOURCE_MEM,
3f4f54b4	84	}, {
ed175343	85	/* irq number is run-time assigned */
3211705f ML	86	.flags = IORESOURCE_IRQ,
	87	},
	88	};
	89
	90	static struct platform_device smsc911x_device = {
	91	.name = "smsc911x",
	92	.id = -1,
	93	.num_resources = ARRAY_SIZE(smsc911x_resources),
	94	.resource = smsc911x_resources,
	95	.dev = {
	96	.platform_data = &smsc911x_config,
	97	},
	98	};
	99
84677d11 DM	100	/*
	101	* SPI
	102	*
	103	* The MC13783 is the only hard-wired SPI device on the module.
	104	*/
	105
	106	static int spi_internal_chipselect[] = {
	107	MXC_SPI_CS(0),
	108	};
	109
06606ff1	110	static const struct spi_imx_master spi1_pdata __initconst = {
84677d11 DM	111	.chipselect = spi_internal_chipselect,
	112	.num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
	113	};
	114
5836372e	115	static struct mc13xxx_platform_data mc13783_pdata __initdata = {
46621ebb	116	.flags = MC13XXX_USE_RTC,
84677d11 DM	117	};
	118
	119	static struct spi_board_info mc13783_spi_dev __initdata = {
	120	.modalias = "mc13783",
	121	.max_speed_hz = 1000000,
	122	.bus_num = 1,
	123	.chip_select = 0,
	124	.platform_data = &mc13783_pdata,
ed175343	125	/* irq number is run-time assigned */
84677d11 DM	126	};
84677d11 DM	127
a050c8e9 DM	128	/*
	129	* USB
	130	*/
	131
	132	#define USB_PAD_CFG (PAD_CTL_DRV_MAX \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS_CMOS \| \
	133	PAD_CTL_ODE_CMOS \| PAD_CTL_100K_PU)
	134
	135	static int usbh2_init(struct platform_device *pdev)
	136	{
	137	int pins[] = {
	138	MX31_PIN_USBH2_DATA0__USBH2_DATA0,
	139	MX31_PIN_USBH2_DATA1__USBH2_DATA1,
	140	MX31_PIN_USBH2_CLK__USBH2_CLK,
	141	MX31_PIN_USBH2_DIR__USBH2_DIR,
	142	MX31_PIN_USBH2_NXT__USBH2_NXT,
	143	MX31_PIN_USBH2_STP__USBH2_STP,
	144	};
	145
	146	mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H2");
	147
	148	mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
	149	mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
	150	mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
	151	mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
	152	mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
	153	mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
	154	mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
	155	mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
	156	mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
	157	mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
	158	mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
	159	mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);
	160
	161	mxc_iomux_set_gpr(MUX_PGP_UH2, true);
	162
	163	/* chip select */
	164	mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO),
	165	"USBH2_CS");
	166	gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS");
	167	gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0);
	168
4bd597b6 SH	169	mdelay(10);
	170
	171	return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
a050c8e9 DM	172	}
a050c8e9 DM	173
2d58de28	174	static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
a050c8e9 DM	175	.init = usbh2_init,
a050c8e9 DM	176	.portsc = MXC_EHCI_MODE_ULPI \| MXC_EHCI_UTMI_8BIT,
a050c8e9 DM	177	};
a050c8e9 DM	178
6d3e6601 DM	179	/*
	180	* NOR flash
	181	*/
	182
	183	static struct physmap_flash_data nor_flash_data = {
	184	.width = 2,
	185	};
	186
	187	static struct resource nor_flash_resource = {
	188	.start = 0xa0000000,
	189	.end = 0xa1ffffff,
	190	.flags = IORESOURCE_MEM,
	191	};
	192
	193	static struct platform_device physmap_flash_device = {
	194	.name = "physmap-flash",
	195	.id = 0,
	196	.dev = {
	197	.platform_data = &nor_flash_data,
	198	},
	199	.resource = &nor_flash_resource,
	200	.num_resources = 1,
	201	};
	202
	203
	204
9a4cd7a5 DM	205	/*
	206	* This structure defines the MX31 memory map.
	207	*/
	208	static struct map_desc mx31lite_io_desc[] __initdata = {
	209	{
f25d696a	210	.virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT,
f568dd7f UKK	211	.pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
f568dd7f UKK	212	.length = MX31_CS4_SIZE,
9a4cd7a5 DM	213	.type = MT_DEVICE
	214	}
	215	};
	216
	217	/*
	218	* Set up static virtual mappings.
	219	*/
	220	void __init mx31lite_map_io(void)
	221	{
cd4a05f9	222	mx31_map_io();
9a4cd7a5 DM	223	iotable_init(mx31lite_io_desc, ARRAY_SIZE(mx31lite_io_desc));
	224	}
	225
b7d91a62 DM	226	static int mx31lite_baseboard;
	227	core_param(mx31lite_baseboard, mx31lite_baseboard, int, 0444);
	228
da21d4dc FE	229	static struct regulator_consumer_supply dummy_supplies[] = {
	230	REGULATOR_SUPPLY("vdd33a", "smsc911x"),
	231	REGULATOR_SUPPLY("vddvario", "smsc911x"),
	232	};
	233
e134fb2b	234	static void __init mx31lite_init(void)
9a4cd7a5	235	{
4f163eb8 SH	236	int ret;
4f163eb8 SH	237
b78d8e59 SG	238	imx31_soc_init();
b78d8e59 SG	239
b7d91a62 DM	240	switch (mx31lite_baseboard) {
	241	case MX31LITE_NOBOARD:
	242	break;
	243	case MX31LITE_DB:
	244	mx31lite_db_init();
	245	break;
	246	default:
	247	printk(KERN_ERR "Illegal mx31lite_baseboard type %d\n",
	248	mx31lite_baseboard);
	249	}
	250
a854b8ab ML	251	mxc_iomux_setup_multiple_pins(mx31lite_pins, ARRAY_SIZE(mx31lite_pins),
	252	"mx31lite");
	253
6d3e6601 DM	254	/* NOR and NAND flash */
6d3e6601 DM	255	platform_device_register(&physmap_flash_device);
a2ceeef5	256	imx31_add_mxc_nand(&mx31lite_nand_board_info);
6d3e6601	257
06606ff1	258	imx31_add_spi_imx1(&spi1_pdata);
ed175343	259	mc13783_spi_dev.irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
84677d11	260	spi_register_board_info(&mc13783_spi_dev, 1);
3211705f	261
a050c8e9	262	/* USB */
48f6b099 SH	263	usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS \|
	264	ULPI_OTG_DRVVBUS_EXT);
	265	if (usbh2_pdata.otg)
	266	imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
a050c8e9	267
da21d4dc FE	268	regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
da21d4dc FE	269
3211705f	270	/* SMSC9117 IRQ pin */
4f163eb8 SH	271	ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq");
	272	if (ret)
	273	pr_warning("could not get LAN irq gpio\n");
	274	else {
	275	gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_SFS6));
ed175343 SG	276	smsc911x_resources[1].start =
	277	gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SFS6));
	278	smsc911x_resources[1].end =
	279	gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SFS6));
4f163eb8 SH	280	platform_device_register(&smsc911x_device);
4f163eb8 SH	281	}
9a4cd7a5 DM	282	}
9a4cd7a5 DM	283
9e8a30dc JB	284	static void __init mx31lite_timer_init(void)
9e8a30dc JB	285	{
30c730f8	286	mx31_clocks_init(26000000);
9e8a30dc JB	287	}
9e8a30dc JB	288
b7d91a62	289	MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
9a4cd7a5	290	/* Maintainer: Freescale Semiconductor, Inc. */
dc8f1907	291	.atag_offset = 0x100,
97976e22 UKK	292	.map_io = mx31lite_map_io,
	293	.init_early = imx31_init_early,
	294	.init_irq = mx31_init_irq,
6bb27d73	295	.init_time = mx31lite_timer_init,
e134fb2b	296	.init_machine = mx31lite_init,
65ea7884	297	.restart = mxc_restart,
9a4cd7a5	298	MACHINE_END