[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-imx / mach-mx31lite.c

/*
 *  Copyright (C) 2000 Deep Blue Solutions Ltd
 *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
 *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 *  Copyright (C) 2009 Daniel Mack <daniel@caiaq.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/types.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/memory.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/moduleparam.h>
#include <linux/smsc911x.h>
#include <linux/mfd/mc13783.h>
#include <linux/spi/spi.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <linux/mtd/physmap.h>
#include <linux/delay.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/fixed.h>

#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <asm/page.h>
#include <asm/setup.h>

#include "board-mx31lite.h"
#include "common.h"
#include "devices-imx31.h"
#include "ehci.h"
#include "hardware.h"
#include "iomux-mx3.h"
#include "ulpi.h"

/*
 * This file contains the module-specific initialization routines.
 */

static unsigned int mx31lite_pins[] = {
	/* UART1 */
	MX31_PIN_CTS1__CTS1,
	MX31_PIN_RTS1__RTS1,
	MX31_PIN_TXD1__TXD1,
	MX31_PIN_RXD1__RXD1,
	/* SPI 0 */
	MX31_PIN_CSPI1_SCLK__SCLK,
	MX31_PIN_CSPI1_MOSI__MOSI,
	MX31_PIN_CSPI1_MISO__MISO,
	MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
	MX31_PIN_CSPI1_SS0__SS0,
	MX31_PIN_CSPI1_SS1__SS1,
	MX31_PIN_CSPI1_SS2__SS2,
	/* LAN9117 IRQ pin */
	IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO),
	/* SPI 1 */
	MX31_PIN_CSPI2_SCLK__SCLK,
	MX31_PIN_CSPI2_MOSI__MOSI,
	MX31_PIN_CSPI2_MISO__MISO,
	MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
	MX31_PIN_CSPI2_SS0__SS0,
	MX31_PIN_CSPI2_SS1__SS1,
	MX31_PIN_CSPI2_SS2__SS2,
};

/* UART */
static const struct imxuart_platform_data uart_pdata __initconst = {
	.flags = IMXUART_HAVE_RTSCTS,
};

/* SPI */
static int spi0_internal_chipselect[] = {
	MXC_SPI_CS(0),
	MXC_SPI_CS(1),
	MXC_SPI_CS(2),
};

static const struct spi_imx_master spi0_pdata __initconst = {
	.chipselect	= spi0_internal_chipselect,
	.num_chipselect	= ARRAY_SIZE(spi0_internal_chipselect),
};

static const struct mxc_nand_platform_data
mx31lite_nand_board_info __initconst  = {
	.width = 1,
	.hw_ecc = 1,
};

static struct smsc911x_platform_config smsc911x_config = {
	.irq_polarity	= SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
	.irq_type	= SMSC911X_IRQ_TYPE_PUSH_PULL,
	.flags		= SMSC911X_USE_16BIT,
};

static struct resource smsc911x_resources[] = {
	{
		.start		= MX31_CS4_BASE_ADDR,
		.end		= MX31_CS4_BASE_ADDR + 0x100,
		.flags		= IORESOURCE_MEM,
	}, {
		/* irq number is run-time assigned */
		.flags		= IORESOURCE_IRQ,
	},
};

static struct platform_device smsc911x_device = {
	.name		= "smsc911x",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(smsc911x_resources),
	.resource	= smsc911x_resources,
	.dev		= {
		.platform_data = &smsc911x_config,
	},
};

/*
 * SPI
 *
 * The MC13783 is the only hard-wired SPI device on the module.
 */

static int spi1_internal_chipselect[] = {
	MXC_SPI_CS(0),
};

static const struct spi_imx_master spi1_pdata __initconst = {
	.chipselect	= spi1_internal_chipselect,
	.num_chipselect	= ARRAY_SIZE(spi1_internal_chipselect),
};

static struct mc13xxx_platform_data mc13783_pdata __initdata = {
	.flags = MC13XXX_USE_RTC,
};

static struct spi_board_info mc13783_spi_dev __initdata = {
	.modalias       = "mc13783",
	.max_speed_hz   = 1000000,
	.bus_num	= 1,
	.chip_select    = 0,
	.platform_data  = &mc13783_pdata,
	/* irq number is run-time assigned */
};

/*
 * USB
 */

#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
			PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)

static int usbh2_init(struct platform_device *pdev)
{
	int pins[] = {
		MX31_PIN_USBH2_DATA0__USBH2_DATA0,
		MX31_PIN_USBH2_DATA1__USBH2_DATA1,
		MX31_PIN_USBH2_CLK__USBH2_CLK,
		MX31_PIN_USBH2_DIR__USBH2_DIR,
		MX31_PIN_USBH2_NXT__USBH2_NXT,
		MX31_PIN_USBH2_STP__USBH2_STP,
	};

	mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H2");

	mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);

	mxc_iomux_set_gpr(MUX_PGP_UH2, true);

	/* chip select */
	mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO),
				"USBH2_CS");
	gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS");
	gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0);

	mdelay(10);

	return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
}

static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
	.init   = usbh2_init,
	.portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
};

/*
 * NOR flash
 */

static struct physmap_flash_data nor_flash_data = {
	.width  = 2,
};

static struct resource nor_flash_resource = {
	.start  = 0xa0000000,
	.end    = 0xa1ffffff,
	.flags  = IORESOURCE_MEM,
};

static struct platform_device physmap_flash_device = {
	.name   = "physmap-flash",
	.id     = 0,
	.dev    = {
		.platform_data  = &nor_flash_data,
	},
	.resource = &nor_flash_resource,
	.num_resources = 1,
};

/*
 * This structure defines the MX31 memory map.
 */
static struct map_desc mx31lite_io_desc[] __initdata = {
	{
		.virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT,
		.pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
		.length = MX31_CS4_SIZE,
		.type = MT_DEVICE
	}
};

/*
 * Set up static virtual mappings.
 */
void __init mx31lite_map_io(void)
{
	mx31_map_io();
	iotable_init(mx31lite_io_desc, ARRAY_SIZE(mx31lite_io_desc));
}

static int mx31lite_baseboard;
core_param(mx31lite_baseboard, mx31lite_baseboard, int, 0444);

static struct regulator_consumer_supply dummy_supplies[] = {
	REGULATOR_SUPPLY("vdd33a", "smsc911x"),
	REGULATOR_SUPPLY("vddvario", "smsc911x"),
};

static void __init mx31lite_init(void)
{
	imx31_soc_init();

	mxc_iomux_setup_multiple_pins(mx31lite_pins, ARRAY_SIZE(mx31lite_pins),
				      "mx31lite");

	imx31_add_imx_uart0(&uart_pdata);
	imx31_add_spi_imx0(&spi0_pdata);

	/* NOR and NAND flash */
	platform_device_register(&physmap_flash_device);
	imx31_add_mxc_nand(&mx31lite_nand_board_info);

	imx31_add_spi_imx1(&spi1_pdata);

	regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
}

static void __init mx31lite_late(void)
{
	int ret;

	if (mx31lite_baseboard == MX31LITE_DB)
		mx31lite_db_init();

	mc13783_spi_dev.irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
	spi_register_board_info(&mc13783_spi_dev, 1);

	/* USB */
	usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
			ULPI_OTG_DRVVBUS_EXT);
	if (usbh2_pdata.otg)
		imx31_add_mxc_ehci_hs(2, &usbh2_pdata);

	/* SMSC9117 IRQ pin */
	ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq");
	if (ret)
		pr_warn("could not get LAN irq gpio\n");
	else {
		gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_SFS6));
		smsc911x_resources[1].start =
			gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SFS6));
		smsc911x_resources[1].end =
			gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SFS6));
		platform_device_register(&smsc911x_device);
	}
}

static void __init mx31lite_timer_init(void)
{
	mx31_clocks_init(26000000);
}

MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
	/* Maintainer: Freescale Semiconductor, Inc. */
	.atag_offset = 0x100,
	.map_io = mx31lite_map_io,
	.init_early = imx31_init_early,
	.init_irq = mx31_init_irq,
	.init_time	= mx31lite_timer_init,
	.init_machine = mx31lite_init,
	.init_late	= mx31lite_late,
	.restart	= mxc_restart,
MACHINE_END
Commit	Line	Data
9a4cd7a5 DM	1	/*
	2	* Copyright (C) 2000 Deep Blue Solutions Ltd
	3	* Copyright (C) 2002 Shane Nay (shane@minirl.com)
	4	* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
84677d11	5	* Copyright (C) 2009 Daniel Mack <daniel@caiaq.de>
9a4cd7a5 DM	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
9a4cd7a5 DM	16	*/
	17
	18	#include <linux/types.h>
	19	#include <linux/init.h>
	20	#include <linux/kernel.h>
	21	#include <linux/memory.h>
3211705f ML	22	#include <linux/platform_device.h>
3211705f ML	23	#include <linux/gpio.h>
9e907416	24	#include <linux/moduleparam.h>
3211705f	25	#include <linux/smsc911x.h>
84677d11 DM	26	#include <linux/mfd/mc13783.h>
84677d11 DM	27	#include <linux/spi/spi.h>
a050c8e9 DM	28	#include <linux/usb/otg.h>
a050c8e9 DM	29	#include <linux/usb/ulpi.h>
6d3e6601	30	#include <linux/mtd/physmap.h>
4bd597b6	31	#include <linux/delay.h>
da21d4dc FE	32	#include <linux/regulator/machine.h>
da21d4dc FE	33	#include <linux/regulator/fixed.h>
9a4cd7a5	34
9a4cd7a5 DM	35	#include <asm/mach-types.h>
9a4cd7a5 DM	36	#include <asm/mach/arch.h>
9e8a30dc	37	#include <asm/mach/time.h>
9a4cd7a5	38	#include <asm/mach/map.h>
9a4cd7a5 DM	39	#include <asm/page.h>
9a4cd7a5 DM	40	#include <asm/setup.h>
84677d11	41
3ed0bcb4	42	#include "board-mx31lite.h"
e3372474	43	#include "common.h"
a2ceeef5	44	#include "devices-imx31.h"
641dfe8b	45	#include "ehci.h"
50f2de61	46	#include "hardware.h"
267dd34c	47	#include "iomux-mx3.h"
39ef6340	48	#include "ulpi.h"
9a4cd7a5 DM	49
9a4cd7a5 DM	50	/*
b7d91a62	51	* This file contains the module-specific initialization routines.
9a4cd7a5 DM	52	*/
9a4cd7a5 DM	53
a854b8ab	54	static unsigned int mx31lite_pins[] = {
4ed9bb21 VZ	55	/* UART1 */
	56	MX31_PIN_CTS1__CTS1,
	57	MX31_PIN_RTS1__RTS1,
	58	MX31_PIN_TXD1__TXD1,
	59	MX31_PIN_RXD1__RXD1,
	60	/* SPI 0 */
	61	MX31_PIN_CSPI1_SCLK__SCLK,
	62	MX31_PIN_CSPI1_MOSI__MOSI,
	63	MX31_PIN_CSPI1_MISO__MISO,
	64	MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
	65	MX31_PIN_CSPI1_SS0__SS0,
	66	MX31_PIN_CSPI1_SS1__SS1,
	67	MX31_PIN_CSPI1_SS2__SS2,
3211705f ML	68	/* LAN9117 IRQ pin */
3211705f ML	69	IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO),
84677d11 DM	70	/* SPI 1 */
	71	MX31_PIN_CSPI2_SCLK__SCLK,
	72	MX31_PIN_CSPI2_MOSI__MOSI,
	73	MX31_PIN_CSPI2_MISO__MISO,
	74	MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
	75	MX31_PIN_CSPI2_SS0__SS0,
	76	MX31_PIN_CSPI2_SS1__SS1,
	77	MX31_PIN_CSPI2_SS2__SS2,
a854b8ab ML	78	};
a854b8ab ML	79
4ed9bb21 VZ	80	/* UART */
	81	static const struct imxuart_platform_data uart_pdata __initconst = {
	82	.flags = IMXUART_HAVE_RTSCTS,
	83	};
	84
	85	/* SPI */
	86	static int spi0_internal_chipselect[] = {
	87	MXC_SPI_CS(0),
	88	MXC_SPI_CS(1),
	89	MXC_SPI_CS(2),
	90	};
	91
	92	static const struct spi_imx_master spi0_pdata __initconst = {
	93	.chipselect = spi0_internal_chipselect,
	94	.num_chipselect = ARRAY_SIZE(spi0_internal_chipselect),
	95	};
	96
a2ceeef5 UKK	97	static const struct mxc_nand_platform_data
a2ceeef5 UKK	98	mx31lite_nand_board_info __initconst = {
183c7fff ML	99	.width = 1,
	100	.hw_ecc = 1,
	101	};
	102
3211705f ML	103	static struct smsc911x_platform_config smsc911x_config = {
	104	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
	105	.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
	106	.flags = SMSC911X_USE_16BIT,
	107	};
	108
	109	static struct resource smsc911x_resources[] = {
3f4f54b4	110	{
f568dd7f UKK	111	.start = MX31_CS4_BASE_ADDR,
f568dd7f UKK	112	.end = MX31_CS4_BASE_ADDR + 0x100,
3211705f	113	.flags = IORESOURCE_MEM,
3f4f54b4	114	}, {
ed175343	115	/* irq number is run-time assigned */
3211705f ML	116	.flags = IORESOURCE_IRQ,
	117	},
	118	};
	119
	120	static struct platform_device smsc911x_device = {
	121	.name = "smsc911x",
	122	.id = -1,
	123	.num_resources = ARRAY_SIZE(smsc911x_resources),
	124	.resource = smsc911x_resources,
	125	.dev = {
	126	.platform_data = &smsc911x_config,
	127	},
	128	};
	129
84677d11 DM	130	/*
	131	* SPI
	132	*
	133	* The MC13783 is the only hard-wired SPI device on the module.
	134	*/
	135
4ed9bb21	136	static int spi1_internal_chipselect[] = {
84677d11 DM	137	MXC_SPI_CS(0),
	138	};
	139
06606ff1	140	static const struct spi_imx_master spi1_pdata __initconst = {
4ed9bb21 VZ	141	.chipselect = spi1_internal_chipselect,
4ed9bb21 VZ	142	.num_chipselect = ARRAY_SIZE(spi1_internal_chipselect),
84677d11 DM	143	};
84677d11 DM	144
5836372e	145	static struct mc13xxx_platform_data mc13783_pdata __initdata = {
46621ebb	146	.flags = MC13XXX_USE_RTC,
84677d11 DM	147	};
	148
	149	static struct spi_board_info mc13783_spi_dev __initdata = {
	150	.modalias = "mc13783",
	151	.max_speed_hz = 1000000,
	152	.bus_num = 1,
	153	.chip_select = 0,
	154	.platform_data = &mc13783_pdata,
ed175343	155	/* irq number is run-time assigned */
84677d11 DM	156	};
84677d11 DM	157
a050c8e9 DM	158	/*
	159	* USB
	160	*/
	161
	162	#define USB_PAD_CFG (PAD_CTL_DRV_MAX \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS_CMOS \| \
	163	PAD_CTL_ODE_CMOS \| PAD_CTL_100K_PU)
	164
	165	static int usbh2_init(struct platform_device *pdev)
	166	{
	167	int pins[] = {
	168	MX31_PIN_USBH2_DATA0__USBH2_DATA0,
	169	MX31_PIN_USBH2_DATA1__USBH2_DATA1,
	170	MX31_PIN_USBH2_CLK__USBH2_CLK,
	171	MX31_PIN_USBH2_DIR__USBH2_DIR,
	172	MX31_PIN_USBH2_NXT__USBH2_NXT,
	173	MX31_PIN_USBH2_STP__USBH2_STP,
	174	};
	175
	176	mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H2");
	177
	178	mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
	179	mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
	180	mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
	181	mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
	182	mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
	183	mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
	184	mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
	185	mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
	186	mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
	187	mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
	188	mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
	189	mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);
	190
	191	mxc_iomux_set_gpr(MUX_PGP_UH2, true);
	192
	193	/* chip select */
	194	mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO),
	195	"USBH2_CS");
	196	gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS");
	197	gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0);
	198
4bd597b6 SH	199	mdelay(10);
	200
	201	return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
a050c8e9 DM	202	}
a050c8e9 DM	203
2d58de28	204	static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
a050c8e9 DM	205	.init = usbh2_init,
a050c8e9 DM	206	.portsc = MXC_EHCI_MODE_ULPI \| MXC_EHCI_UTMI_8BIT,
a050c8e9 DM	207	};
a050c8e9 DM	208
6d3e6601 DM	209	/*
	210	* NOR flash
	211	*/
	212
	213	static struct physmap_flash_data nor_flash_data = {
	214	.width = 2,
	215	};
	216
	217	static struct resource nor_flash_resource = {
	218	.start = 0xa0000000,
	219	.end = 0xa1ffffff,
	220	.flags = IORESOURCE_MEM,
	221	};
	222
	223	static struct platform_device physmap_flash_device = {
	224	.name = "physmap-flash",
	225	.id = 0,
	226	.dev = {
	227	.platform_data = &nor_flash_data,
	228	},
	229	.resource = &nor_flash_resource,
	230	.num_resources = 1,
	231	};
	232
9a4cd7a5 DM	233	/*
	234	* This structure defines the MX31 memory map.
	235	*/
	236	static struct map_desc mx31lite_io_desc[] __initdata = {
	237	{
f25d696a	238	.virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT,
f568dd7f UKK	239	.pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
f568dd7f UKK	240	.length = MX31_CS4_SIZE,
9a4cd7a5 DM	241	.type = MT_DEVICE
	242	}
	243	};
	244
	245	/*
	246	* Set up static virtual mappings.
	247	*/
	248	void __init mx31lite_map_io(void)
	249	{
cd4a05f9	250	mx31_map_io();
9a4cd7a5 DM	251	iotable_init(mx31lite_io_desc, ARRAY_SIZE(mx31lite_io_desc));
	252	}
	253
b7d91a62 DM	254	static int mx31lite_baseboard;
	255	core_param(mx31lite_baseboard, mx31lite_baseboard, int, 0444);
	256
da21d4dc FE	257	static struct regulator_consumer_supply dummy_supplies[] = {
	258	REGULATOR_SUPPLY("vdd33a", "smsc911x"),
	259	REGULATOR_SUPPLY("vddvario", "smsc911x"),
	260	};
	261
e134fb2b	262	static void __init mx31lite_init(void)
9a4cd7a5	263	{
b78d8e59 SG	264	imx31_soc_init();
b78d8e59 SG	265
a854b8ab ML	266	mxc_iomux_setup_multiple_pins(mx31lite_pins, ARRAY_SIZE(mx31lite_pins),
	267	"mx31lite");
	268
4ed9bb21 VZ	269	imx31_add_imx_uart0(&uart_pdata);
	270	imx31_add_spi_imx0(&spi0_pdata);
	271
6d3e6601 DM	272	/* NOR and NAND flash */
6d3e6601 DM	273	platform_device_register(&physmap_flash_device);
a2ceeef5	274	imx31_add_mxc_nand(&mx31lite_nand_board_info);
6d3e6601	275
06606ff1	276	imx31_add_spi_imx1(&spi1_pdata);
4ed9bb21 VZ	277
	278	regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
	279	}
	280
	281	static void __init mx31lite_late(void)
	282	{
	283	int ret;
	284
	285	if (mx31lite_baseboard == MX31LITE_DB)
	286	mx31lite_db_init();
	287
ed175343	288	mc13783_spi_dev.irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
84677d11	289	spi_register_board_info(&mc13783_spi_dev, 1);
3211705f	290
a050c8e9	291	/* USB */
48f6b099 SH	292	usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS \|
	293	ULPI_OTG_DRVVBUS_EXT);
	294	if (usbh2_pdata.otg)
	295	imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
a050c8e9	296
3211705f	297	/* SMSC9117 IRQ pin */
4f163eb8 SH	298	ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq");
4f163eb8 SH	299	if (ret)
75fd32b8	300	pr_warn("could not get LAN irq gpio\n");
4f163eb8 SH	301	else {
4f163eb8 SH	302	gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_SFS6));
ed175343 SG	303	smsc911x_resources[1].start =
	304	gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SFS6));
	305	smsc911x_resources[1].end =
	306	gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SFS6));
4f163eb8 SH	307	platform_device_register(&smsc911x_device);
4f163eb8 SH	308	}
9a4cd7a5 DM	309	}
9a4cd7a5 DM	310
9e8a30dc JB	311	static void __init mx31lite_timer_init(void)
9e8a30dc JB	312	{
30c730f8	313	mx31_clocks_init(26000000);
9e8a30dc JB	314	}
9e8a30dc JB	315
b7d91a62	316	MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
9a4cd7a5	317	/* Maintainer: Freescale Semiconductor, Inc. */
dc8f1907	318	.atag_offset = 0x100,
97976e22 UKK	319	.map_io = mx31lite_map_io,
	320	.init_early = imx31_init_early,
	321	.init_irq = mx31_init_irq,
6bb27d73	322	.init_time = mx31lite_timer_init,
e134fb2b	323	.init_machine = mx31lite_init,
4ed9bb21	324	.init_late = mx31lite_late,
65ea7884	325	.restart = mxc_restart,
9a4cd7a5	326	MACHINE_END