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Commit | Line | Data |
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a1f1c7ef | 1 | /* |
df595746 | 2 | * Copyright 2011-2014 Freescale Semiconductor, Inc. |
a1f1c7ef SG |
3 | * Copyright 2011 Linaro Ltd. |
4 | * | |
5 | * The code contained herein is licensed under the GNU General Public | |
6 | * License. You may obtain a copy of the GNU General Public License | |
7 | * Version 2 or later at the following locations: | |
8 | * | |
9 | * http://www.opensource.org/licenses/gpl-license.html | |
10 | * http://www.gnu.org/copyleft/gpl.html | |
11 | */ | |
12 | ||
9e8147bb | 13 | #include <linux/delay.h> |
a1f1c7ef SG |
14 | #include <linux/init.h> |
15 | #include <linux/io.h> | |
d48866fe | 16 | #include <linux/irq.h> |
df595746 | 17 | #include <linux/genalloc.h> |
d48866fe SG |
18 | #include <linux/mfd/syscon.h> |
19 | #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> | |
a1f1c7ef | 20 | #include <linux/of.h> |
9e8147bb | 21 | #include <linux/of_address.h> |
df595746 | 22 | #include <linux/of_platform.h> |
d48866fe | 23 | #include <linux/regmap.h> |
a1f1c7ef SG |
24 | #include <linux/suspend.h> |
25 | #include <asm/cacheflush.h> | |
df595746 | 26 | #include <asm/fncpy.h> |
a1f1c7ef SG |
27 | #include <asm/proc-fns.h> |
28 | #include <asm/suspend.h> | |
df595746 | 29 | #include <asm/tlb.h> |
a1f1c7ef | 30 | |
e3372474 | 31 | #include "common.h" |
50f2de61 | 32 | #include "hardware.h" |
e3372474 | 33 | |
9e8147bb SG |
34 | #define CCR 0x0 |
35 | #define BM_CCR_WB_COUNT (0x7 << 16) | |
36 | #define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21) | |
37 | #define BM_CCR_RBC_EN (0x1 << 27) | |
38 | ||
39 | #define CLPCR 0x54 | |
40 | #define BP_CLPCR_LPM 0 | |
41 | #define BM_CLPCR_LPM (0x3 << 0) | |
42 | #define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2) | |
43 | #define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) | |
44 | #define BM_CLPCR_SBYOS (0x1 << 6) | |
45 | #define BM_CLPCR_DIS_REF_OSC (0x1 << 7) | |
46 | #define BM_CLPCR_VSTBY (0x1 << 8) | |
47 | #define BP_CLPCR_STBY_COUNT 9 | |
48 | #define BM_CLPCR_STBY_COUNT (0x3 << 9) | |
49 | #define BM_CLPCR_COSC_PWRDOWN (0x1 << 11) | |
50 | #define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16) | |
51 | #define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17) | |
52 | #define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19) | |
53 | #define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21) | |
54 | #define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22) | |
55 | #define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23) | |
56 | #define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24) | |
57 | #define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25) | |
58 | #define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26) | |
59 | #define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27) | |
60 | ||
61 | #define CGPR 0x64 | |
fa6be65e | 62 | #define BM_CGPR_INT_MEM_CLK_LPM (0x1 << 17) |
9e8147bb | 63 | |
df595746 AH |
64 | #define MX6Q_SUSPEND_OCRAM_SIZE 0x1000 |
65 | #define MX6_MAX_MMDC_IO_NUM 33 | |
66 | ||
9e8147bb | 67 | static void __iomem *ccm_base; |
df595746 AH |
68 | static void __iomem *suspend_ocram_base; |
69 | static void (*imx6_suspend_in_ocram_fn)(void __iomem *ocram_vbase); | |
70 | ||
71 | /* | |
72 | * suspend ocram space layout: | |
73 | * ======================== high address ====================== | |
74 | * . | |
75 | * . | |
76 | * . | |
77 | * ^ | |
78 | * ^ | |
79 | * ^ | |
80 | * imx6_suspend code | |
81 | * PM_INFO structure(imx6_cpu_pm_info) | |
82 | * ======================== low address ======================= | |
83 | */ | |
84 | ||
85 | struct imx6_pm_base { | |
86 | phys_addr_t pbase; | |
87 | void __iomem *vbase; | |
88 | }; | |
89 | ||
90 | struct imx6_pm_socdata { | |
ec336b28 | 91 | u32 ddr_type; |
df595746 AH |
92 | const char *mmdc_compat; |
93 | const char *src_compat; | |
94 | const char *iomuxc_compat; | |
95 | const char *gpc_compat; | |
ee4a5f83 | 96 | const char *pl310_compat; |
df595746 AH |
97 | const u32 mmdc_io_num; |
98 | const u32 *mmdc_io_offset; | |
99 | }; | |
100 | ||
101 | static const u32 imx6q_mmdc_io_offset[] __initconst = { | |
102 | 0x5ac, 0x5b4, 0x528, 0x520, /* DQM0 ~ DQM3 */ | |
103 | 0x514, 0x510, 0x5bc, 0x5c4, /* DQM4 ~ DQM7 */ | |
104 | 0x56c, 0x578, 0x588, 0x594, /* CAS, RAS, SDCLK_0, SDCLK_1 */ | |
105 | 0x5a8, 0x5b0, 0x524, 0x51c, /* SDQS0 ~ SDQS3 */ | |
106 | 0x518, 0x50c, 0x5b8, 0x5c0, /* SDQS4 ~ SDQS7 */ | |
107 | 0x784, 0x788, 0x794, 0x79c, /* GPR_B0DS ~ GPR_B3DS */ | |
108 | 0x7a0, 0x7a4, 0x7a8, 0x748, /* GPR_B4DS ~ GPR_B7DS */ | |
109 | 0x59c, 0x5a0, 0x750, 0x774, /* SODT0, SODT1, MODE_CTL, MODE */ | |
110 | 0x74c, /* GPR_ADDS */ | |
111 | }; | |
112 | ||
da9e9261 AH |
113 | static const u32 imx6dl_mmdc_io_offset[] __initconst = { |
114 | 0x470, 0x474, 0x478, 0x47c, /* DQM0 ~ DQM3 */ | |
115 | 0x480, 0x484, 0x488, 0x48c, /* DQM4 ~ DQM7 */ | |
116 | 0x464, 0x490, 0x4ac, 0x4b0, /* CAS, RAS, SDCLK_0, SDCLK_1 */ | |
117 | 0x4bc, 0x4c0, 0x4c4, 0x4c8, /* DRAM_SDQS0 ~ DRAM_SDQS3 */ | |
118 | 0x4cc, 0x4d0, 0x4d4, 0x4d8, /* DRAM_SDQS4 ~ DRAM_SDQS7 */ | |
119 | 0x764, 0x770, 0x778, 0x77c, /* GPR_B0DS ~ GPR_B3DS */ | |
120 | 0x780, 0x784, 0x78c, 0x748, /* GPR_B4DS ~ GPR_B7DS */ | |
121 | 0x4b4, 0x4b8, 0x750, 0x760, /* SODT0, SODT1, MODE_CTL, MODE */ | |
122 | 0x74c, /* GPR_ADDS */ | |
123 | }; | |
124 | ||
64b08681 AH |
125 | static const u32 imx6sl_mmdc_io_offset[] __initconst = { |
126 | 0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */ | |
127 | 0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */ | |
128 | 0x300, 0x31c, 0x338, 0x5ac, /* CAS, RAS, SDCLK_0, GPR_ADDS */ | |
129 | 0x33c, 0x340, 0x5b0, 0x5c0, /* SODT0, SODT1, MODE_CTL, MODE */ | |
130 | 0x330, 0x334, 0x320, /* SDCKE0, SDCKE1, RESET */ | |
131 | }; | |
132 | ||
22021948 AH |
133 | static const u32 imx6sll_mmdc_io_offset[] __initconst = { |
134 | 0x294, 0x298, 0x29c, 0x2a0, /* DQM0 ~ DQM3 */ | |
135 | 0x544, 0x54c, 0x554, 0x558, /* GPR_B0DS ~ GPR_B3DS */ | |
136 | 0x530, 0x540, 0x2ac, 0x52c, /* MODE_CTL, MODE, SDCLK_0, GPR_ADDDS */ | |
137 | 0x2a4, 0x2a8, /* SDCKE0, SDCKE1*/ | |
138 | }; | |
139 | ||
ff843d62 AH |
140 | static const u32 imx6sx_mmdc_io_offset[] __initconst = { |
141 | 0x2ec, 0x2f0, 0x2f4, 0x2f8, /* DQM0 ~ DQM3 */ | |
142 | 0x60c, 0x610, 0x61c, 0x620, /* GPR_B0DS ~ GPR_B3DS */ | |
143 | 0x300, 0x2fc, 0x32c, 0x5f4, /* CAS, RAS, SDCLK_0, GPR_ADDS */ | |
144 | 0x310, 0x314, 0x5f8, 0x608, /* SODT0, SODT1, MODE_CTL, MODE */ | |
145 | 0x330, 0x334, 0x338, 0x33c, /* SDQS0 ~ SDQS3 */ | |
146 | }; | |
147 | ||
ee4a5f83 AH |
148 | static const u32 imx6ul_mmdc_io_offset[] __initconst = { |
149 | 0x244, 0x248, 0x24c, 0x250, /* DQM0, DQM1, RAS, CAS */ | |
150 | 0x27c, 0x498, 0x4a4, 0x490, /* SDCLK0, GPR_B0DS-B1DS, GPR_ADDS */ | |
151 | 0x280, 0x284, 0x260, 0x264, /* SDQS0~1, SODT0, SODT1 */ | |
152 | 0x494, 0x4b0, /* MODE_CTL, MODE, */ | |
153 | }; | |
154 | ||
df595746 | 155 | static const struct imx6_pm_socdata imx6q_pm_data __initconst = { |
df595746 AH |
156 | .mmdc_compat = "fsl,imx6q-mmdc", |
157 | .src_compat = "fsl,imx6q-src", | |
158 | .iomuxc_compat = "fsl,imx6q-iomuxc", | |
159 | .gpc_compat = "fsl,imx6q-gpc", | |
ee4a5f83 | 160 | .pl310_compat = "arm,pl310-cache", |
df595746 AH |
161 | .mmdc_io_num = ARRAY_SIZE(imx6q_mmdc_io_offset), |
162 | .mmdc_io_offset = imx6q_mmdc_io_offset, | |
163 | }; | |
164 | ||
da9e9261 | 165 | static const struct imx6_pm_socdata imx6dl_pm_data __initconst = { |
da9e9261 AH |
166 | .mmdc_compat = "fsl,imx6q-mmdc", |
167 | .src_compat = "fsl,imx6q-src", | |
168 | .iomuxc_compat = "fsl,imx6dl-iomuxc", | |
169 | .gpc_compat = "fsl,imx6q-gpc", | |
ee4a5f83 | 170 | .pl310_compat = "arm,pl310-cache", |
da9e9261 AH |
171 | .mmdc_io_num = ARRAY_SIZE(imx6dl_mmdc_io_offset), |
172 | .mmdc_io_offset = imx6dl_mmdc_io_offset, | |
173 | }; | |
174 | ||
64b08681 | 175 | static const struct imx6_pm_socdata imx6sl_pm_data __initconst = { |
64b08681 AH |
176 | .mmdc_compat = "fsl,imx6sl-mmdc", |
177 | .src_compat = "fsl,imx6sl-src", | |
178 | .iomuxc_compat = "fsl,imx6sl-iomuxc", | |
179 | .gpc_compat = "fsl,imx6sl-gpc", | |
ee4a5f83 | 180 | .pl310_compat = "arm,pl310-cache", |
64b08681 AH |
181 | .mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset), |
182 | .mmdc_io_offset = imx6sl_mmdc_io_offset, | |
183 | }; | |
184 | ||
22021948 AH |
185 | static const struct imx6_pm_socdata imx6sll_pm_data __initconst = { |
186 | .mmdc_compat = "fsl,imx6sll-mmdc", | |
187 | .src_compat = "fsl,imx6sll-src", | |
188 | .iomuxc_compat = "fsl,imx6sll-iomuxc", | |
189 | .gpc_compat = "fsl,imx6sll-gpc", | |
190 | .pl310_compat = "arm,pl310-cache", | |
191 | .mmdc_io_num = ARRAY_SIZE(imx6sll_mmdc_io_offset), | |
192 | .mmdc_io_offset = imx6sll_mmdc_io_offset, | |
193 | }; | |
194 | ||
ff843d62 | 195 | static const struct imx6_pm_socdata imx6sx_pm_data __initconst = { |
ff843d62 AH |
196 | .mmdc_compat = "fsl,imx6sx-mmdc", |
197 | .src_compat = "fsl,imx6sx-src", | |
198 | .iomuxc_compat = "fsl,imx6sx-iomuxc", | |
199 | .gpc_compat = "fsl,imx6sx-gpc", | |
ee4a5f83 | 200 | .pl310_compat = "arm,pl310-cache", |
ff843d62 AH |
201 | .mmdc_io_num = ARRAY_SIZE(imx6sx_mmdc_io_offset), |
202 | .mmdc_io_offset = imx6sx_mmdc_io_offset, | |
203 | }; | |
204 | ||
ee4a5f83 AH |
205 | static const struct imx6_pm_socdata imx6ul_pm_data __initconst = { |
206 | .mmdc_compat = "fsl,imx6ul-mmdc", | |
207 | .src_compat = "fsl,imx6ul-src", | |
208 | .iomuxc_compat = "fsl,imx6ul-iomuxc", | |
209 | .gpc_compat = "fsl,imx6ul-gpc", | |
210 | .pl310_compat = NULL, | |
211 | .mmdc_io_num = ARRAY_SIZE(imx6ul_mmdc_io_offset), | |
212 | .mmdc_io_offset = imx6ul_mmdc_io_offset, | |
213 | }; | |
214 | ||
df595746 AH |
215 | /* |
216 | * This structure is for passing necessary data for low level ocram | |
217 | * suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct | |
218 | * definition is changed, the offset definition in | |
219 | * arch/arm/mach-imx/suspend-imx6.S must be also changed accordingly, | |
220 | * otherwise, the suspend to ocram function will be broken! | |
221 | */ | |
222 | struct imx6_cpu_pm_info { | |
223 | phys_addr_t pbase; /* The physical address of pm_info. */ | |
224 | phys_addr_t resume_addr; /* The physical resume address for asm code */ | |
ec336b28 | 225 | u32 ddr_type; |
df595746 AH |
226 | u32 pm_info_size; /* Size of pm_info. */ |
227 | struct imx6_pm_base mmdc_base; | |
228 | struct imx6_pm_base src_base; | |
229 | struct imx6_pm_base iomuxc_base; | |
230 | struct imx6_pm_base ccm_base; | |
231 | struct imx6_pm_base gpc_base; | |
232 | struct imx6_pm_base l2_base; | |
233 | u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */ | |
234 | u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */ | |
235 | } __aligned(8); | |
9e8147bb | 236 | |
8765caa5 | 237 | void imx6_set_int_mem_clk_lpm(bool enable) |
9e8147bb SG |
238 | { |
239 | u32 val = readl_relaxed(ccm_base + CGPR); | |
240 | ||
dfea953a AH |
241 | val &= ~BM_CGPR_INT_MEM_CLK_LPM; |
242 | if (enable) | |
243 | val |= BM_CGPR_INT_MEM_CLK_LPM; | |
9e8147bb SG |
244 | writel_relaxed(val, ccm_base + CGPR); |
245 | } | |
246 | ||
05136f08 | 247 | void imx6_enable_rbc(bool enable) |
9e8147bb SG |
248 | { |
249 | u32 val; | |
9e8147bb | 250 | |
9e8147bb SG |
251 | /* |
252 | * need to mask all interrupts in GPC before | |
253 | * operating RBC configurations | |
254 | */ | |
255 | imx_gpc_mask_all(); | |
256 | ||
257 | /* configure RBC enable bit */ | |
258 | val = readl_relaxed(ccm_base + CCR); | |
259 | val &= ~BM_CCR_RBC_EN; | |
260 | val |= enable ? BM_CCR_RBC_EN : 0; | |
261 | writel_relaxed(val, ccm_base + CCR); | |
262 | ||
263 | /* configure RBC count */ | |
264 | val = readl_relaxed(ccm_base + CCR); | |
265 | val &= ~BM_CCR_RBC_BYPASS_COUNT; | |
266 | val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0; | |
267 | writel(val, ccm_base + CCR); | |
268 | ||
269 | /* | |
270 | * need to delay at least 2 cycles of CKIL(32K) | |
271 | * due to hardware design requirement, which is | |
272 | * ~61us, here we use 65us for safe | |
273 | */ | |
274 | udelay(65); | |
275 | ||
276 | /* restore GPC interrupt mask settings */ | |
277 | imx_gpc_restore_all(); | |
9e8147bb SG |
278 | } |
279 | ||
280 | static void imx6q_enable_wb(bool enable) | |
281 | { | |
282 | u32 val; | |
9e8147bb SG |
283 | |
284 | /* configure well bias enable bit */ | |
285 | val = readl_relaxed(ccm_base + CLPCR); | |
286 | val &= ~BM_CLPCR_WB_PER_AT_LPM; | |
287 | val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0; | |
288 | writel_relaxed(val, ccm_base + CLPCR); | |
289 | ||
290 | /* configure well bias count */ | |
291 | val = readl_relaxed(ccm_base + CCR); | |
292 | val &= ~BM_CCR_WB_COUNT; | |
293 | val |= enable ? BM_CCR_WB_COUNT : 0; | |
294 | writel_relaxed(val, ccm_base + CCR); | |
9e8147bb SG |
295 | } |
296 | ||
8fb76a07 | 297 | int imx6_set_lpm(enum mxc_cpu_pwr_mode mode) |
9e8147bb SG |
298 | { |
299 | u32 val = readl_relaxed(ccm_base + CLPCR); | |
300 | ||
301 | val &= ~BM_CLPCR_LPM; | |
302 | switch (mode) { | |
303 | case WAIT_CLOCKED: | |
9e8147bb SG |
304 | break; |
305 | case WAIT_UNCLOCKED: | |
306 | val |= 0x1 << BP_CLPCR_LPM; | |
307 | val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM; | |
308 | break; | |
309 | case STOP_POWER_ON: | |
310 | val |= 0x2 << BP_CLPCR_LPM; | |
80c0ecdc AH |
311 | val &= ~BM_CLPCR_VSTBY; |
312 | val &= ~BM_CLPCR_SBYOS; | |
313 | if (cpu_is_imx6sl()) | |
314 | val |= BM_CLPCR_BYPASS_PMIC_READY; | |
bf5a01d7 | 315 | if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() || |
c90dec00 | 316 | cpu_is_imx6ull() || cpu_is_imx6sll() || cpu_is_imx6ulz()) |
80c0ecdc AH |
317 | val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; |
318 | else | |
319 | val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; | |
9e8147bb SG |
320 | break; |
321 | case WAIT_UNCLOCKED_POWER_OFF: | |
322 | val |= 0x1 << BP_CLPCR_LPM; | |
323 | val &= ~BM_CLPCR_VSTBY; | |
324 | val &= ~BM_CLPCR_SBYOS; | |
325 | break; | |
326 | case STOP_POWER_OFF: | |
327 | val |= 0x2 << BP_CLPCR_LPM; | |
328 | val |= 0x3 << BP_CLPCR_STBY_COUNT; | |
329 | val |= BM_CLPCR_VSTBY; | |
330 | val |= BM_CLPCR_SBYOS; | |
8aade778 | 331 | if (cpu_is_imx6sl() || cpu_is_imx6sx()) |
9ba64fe3 | 332 | val |= BM_CLPCR_BYPASS_PMIC_READY; |
bf5a01d7 | 333 | if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() || |
c90dec00 | 334 | cpu_is_imx6ull() || cpu_is_imx6sll() || cpu_is_imx6ulz()) |
9ba64fe3 | 335 | val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; |
ff843d62 | 336 | else |
9ba64fe3 | 337 | val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; |
9e8147bb SG |
338 | break; |
339 | default: | |
340 | return -EINVAL; | |
341 | } | |
342 | ||
d48866fe | 343 | /* |
48c95841 AH |
344 | * ERR007265: CCM: When improper low-power sequence is used, |
345 | * the SoC enters low power mode before the ARM core executes WFI. | |
346 | * | |
347 | * Software workaround: | |
348 | * 1) Software should trigger IRQ #32 (IOMUX) to be always pending | |
349 | * by setting IOMUX_GPR1_GINT. | |
350 | * 2) Software should then unmask IRQ #32 in GPC before setting CCM | |
351 | * Low-Power mode. | |
352 | * 3) Software should mask IRQ #32 right after CCM Low-Power mode | |
353 | * is set (set bits 0-1 of CCM_CLPCR). | |
b923ff6a MZ |
354 | * |
355 | * Note that IRQ #32 is GIC SPI #0. | |
d48866fe | 356 | */ |
8f3e2d2c KO |
357 | if (mode != WAIT_CLOCKED) |
358 | imx_gpc_hwirq_unmask(0); | |
9e8147bb | 359 | writel_relaxed(val, ccm_base + CLPCR); |
8f3e2d2c KO |
360 | if (mode != WAIT_CLOCKED) |
361 | imx_gpc_hwirq_mask(0); | |
9e8147bb SG |
362 | |
363 | return 0; | |
364 | } | |
365 | ||
a1f1c7ef SG |
366 | static int imx6q_suspend_finish(unsigned long val) |
367 | { | |
df595746 AH |
368 | if (!imx6_suspend_in_ocram_fn) { |
369 | cpu_do_idle(); | |
370 | } else { | |
371 | /* | |
372 | * call low level suspend function in ocram, | |
373 | * as we need to float DDR IO. | |
374 | */ | |
375 | local_flush_tlb_all(); | |
ee4a5f83 AH |
376 | /* check if need to flush internal L2 cache */ |
377 | if (!((struct imx6_cpu_pm_info *) | |
378 | suspend_ocram_base)->l2_base.vbase) | |
379 | flush_cache_all(); | |
df595746 AH |
380 | imx6_suspend_in_ocram_fn(suspend_ocram_base); |
381 | } | |
382 | ||
a1f1c7ef SG |
383 | return 0; |
384 | } | |
385 | ||
386 | static int imx6q_pm_enter(suspend_state_t state) | |
387 | { | |
388 | switch (state) { | |
80c0ecdc | 389 | case PM_SUSPEND_STANDBY: |
8fb76a07 | 390 | imx6_set_lpm(STOP_POWER_ON); |
8765caa5 | 391 | imx6_set_int_mem_clk_lpm(true); |
80c0ecdc AH |
392 | imx_gpc_pre_suspend(false); |
393 | if (cpu_is_imx6sl()) | |
394 | imx6sl_set_wait_clk(true); | |
395 | /* Zzz ... */ | |
396 | cpu_do_idle(); | |
397 | if (cpu_is_imx6sl()) | |
398 | imx6sl_set_wait_clk(false); | |
399 | imx_gpc_post_resume(); | |
8fb76a07 | 400 | imx6_set_lpm(WAIT_CLOCKED); |
80c0ecdc | 401 | break; |
a1f1c7ef | 402 | case PM_SUSPEND_MEM: |
8fb76a07 | 403 | imx6_set_lpm(STOP_POWER_OFF); |
8765caa5 | 404 | imx6_set_int_mem_clk_lpm(false); |
1d674a73 | 405 | imx6q_enable_wb(true); |
df595746 AH |
406 | /* |
407 | * For suspend into ocram, asm code already take care of | |
408 | * RBC setting, so we do NOT need to do that here. | |
409 | */ | |
410 | if (!imx6_suspend_in_ocram_fn) | |
05136f08 | 411 | imx6_enable_rbc(true); |
80c0ecdc | 412 | imx_gpc_pre_suspend(true); |
e95dddb3 | 413 | imx_anatop_pre_suspend(); |
a1f1c7ef SG |
414 | /* Zzz ... */ |
415 | cpu_suspend(0, imx6q_suspend_finish); | |
9ba64fe3 SG |
416 | if (cpu_is_imx6q() || cpu_is_imx6dl()) |
417 | imx_smp_prepare(); | |
e95dddb3 | 418 | imx_anatop_post_resume(); |
a1f1c7ef | 419 | imx_gpc_post_resume(); |
05136f08 | 420 | imx6_enable_rbc(false); |
1d674a73 | 421 | imx6q_enable_wb(false); |
8765caa5 | 422 | imx6_set_int_mem_clk_lpm(true); |
8fb76a07 | 423 | imx6_set_lpm(WAIT_CLOCKED); |
a1f1c7ef SG |
424 | break; |
425 | default: | |
426 | return -EINVAL; | |
427 | } | |
428 | ||
429 | return 0; | |
430 | } | |
431 | ||
80c0ecdc AH |
432 | static int imx6q_pm_valid(suspend_state_t state) |
433 | { | |
434 | return (state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM); | |
435 | } | |
436 | ||
a1f1c7ef SG |
437 | static const struct platform_suspend_ops imx6q_pm_ops = { |
438 | .enter = imx6q_pm_enter, | |
80c0ecdc | 439 | .valid = imx6q_pm_valid, |
a1f1c7ef SG |
440 | }; |
441 | ||
df595746 AH |
442 | static int __init imx6_pm_get_base(struct imx6_pm_base *base, |
443 | const char *compat) | |
444 | { | |
445 | struct device_node *node; | |
446 | struct resource res; | |
447 | int ret = 0; | |
448 | ||
449 | node = of_find_compatible_node(NULL, NULL, compat); | |
258172f9 FE |
450 | if (!node) |
451 | return -ENODEV; | |
df595746 AH |
452 | |
453 | ret = of_address_to_resource(node, 0, &res); | |
454 | if (ret) | |
455 | goto put_node; | |
456 | ||
457 | base->pbase = res.start; | |
458 | base->vbase = ioremap(res.start, resource_size(&res)); | |
459 | if (!base->vbase) | |
460 | ret = -ENOMEM; | |
461 | ||
462 | put_node: | |
463 | of_node_put(node); | |
df595746 AH |
464 | return ret; |
465 | } | |
466 | ||
afc51f46 | 467 | static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata) |
df595746 AH |
468 | { |
469 | phys_addr_t ocram_pbase; | |
470 | struct device_node *node; | |
471 | struct platform_device *pdev; | |
472 | struct imx6_cpu_pm_info *pm_info; | |
473 | struct gen_pool *ocram_pool; | |
474 | unsigned long ocram_base; | |
475 | int i, ret = 0; | |
476 | const u32 *mmdc_offset_array; | |
477 | ||
afc51f46 SG |
478 | suspend_set_ops(&imx6q_pm_ops); |
479 | ||
df595746 AH |
480 | if (!socdata) { |
481 | pr_warn("%s: invalid argument!\n", __func__); | |
482 | return -EINVAL; | |
483 | } | |
484 | ||
485 | node = of_find_compatible_node(NULL, NULL, "mmio-sram"); | |
486 | if (!node) { | |
487 | pr_warn("%s: failed to find ocram node!\n", __func__); | |
488 | return -ENODEV; | |
489 | } | |
490 | ||
491 | pdev = of_find_device_by_node(node); | |
492 | if (!pdev) { | |
493 | pr_warn("%s: failed to find ocram device!\n", __func__); | |
494 | ret = -ENODEV; | |
495 | goto put_node; | |
496 | } | |
497 | ||
73858173 | 498 | ocram_pool = gen_pool_get(&pdev->dev, NULL); |
df595746 AH |
499 | if (!ocram_pool) { |
500 | pr_warn("%s: ocram pool unavailable!\n", __func__); | |
501 | ret = -ENODEV; | |
502 | goto put_node; | |
503 | } | |
504 | ||
505 | ocram_base = gen_pool_alloc(ocram_pool, MX6Q_SUSPEND_OCRAM_SIZE); | |
506 | if (!ocram_base) { | |
507 | pr_warn("%s: unable to alloc ocram!\n", __func__); | |
508 | ret = -ENOMEM; | |
509 | goto put_node; | |
510 | } | |
511 | ||
512 | ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base); | |
513 | ||
514 | suspend_ocram_base = __arm_ioremap_exec(ocram_pbase, | |
515 | MX6Q_SUSPEND_OCRAM_SIZE, false); | |
516 | ||
ee4a5f83 | 517 | memset(suspend_ocram_base, 0, sizeof(*pm_info)); |
df595746 AH |
518 | pm_info = suspend_ocram_base; |
519 | pm_info->pbase = ocram_pbase; | |
64fc2a94 | 520 | pm_info->resume_addr = __pa_symbol(v7_cpu_resume); |
df595746 AH |
521 | pm_info->pm_info_size = sizeof(*pm_info); |
522 | ||
523 | /* | |
524 | * ccm physical address is not used by asm code currently, | |
f0b478b5 | 525 | * so get ccm virtual address directly. |
df595746 AH |
526 | */ |
527 | pm_info->ccm_base.vbase = ccm_base; | |
528 | ||
529 | ret = imx6_pm_get_base(&pm_info->mmdc_base, socdata->mmdc_compat); | |
530 | if (ret) { | |
531 | pr_warn("%s: failed to get mmdc base %d!\n", __func__, ret); | |
532 | goto put_node; | |
533 | } | |
534 | ||
535 | ret = imx6_pm_get_base(&pm_info->src_base, socdata->src_compat); | |
536 | if (ret) { | |
537 | pr_warn("%s: failed to get src base %d!\n", __func__, ret); | |
538 | goto src_map_failed; | |
539 | } | |
540 | ||
541 | ret = imx6_pm_get_base(&pm_info->iomuxc_base, socdata->iomuxc_compat); | |
542 | if (ret) { | |
543 | pr_warn("%s: failed to get iomuxc base %d!\n", __func__, ret); | |
544 | goto iomuxc_map_failed; | |
545 | } | |
546 | ||
547 | ret = imx6_pm_get_base(&pm_info->gpc_base, socdata->gpc_compat); | |
548 | if (ret) { | |
549 | pr_warn("%s: failed to get gpc base %d!\n", __func__, ret); | |
550 | goto gpc_map_failed; | |
551 | } | |
552 | ||
ee4a5f83 AH |
553 | if (socdata->pl310_compat) { |
554 | ret = imx6_pm_get_base(&pm_info->l2_base, socdata->pl310_compat); | |
555 | if (ret) { | |
556 | pr_warn("%s: failed to get pl310-cache base %d!\n", | |
557 | __func__, ret); | |
558 | goto pl310_cache_map_failed; | |
559 | } | |
df595746 AH |
560 | } |
561 | ||
ec336b28 | 562 | pm_info->ddr_type = imx_mmdc_get_ddr_type(); |
df595746 AH |
563 | pm_info->mmdc_io_num = socdata->mmdc_io_num; |
564 | mmdc_offset_array = socdata->mmdc_io_offset; | |
565 | ||
566 | for (i = 0; i < pm_info->mmdc_io_num; i++) { | |
567 | pm_info->mmdc_io_val[i][0] = | |
568 | mmdc_offset_array[i]; | |
569 | pm_info->mmdc_io_val[i][1] = | |
570 | readl_relaxed(pm_info->iomuxc_base.vbase + | |
571 | mmdc_offset_array[i]); | |
572 | } | |
573 | ||
574 | imx6_suspend_in_ocram_fn = fncpy( | |
575 | suspend_ocram_base + sizeof(*pm_info), | |
576 | &imx6_suspend, | |
577 | MX6Q_SUSPEND_OCRAM_SIZE - sizeof(*pm_info)); | |
578 | ||
579 | goto put_node; | |
580 | ||
581 | pl310_cache_map_failed: | |
cfefb762 | 582 | iounmap(pm_info->gpc_base.vbase); |
df595746 | 583 | gpc_map_failed: |
cfefb762 | 584 | iounmap(pm_info->iomuxc_base.vbase); |
df595746 | 585 | iomuxc_map_failed: |
cfefb762 | 586 | iounmap(pm_info->src_base.vbase); |
df595746 | 587 | src_map_failed: |
cfefb762 | 588 | iounmap(pm_info->mmdc_base.vbase); |
df595746 AH |
589 | put_node: |
590 | of_node_put(node); | |
591 | ||
592 | return ret; | |
593 | } | |
594 | ||
595 | static void __init imx6_pm_common_init(const struct imx6_pm_socdata | |
596 | *socdata) | |
a1f1c7ef | 597 | { |
d48866fe | 598 | struct regmap *gpr; |
df595746 | 599 | int ret; |
d48866fe | 600 | |
9e8147bb SG |
601 | WARN_ON(!ccm_base); |
602 | ||
110666dc SG |
603 | if (IS_ENABLED(CONFIG_SUSPEND)) { |
604 | ret = imx6q_suspend_init(socdata); | |
605 | if (ret) | |
606 | pr_warn("%s: No DDR LPM support with suspend %d!\n", | |
607 | __func__, ret); | |
608 | } | |
df595746 | 609 | |
d48866fe | 610 | /* |
48c95841 | 611 | * This is for SW workaround step #1 of ERR007265, see comments |
8fb76a07 | 612 | * in imx6_set_lpm for details of this errata. |
d48866fe SG |
613 | * Force IOMUXC irq pending, so that the interrupt to GPC can be |
614 | * used to deassert dsm_request signal when the signal gets | |
615 | * asserted unexpectedly. | |
616 | */ | |
617 | gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); | |
618 | if (!IS_ERR(gpr)) | |
619 | regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT, | |
620 | IMX6Q_GPR1_GINT); | |
a1f1c7ef | 621 | } |
df595746 | 622 | |
8148d213 OR |
623 | static void imx6_pm_stby_poweroff(void) |
624 | { | |
625 | imx6_set_lpm(STOP_POWER_OFF); | |
626 | imx6q_suspend_finish(0); | |
627 | ||
628 | mdelay(1000); | |
629 | ||
630 | pr_emerg("Unable to poweroff system\n"); | |
631 | } | |
632 | ||
633 | static int imx6_pm_stby_poweroff_probe(void) | |
634 | { | |
635 | if (pm_power_off) { | |
d75f773c | 636 | pr_warn("%s: pm_power_off already claimed %p %ps!\n", |
8148d213 OR |
637 | __func__, pm_power_off, pm_power_off); |
638 | return -EBUSY; | |
639 | } | |
640 | ||
641 | pm_power_off = imx6_pm_stby_poweroff; | |
642 | return 0; | |
643 | } | |
644 | ||
35e2916f SG |
645 | void __init imx6_pm_ccm_init(const char *ccm_compat) |
646 | { | |
647 | struct device_node *np; | |
648 | u32 val; | |
649 | ||
650 | np = of_find_compatible_node(NULL, NULL, ccm_compat); | |
651 | ccm_base = of_iomap(np, 0); | |
652 | BUG_ON(!ccm_base); | |
653 | ||
654 | /* | |
655 | * Initialize CCM_CLPCR_LPM into RUN mode to avoid ARM core | |
656 | * clock being shut down unexpectedly by WAIT mode. | |
657 | */ | |
658 | val = readl_relaxed(ccm_base + CLPCR); | |
659 | val &= ~BM_CLPCR_LPM; | |
660 | writel_relaxed(val, ccm_base + CLPCR); | |
8148d213 OR |
661 | |
662 | if (of_property_read_bool(np, "fsl,pmic-stby-poweroff")) | |
663 | imx6_pm_stby_poweroff_probe(); | |
35e2916f SG |
664 | } |
665 | ||
df595746 AH |
666 | void __init imx6q_pm_init(void) |
667 | { | |
668 | imx6_pm_common_init(&imx6q_pm_data); | |
669 | } | |
670 | ||
671 | void __init imx6dl_pm_init(void) | |
672 | { | |
da9e9261 | 673 | imx6_pm_common_init(&imx6dl_pm_data); |
df595746 AH |
674 | } |
675 | ||
676 | void __init imx6sl_pm_init(void) | |
677 | { | |
d082852f AH |
678 | struct regmap *gpr; |
679 | ||
680 | if (cpu_is_imx6sl()) { | |
22021948 | 681 | imx6_pm_common_init(&imx6sl_pm_data); |
d082852f | 682 | } else { |
22021948 | 683 | imx6_pm_common_init(&imx6sll_pm_data); |
d082852f AH |
684 | gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); |
685 | if (!IS_ERR(gpr)) | |
686 | regmap_update_bits(gpr, IOMUXC_GPR5, | |
687 | IMX6SLL_GPR5_AFCG_X_BYPASS_MASK, 0); | |
688 | } | |
df595746 | 689 | } |
ff843d62 AH |
690 | |
691 | void __init imx6sx_pm_init(void) | |
692 | { | |
693 | imx6_pm_common_init(&imx6sx_pm_data); | |
694 | } | |
ee4a5f83 AH |
695 | |
696 | void __init imx6ul_pm_init(void) | |
697 | { | |
698 | imx6_pm_common_init(&imx6ul_pm_data); | |
699 | } |