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9fbbe689 SG |
1 | /* |
2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
3 | * Copyright 2011 Linaro Ltd. | |
4 | * | |
5 | * The code contained herein is licensed under the GNU General Public | |
6 | * License. You may obtain a copy of the GNU General Public License | |
7 | * Version 2 or later at the following locations: | |
8 | * | |
9 | * http://www.opensource.org/licenses/gpl-license.html | |
10 | * http://www.gnu.org/copyleft/gpl.html | |
11 | */ | |
12 | ||
13 | #include <linux/init.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/of.h> | |
16 | #include <linux/of_address.h> | |
02985b94 | 17 | #include <linux/reset-controller.h> |
eaa142ca | 18 | #include <linux/smp.h> |
eb50439b | 19 | #include <asm/smp_plat.h> |
9fbbe689 SG |
20 | |
21 | #define SRC_SCR 0x000 | |
22 | #define SRC_GPR1 0x020 | |
0575fb75 | 23 | #define BP_SRC_SCR_WARM_RESET_ENABLE 0 |
02985b94 PZ |
24 | #define BP_SRC_SCR_SW_GPU_RST 1 |
25 | #define BP_SRC_SCR_SW_VPU_RST 2 | |
26 | #define BP_SRC_SCR_SW_IPU1_RST 3 | |
27 | #define BP_SRC_SCR_SW_OPEN_VG_RST 4 | |
28 | #define BP_SRC_SCR_SW_IPU2_RST 12 | |
9fbbe689 SG |
29 | #define BP_SRC_SCR_CORE1_RST 14 |
30 | #define BP_SRC_SCR_CORE1_ENABLE 22 | |
31 | ||
32 | static void __iomem *src_base; | |
02985b94 PZ |
33 | static DEFINE_SPINLOCK(scr_lock); |
34 | ||
35 | static const int sw_reset_bits[5] = { | |
36 | BP_SRC_SCR_SW_GPU_RST, | |
37 | BP_SRC_SCR_SW_VPU_RST, | |
38 | BP_SRC_SCR_SW_IPU1_RST, | |
39 | BP_SRC_SCR_SW_OPEN_VG_RST, | |
40 | BP_SRC_SCR_SW_IPU2_RST | |
41 | }; | |
42 | ||
43 | static int imx_src_reset_module(struct reset_controller_dev *rcdev, | |
44 | unsigned long sw_reset_idx) | |
45 | { | |
46 | unsigned long timeout; | |
47 | unsigned long flags; | |
48 | int bit; | |
49 | u32 val; | |
50 | ||
51 | if (!src_base) | |
52 | return -ENODEV; | |
53 | ||
54 | if (sw_reset_idx >= ARRAY_SIZE(sw_reset_bits)) | |
55 | return -EINVAL; | |
56 | ||
57 | bit = 1 << sw_reset_bits[sw_reset_idx]; | |
58 | ||
59 | spin_lock_irqsave(&scr_lock, flags); | |
60 | val = readl_relaxed(src_base + SRC_SCR); | |
61 | val |= bit; | |
62 | writel_relaxed(val, src_base + SRC_SCR); | |
63 | spin_unlock_irqrestore(&scr_lock, flags); | |
64 | ||
65 | timeout = jiffies + msecs_to_jiffies(1000); | |
66 | while (readl(src_base + SRC_SCR) & bit) { | |
67 | if (time_after(jiffies, timeout)) | |
68 | return -ETIME; | |
69 | cpu_relax(); | |
70 | } | |
71 | ||
72 | return 0; | |
73 | } | |
74 | ||
75 | static struct reset_control_ops imx_src_ops = { | |
76 | .reset = imx_src_reset_module, | |
77 | }; | |
78 | ||
79 | static struct reset_controller_dev imx_reset_controller = { | |
80 | .ops = &imx_src_ops, | |
81 | .nr_resets = ARRAY_SIZE(sw_reset_bits), | |
82 | }; | |
9fbbe689 SG |
83 | |
84 | void imx_enable_cpu(int cpu, bool enable) | |
85 | { | |
86 | u32 mask, val; | |
87 | ||
eaa142ca | 88 | cpu = cpu_logical_map(cpu); |
9fbbe689 | 89 | mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1); |
02985b94 | 90 | spin_lock(&scr_lock); |
9fbbe689 SG |
91 | val = readl_relaxed(src_base + SRC_SCR); |
92 | val = enable ? val | mask : val & ~mask; | |
93 | writel_relaxed(val, src_base + SRC_SCR); | |
02985b94 | 94 | spin_unlock(&scr_lock); |
9fbbe689 SG |
95 | } |
96 | ||
97 | void imx_set_cpu_jump(int cpu, void *jump_addr) | |
98 | { | |
eaa142ca | 99 | cpu = cpu_logical_map(cpu); |
0a60cb14 | 100 | writel_relaxed(virt_to_phys(jump_addr), |
9fbbe689 SG |
101 | src_base + SRC_GPR1 + cpu * 8); |
102 | } | |
103 | ||
2f3edfd7 SG |
104 | u32 imx_get_cpu_arg(int cpu) |
105 | { | |
106 | cpu = cpu_logical_map(cpu); | |
107 | return readl_relaxed(src_base + SRC_GPR1 + cpu * 8 + 4); | |
108 | } | |
109 | ||
110 | void imx_set_cpu_arg(int cpu, u32 arg) | |
111 | { | |
112 | cpu = cpu_logical_map(cpu); | |
113 | writel_relaxed(arg, src_base + SRC_GPR1 + cpu * 8 + 4); | |
114 | } | |
115 | ||
0575fb75 SG |
116 | void imx_src_prepare_restart(void) |
117 | { | |
118 | u32 val; | |
119 | ||
120 | /* clear enable bits of secondary cores */ | |
02985b94 | 121 | spin_lock(&scr_lock); |
0575fb75 SG |
122 | val = readl_relaxed(src_base + SRC_SCR); |
123 | val &= ~(0x7 << BP_SRC_SCR_CORE1_ENABLE); | |
124 | writel_relaxed(val, src_base + SRC_SCR); | |
02985b94 | 125 | spin_unlock(&scr_lock); |
0575fb75 SG |
126 | |
127 | /* clear persistent entry register of primary core */ | |
128 | writel_relaxed(0, src_base + SRC_GPR1); | |
129 | } | |
130 | ||
9fbbe689 SG |
131 | void __init imx_src_init(void) |
132 | { | |
133 | struct device_node *np; | |
0575fb75 | 134 | u32 val; |
9fbbe689 SG |
135 | |
136 | np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-src"); | |
137 | src_base = of_iomap(np, 0); | |
138 | WARN_ON(!src_base); | |
0575fb75 | 139 | |
02985b94 PZ |
140 | imx_reset_controller.of_node = np; |
141 | reset_controller_register(&imx_reset_controller); | |
142 | ||
0575fb75 SG |
143 | /* |
144 | * force warm reset sources to generate cold reset | |
145 | * for a more reliable restart | |
146 | */ | |
02985b94 | 147 | spin_lock(&scr_lock); |
0575fb75 SG |
148 | val = readl_relaxed(src_base + SRC_SCR); |
149 | val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE); | |
150 | writel_relaxed(val, src_base + SRC_SCR); | |
02985b94 | 151 | spin_unlock(&scr_lock); |
9fbbe689 | 152 | } |