[mirror_ubuntu-hirsute-kernel.git] / arch / arm / mach-imx / src.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2011 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 */

#include <linux/init.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/reset-controller.h>
#include <linux/smp.h>
#include <asm/smp_plat.h>
#include "common.h"

#define SRC_SCR				0x000
#define SRC_GPR1			0x020
#define BP_SRC_SCR_WARM_RESET_ENABLE	0
#define BP_SRC_SCR_SW_GPU_RST		1
#define BP_SRC_SCR_SW_VPU_RST		2
#define BP_SRC_SCR_SW_IPU1_RST		3
#define BP_SRC_SCR_SW_OPEN_VG_RST	4
#define BP_SRC_SCR_SW_IPU2_RST		12
#define BP_SRC_SCR_CORE1_RST		14
#define BP_SRC_SCR_CORE1_ENABLE		22

static void __iomem *src_base;
static DEFINE_SPINLOCK(scr_lock);

static const int sw_reset_bits[5] = {
	BP_SRC_SCR_SW_GPU_RST,
	BP_SRC_SCR_SW_VPU_RST,
	BP_SRC_SCR_SW_IPU1_RST,
	BP_SRC_SCR_SW_OPEN_VG_RST,
	BP_SRC_SCR_SW_IPU2_RST
};

static int imx_src_reset_module(struct reset_controller_dev *rcdev,
		unsigned long sw_reset_idx)
{
	unsigned long timeout;
	unsigned long flags;
	int bit;
	u32 val;

	if (sw_reset_idx >= ARRAY_SIZE(sw_reset_bits))
		return -EINVAL;

	bit = 1 << sw_reset_bits[sw_reset_idx];

	spin_lock_irqsave(&scr_lock, flags);
	val = readl_relaxed(src_base + SRC_SCR);
	val |= bit;
	writel_relaxed(val, src_base + SRC_SCR);
	spin_unlock_irqrestore(&scr_lock, flags);

	timeout = jiffies + msecs_to_jiffies(1000);
	while (readl(src_base + SRC_SCR) & bit) {
		if (time_after(jiffies, timeout))
			return -ETIME;
		cpu_relax();
	}

	return 0;
}

static const struct reset_control_ops imx_src_ops = {
	.reset = imx_src_reset_module,
};

static struct reset_controller_dev imx_reset_controller = {
	.ops = &imx_src_ops,
	.nr_resets = ARRAY_SIZE(sw_reset_bits),
};

void imx_enable_cpu(int cpu, bool enable)
{
	u32 mask, val;

	cpu = cpu_logical_map(cpu);
	mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1);
	spin_lock(&scr_lock);
	val = readl_relaxed(src_base + SRC_SCR);
	val = enable ? val | mask : val & ~mask;
	val |= 1 << (BP_SRC_SCR_CORE1_RST + cpu - 1);
	writel_relaxed(val, src_base + SRC_SCR);
	spin_unlock(&scr_lock);
}

void imx_set_cpu_jump(int cpu, void *jump_addr)
{
	cpu = cpu_logical_map(cpu);
	writel_relaxed(__pa_symbol(jump_addr),
		       src_base + SRC_GPR1 + cpu * 8);
}

u32 imx_get_cpu_arg(int cpu)
{
	cpu = cpu_logical_map(cpu);
	return readl_relaxed(src_base + SRC_GPR1 + cpu * 8 + 4);
}

void imx_set_cpu_arg(int cpu, u32 arg)
{
	cpu = cpu_logical_map(cpu);
	writel_relaxed(arg, src_base + SRC_GPR1 + cpu * 8 + 4);
}

void __init imx_src_init(void)
{
	struct device_node *np;
	u32 val;

	np = of_find_compatible_node(NULL, NULL, "fsl,imx51-src");
	if (!np)
		return;
	src_base = of_iomap(np, 0);
	WARN_ON(!src_base);

	imx_reset_controller.of_node = np;
	if (IS_ENABLED(CONFIG_RESET_CONTROLLER))
		reset_controller_register(&imx_reset_controller);

	/*
	 * force warm reset sources to generate cold reset
	 * for a more reliable restart
	 */
	spin_lock(&scr_lock);
	val = readl_relaxed(src_base + SRC_SCR);
	val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE);
	writel_relaxed(val, src_base + SRC_SCR);
	spin_unlock(&scr_lock);
}
Commit	Line	Data
fcaf2036	1	// SPDX-License-Identifier: GPL-2.0-or-later
9fbbe689 SG	2	/*
	3	* Copyright 2011 Freescale Semiconductor, Inc.
	4	* Copyright 2011 Linaro Ltd.
9fbbe689 SG	5	*/
	6
	7	#include <linux/init.h>
	8	#include <linux/io.h>
	9	#include <linux/of.h>
	10	#include <linux/of_address.h>
02985b94	11	#include <linux/reset-controller.h>
eaa142ca	12	#include <linux/smp.h>
eb50439b	13	#include <asm/smp_plat.h>
09898576	14	#include "common.h"
9fbbe689 SG	15
	16	#define SRC_SCR 0x000
	17	#define SRC_GPR1 0x020
0575fb75	18	#define BP_SRC_SCR_WARM_RESET_ENABLE 0
02985b94 PZ	19	#define BP_SRC_SCR_SW_GPU_RST 1
	20	#define BP_SRC_SCR_SW_VPU_RST 2
	21	#define BP_SRC_SCR_SW_IPU1_RST 3
	22	#define BP_SRC_SCR_SW_OPEN_VG_RST 4
	23	#define BP_SRC_SCR_SW_IPU2_RST 12
9fbbe689 SG	24	#define BP_SRC_SCR_CORE1_RST 14
	25	#define BP_SRC_SCR_CORE1_ENABLE 22
	26
	27	static void __iomem *src_base;
02985b94 PZ	28	static DEFINE_SPINLOCK(scr_lock);
	29
	30	static const int sw_reset_bits[5] = {
	31	BP_SRC_SCR_SW_GPU_RST,
	32	BP_SRC_SCR_SW_VPU_RST,
	33	BP_SRC_SCR_SW_IPU1_RST,
	34	BP_SRC_SCR_SW_OPEN_VG_RST,
	35	BP_SRC_SCR_SW_IPU2_RST
	36	};
	37
	38	static int imx_src_reset_module(struct reset_controller_dev *rcdev,
	39	unsigned long sw_reset_idx)
	40	{
	41	unsigned long timeout;
	42	unsigned long flags;
	43	int bit;
	44	u32 val;
	45
02985b94 PZ	46	if (sw_reset_idx >= ARRAY_SIZE(sw_reset_bits))
	47	return -EINVAL;
	48
	49	bit = 1 << sw_reset_bits[sw_reset_idx];
	50
	51	spin_lock_irqsave(&scr_lock, flags);
	52	val = readl_relaxed(src_base + SRC_SCR);
	53	val \|= bit;
	54	writel_relaxed(val, src_base + SRC_SCR);
	55	spin_unlock_irqrestore(&scr_lock, flags);
	56
	57	timeout = jiffies + msecs_to_jiffies(1000);
	58	while (readl(src_base + SRC_SCR) & bit) {
	59	if (time_after(jiffies, timeout))
	60	return -ETIME;
	61	cpu_relax();
	62	}
	63
	64	return 0;
	65	}
	66
d2443b2e	67	static const struct reset_control_ops imx_src_ops = {
02985b94 PZ	68	.reset = imx_src_reset_module,
	69	};
	70
	71	static struct reset_controller_dev imx_reset_controller = {
	72	.ops = &imx_src_ops,
	73	.nr_resets = ARRAY_SIZE(sw_reset_bits),
	74	};
9fbbe689 SG	75
	76	void imx_enable_cpu(int cpu, bool enable)
	77	{
	78	u32 mask, val;
	79
eaa142ca	80	cpu = cpu_logical_map(cpu);
9fbbe689	81	mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1);
02985b94	82	spin_lock(&scr_lock);
9fbbe689 SG	83	val = readl_relaxed(src_base + SRC_SCR);
9fbbe689 SG	84	val = enable ? val \| mask : val & ~mask;
6050d181	85	val \|= 1 << (BP_SRC_SCR_CORE1_RST + cpu - 1);
9fbbe689	86	writel_relaxed(val, src_base + SRC_SCR);
02985b94	87	spin_unlock(&scr_lock);
9fbbe689 SG	88	}
	89
	90	void imx_set_cpu_jump(int cpu, void *jump_addr)
	91	{
eaa142ca	92	cpu = cpu_logical_map(cpu);
64fc2a94	93	writel_relaxed(__pa_symbol(jump_addr),
9fbbe689 SG	94	src_base + SRC_GPR1 + cpu * 8);
	95	}
	96
2f3edfd7 SG	97	u32 imx_get_cpu_arg(int cpu)
	98	{
	99	cpu = cpu_logical_map(cpu);
	100	return readl_relaxed(src_base + SRC_GPR1 + cpu * 8 + 4);
	101	}
	102
	103	void imx_set_cpu_arg(int cpu, u32 arg)
	104	{
	105	cpu = cpu_logical_map(cpu);
	106	writel_relaxed(arg, src_base + SRC_GPR1 + cpu * 8 + 4);
	107	}
	108
9fbbe689 SG	109	void __init imx_src_init(void)
	110	{
	111	struct device_node *np;
0575fb75	112	u32 val;
9fbbe689	113
bd3d924d PZ	114	np = of_find_compatible_node(NULL, NULL, "fsl,imx51-src");
	115	if (!np)
	116	return;
9fbbe689 SG	117	src_base = of_iomap(np, 0);
9fbbe689 SG	118	WARN_ON(!src_base);
0575fb75	119
02985b94	120	imx_reset_controller.of_node = np;
5c5f0421 AB	121	if (IS_ENABLED(CONFIG_RESET_CONTROLLER))
5c5f0421 AB	122	reset_controller_register(&imx_reset_controller);
02985b94	123
0575fb75 SG	124	/*
	125	* force warm reset sources to generate cold reset
	126	* for a more reliable restart
	127	*/
02985b94	128	spin_lock(&scr_lock);
0575fb75 SG	129	val = readl_relaxed(src_base + SRC_SCR);
	130	val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE);
	131	writel_relaxed(val, src_base + SRC_SCR);
02985b94	132	spin_unlock(&scr_lock);
9fbbe689	133	}