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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mach-integrator/core.c | |
3 | * | |
4 | * Copyright (C) 2000-2003 Deep Blue Solutions Ltd | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2, as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | #include <linux/types.h> | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/device.h> | |
14 | #include <linux/spinlock.h> | |
15 | #include <linux/interrupt.h> | |
a03d4d27 | 16 | #include <linux/irq.h> |
1da177e4 | 17 | #include <linux/sched.h> |
20cf33ea | 18 | #include <linux/smp.h> |
fbb18a27 | 19 | #include <linux/termios.h> |
a62c80e5 | 20 | #include <linux/amba/bus.h> |
fbb18a27 | 21 | #include <linux/amba/serial.h> |
fced80c7 | 22 | #include <linux/io.h> |
1da177e4 | 23 | |
d72fbdf0 RK |
24 | #include <asm/clkdev.h> |
25 | #include <mach/clkdev.h> | |
a09e64fb | 26 | #include <mach/hardware.h> |
1da177e4 | 27 | #include <asm/irq.h> |
b720f732 | 28 | #include <asm/hardware/arm_timer.h> |
a09e64fb | 29 | #include <mach/cm.h> |
1da177e4 LT |
30 | #include <asm/system.h> |
31 | #include <asm/leds.h> | |
32 | #include <asm/mach/time.h> | |
33 | ||
34 | #include "common.h" | |
35 | ||
fbb18a27 RK |
36 | static struct amba_pl010_data integrator_uart_data; |
37 | ||
1da177e4 LT |
38 | static struct amba_device rtc_device = { |
39 | .dev = { | |
1d559e29 | 40 | .init_name = "mb:15", |
1da177e4 LT |
41 | }, |
42 | .res = { | |
43 | .start = INTEGRATOR_RTC_BASE, | |
44 | .end = INTEGRATOR_RTC_BASE + SZ_4K - 1, | |
45 | .flags = IORESOURCE_MEM, | |
46 | }, | |
47 | .irq = { IRQ_RTCINT, NO_IRQ }, | |
48 | .periphid = 0x00041030, | |
49 | }; | |
50 | ||
51 | static struct amba_device uart0_device = { | |
52 | .dev = { | |
1d559e29 | 53 | .init_name = "mb:16", |
fbb18a27 | 54 | .platform_data = &integrator_uart_data, |
1da177e4 LT |
55 | }, |
56 | .res = { | |
57 | .start = INTEGRATOR_UART0_BASE, | |
58 | .end = INTEGRATOR_UART0_BASE + SZ_4K - 1, | |
59 | .flags = IORESOURCE_MEM, | |
60 | }, | |
61 | .irq = { IRQ_UARTINT0, NO_IRQ }, | |
62 | .periphid = 0x0041010, | |
63 | }; | |
64 | ||
65 | static struct amba_device uart1_device = { | |
66 | .dev = { | |
1d559e29 | 67 | .init_name = "mb:17", |
fbb18a27 | 68 | .platform_data = &integrator_uart_data, |
1da177e4 LT |
69 | }, |
70 | .res = { | |
71 | .start = INTEGRATOR_UART1_BASE, | |
72 | .end = INTEGRATOR_UART1_BASE + SZ_4K - 1, | |
73 | .flags = IORESOURCE_MEM, | |
74 | }, | |
75 | .irq = { IRQ_UARTINT1, NO_IRQ }, | |
76 | .periphid = 0x0041010, | |
77 | }; | |
78 | ||
79 | static struct amba_device kmi0_device = { | |
80 | .dev = { | |
1d559e29 | 81 | .init_name = "mb:18", |
1da177e4 LT |
82 | }, |
83 | .res = { | |
84 | .start = KMI0_BASE, | |
85 | .end = KMI0_BASE + SZ_4K - 1, | |
86 | .flags = IORESOURCE_MEM, | |
87 | }, | |
88 | .irq = { IRQ_KMIINT0, NO_IRQ }, | |
89 | .periphid = 0x00041050, | |
90 | }; | |
91 | ||
92 | static struct amba_device kmi1_device = { | |
93 | .dev = { | |
1d559e29 | 94 | .init_name = "mb:19", |
1da177e4 LT |
95 | }, |
96 | .res = { | |
97 | .start = KMI1_BASE, | |
98 | .end = KMI1_BASE + SZ_4K - 1, | |
99 | .flags = IORESOURCE_MEM, | |
100 | }, | |
101 | .irq = { IRQ_KMIINT1, NO_IRQ }, | |
102 | .periphid = 0x00041050, | |
103 | }; | |
104 | ||
105 | static struct amba_device *amba_devs[] __initdata = { | |
106 | &rtc_device, | |
107 | &uart0_device, | |
108 | &uart1_device, | |
109 | &kmi0_device, | |
110 | &kmi1_device, | |
111 | }; | |
112 | ||
d72fbdf0 RK |
113 | /* |
114 | * These are fixed clocks. | |
115 | */ | |
116 | static struct clk clk24mhz = { | |
117 | .rate = 24000000, | |
118 | }; | |
119 | ||
120 | static struct clk uartclk = { | |
121 | .rate = 14745600, | |
122 | }; | |
123 | ||
a93ea9b3 | 124 | static struct clk_lookup lookups[] = { |
d72fbdf0 RK |
125 | { /* UART0 */ |
126 | .dev_id = "mb:16", | |
127 | .clk = &uartclk, | |
128 | }, { /* UART1 */ | |
129 | .dev_id = "mb:17", | |
130 | .clk = &uartclk, | |
131 | }, { /* KMI0 */ | |
132 | .dev_id = "mb:18", | |
133 | .clk = &clk24mhz, | |
134 | }, { /* KMI1 */ | |
135 | .dev_id = "mb:19", | |
136 | .clk = &clk24mhz, | |
137 | }, { /* MMCI - IntegratorCP */ | |
138 | .dev_id = "mb:1c", | |
139 | .clk = &uartclk, | |
140 | } | |
141 | }; | |
142 | ||
1da177e4 LT |
143 | static int __init integrator_init(void) |
144 | { | |
145 | int i; | |
146 | ||
0a0300dc | 147 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); |
d72fbdf0 | 148 | |
1da177e4 LT |
149 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { |
150 | struct amba_device *d = amba_devs[i]; | |
151 | amba_device_register(d, &iomem_resource); | |
152 | } | |
153 | ||
154 | return 0; | |
155 | } | |
156 | ||
157 | arch_initcall(integrator_init); | |
158 | ||
fbb18a27 RK |
159 | /* |
160 | * On the Integrator platform, the port RTS and DTR are provided by | |
161 | * bits in the following SC_CTRLS register bits: | |
162 | * RTS DTR | |
163 | * UART0 7 6 | |
164 | * UART1 5 4 | |
165 | */ | |
166 | #define SC_CTRLC (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_CTRLC_OFFSET) | |
167 | #define SC_CTRLS (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_CTRLS_OFFSET) | |
168 | ||
169 | static void integrator_uart_set_mctrl(struct amba_device *dev, void __iomem *base, unsigned int mctrl) | |
170 | { | |
171 | unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask; | |
172 | ||
173 | if (dev == &uart0_device) { | |
174 | rts_mask = 1 << 4; | |
175 | dtr_mask = 1 << 5; | |
176 | } else { | |
177 | rts_mask = 1 << 6; | |
178 | dtr_mask = 1 << 7; | |
179 | } | |
180 | ||
181 | if (mctrl & TIOCM_RTS) | |
182 | ctrlc |= rts_mask; | |
183 | else | |
184 | ctrls |= rts_mask; | |
185 | ||
186 | if (mctrl & TIOCM_DTR) | |
187 | ctrlc |= dtr_mask; | |
188 | else | |
189 | ctrls |= dtr_mask; | |
190 | ||
191 | __raw_writel(ctrls, SC_CTRLS); | |
192 | __raw_writel(ctrlc, SC_CTRLC); | |
193 | } | |
194 | ||
195 | static struct amba_pl010_data integrator_uart_data = { | |
196 | .set_mctrl = integrator_uart_set_mctrl, | |
197 | }; | |
198 | ||
1da177e4 LT |
199 | #define CM_CTRL IO_ADDRESS(INTEGRATOR_HDR_BASE) + INTEGRATOR_HDR_CTRL_OFFSET |
200 | ||
201 | static DEFINE_SPINLOCK(cm_lock); | |
202 | ||
203 | /** | |
204 | * cm_control - update the CM_CTRL register. | |
205 | * @mask: bits to change | |
206 | * @set: bits to set | |
207 | */ | |
208 | void cm_control(u32 mask, u32 set) | |
209 | { | |
210 | unsigned long flags; | |
211 | u32 val; | |
212 | ||
213 | spin_lock_irqsave(&cm_lock, flags); | |
214 | val = readl(CM_CTRL) & ~mask; | |
215 | writel(val | set, CM_CTRL); | |
216 | spin_unlock_irqrestore(&cm_lock, flags); | |
217 | } | |
218 | ||
219 | EXPORT_SYMBOL(cm_control); | |
220 | ||
221 | /* | |
222 | * Where is the timer (VA)? | |
223 | */ | |
224 | #define TIMER0_VA_BASE (IO_ADDRESS(INTEGRATOR_CT_BASE)+0x00000000) | |
225 | #define TIMER1_VA_BASE (IO_ADDRESS(INTEGRATOR_CT_BASE)+0x00000100) | |
226 | #define TIMER2_VA_BASE (IO_ADDRESS(INTEGRATOR_CT_BASE)+0x00000200) | |
227 | #define VA_IC_BASE IO_ADDRESS(INTEGRATOR_IC_BASE) | |
228 | ||
229 | /* | |
230 | * How long is the timer interval? | |
231 | */ | |
232 | #define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10) | |
233 | #if TIMER_INTERVAL >= 0x100000 | |
234 | #define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC) | |
235 | #elif TIMER_INTERVAL >= 0x10000 | |
236 | #define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC) | |
237 | #else | |
238 | #define TICKS2USECS(x) ((x) / TICKS_PER_uSEC) | |
239 | #endif | |
240 | ||
1da177e4 LT |
241 | static unsigned long timer_reload; |
242 | ||
243 | /* | |
244 | * Returns number of ms since last clock interrupt. Note that interrupts | |
245 | * will have been disabled by do_gettimeoffset() | |
246 | */ | |
247 | unsigned long integrator_gettimeoffset(void) | |
248 | { | |
1da177e4 LT |
249 | unsigned long ticks1, ticks2, status; |
250 | ||
251 | /* | |
252 | * Get the current number of ticks. Note that there is a race | |
253 | * condition between us reading the timer and checking for | |
254 | * an interrupt. We get around this by ensuring that the | |
255 | * counter has not reloaded between our two reads. | |
256 | */ | |
b720f732 | 257 | ticks2 = readl(TIMER1_VA_BASE + TIMER_VALUE) & 0xffff; |
1da177e4 LT |
258 | do { |
259 | ticks1 = ticks2; | |
260 | status = __raw_readl(VA_IC_BASE + IRQ_RAW_STATUS); | |
b720f732 | 261 | ticks2 = readl(TIMER1_VA_BASE + TIMER_VALUE) & 0xffff; |
1da177e4 LT |
262 | } while (ticks2 > ticks1); |
263 | ||
264 | /* | |
265 | * Number of ticks since last interrupt. | |
266 | */ | |
267 | ticks1 = timer_reload - ticks2; | |
268 | ||
269 | /* | |
270 | * Interrupt pending? If so, we've reloaded once already. | |
271 | */ | |
272 | if (status & (1 << IRQ_TIMERINT1)) | |
273 | ticks1 += timer_reload; | |
274 | ||
275 | /* | |
276 | * Convert the ticks to usecs | |
277 | */ | |
278 | return TICKS2USECS(ticks1); | |
279 | } | |
280 | ||
281 | /* | |
282 | * IRQ handler for the timer | |
283 | */ | |
284 | static irqreturn_t | |
0cd61b68 | 285 | integrator_timer_interrupt(int irq, void *dev_id) |
1da177e4 | 286 | { |
1f9c381f RK |
287 | /* |
288 | * clear the interrupt | |
289 | */ | |
b720f732 | 290 | writel(1, TIMER1_VA_BASE + TIMER_INTCLR); |
1da177e4 | 291 | |
06ba2555 | 292 | timer_tick(); |
1da177e4 | 293 | |
1da177e4 LT |
294 | return IRQ_HANDLED; |
295 | } | |
296 | ||
297 | static struct irqaction integrator_timer_irq = { | |
298 | .name = "Integrator Timer Tick", | |
b30fabad | 299 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, |
09b8b5f8 | 300 | .handler = integrator_timer_interrupt, |
1da177e4 LT |
301 | }; |
302 | ||
303 | /* | |
304 | * Set up timer interrupt, and return the current time in seconds. | |
305 | */ | |
306 | void __init integrator_time_init(unsigned long reload, unsigned int ctrl) | |
307 | { | |
b720f732 | 308 | unsigned int timer_ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC; |
1da177e4 LT |
309 | |
310 | timer_reload = reload; | |
311 | timer_ctrl |= ctrl; | |
312 | ||
313 | if (timer_reload > 0x100000) { | |
314 | timer_reload >>= 8; | |
b720f732 | 315 | timer_ctrl |= TIMER_CTRL_DIV256; |
1da177e4 LT |
316 | } else if (timer_reload > 0x010000) { |
317 | timer_reload >>= 4; | |
b720f732 | 318 | timer_ctrl |= TIMER_CTRL_DIV16; |
1da177e4 LT |
319 | } |
320 | ||
321 | /* | |
322 | * Initialise to a known state (all timers off) | |
323 | */ | |
b720f732 RK |
324 | writel(0, TIMER0_VA_BASE + TIMER_CTRL); |
325 | writel(0, TIMER1_VA_BASE + TIMER_CTRL); | |
326 | writel(0, TIMER2_VA_BASE + TIMER_CTRL); | |
1da177e4 | 327 | |
b720f732 RK |
328 | writel(timer_reload, TIMER1_VA_BASE + TIMER_LOAD); |
329 | writel(timer_reload, TIMER1_VA_BASE + TIMER_VALUE); | |
330 | writel(timer_ctrl, TIMER1_VA_BASE + TIMER_CTRL); | |
1da177e4 | 331 | |
1f9c381f | 332 | /* |
1da177e4 LT |
333 | * Make irqs happen for the system timer |
334 | */ | |
335 | setup_irq(IRQ_TIMERINT1, &integrator_timer_irq); | |
336 | } |