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Commit | Line | Data |
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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
1da177e4 LT |
2 | /* |
3 | * linux/arch/arm/mach-integrator/core.c | |
4 | * | |
5 | * Copyright (C) 2000-2003 Deep Blue Solutions Ltd | |
1da177e4 LT |
6 | */ |
7 | #include <linux/types.h> | |
8 | #include <linux/kernel.h> | |
9 | #include <linux/init.h> | |
10 | #include <linux/device.h> | |
b434f5c9 | 11 | #include <linux/export.h> |
1da177e4 LT |
12 | #include <linux/spinlock.h> |
13 | #include <linux/interrupt.h> | |
a03d4d27 | 14 | #include <linux/irq.h> |
8d717a52 | 15 | #include <linux/memblock.h> |
1da177e4 | 16 | #include <linux/sched.h> |
20cf33ea | 17 | #include <linux/smp.h> |
a62c80e5 | 18 | #include <linux/amba/bus.h> |
fbb18a27 | 19 | #include <linux/amba/serial.h> |
fced80c7 | 20 | #include <linux/io.h> |
e67ae6be | 21 | #include <linux/stat.h> |
bb4dbefe LW |
22 | #include <linux/of.h> |
23 | #include <linux/of_address.h> | |
1da177e4 | 24 | |
ee35887e | 25 | #include <asm/mach-types.h> |
1da177e4 | 26 | #include <asm/mach/time.h> |
98c672cf | 27 | #include <asm/pgtable.h> |
1da177e4 | 28 | |
1b1ef755 | 29 | #include "hardware.h" |
bb4dbefe | 30 | #include "cm.h" |
4672cddf LW |
31 | #include "common.h" |
32 | ||
bd31b859 | 33 | static DEFINE_RAW_SPINLOCK(cm_lock); |
bb4dbefe | 34 | static void __iomem *cm_base; |
1da177e4 | 35 | |
fb61f862 LW |
36 | /** |
37 | * cm_get - get the value from the CM_CTRL register | |
38 | */ | |
39 | u32 cm_get(void) | |
40 | { | |
41 | return readl(cm_base + INTEGRATOR_HDR_CTRL_OFFSET); | |
42 | } | |
43 | ||
1da177e4 LT |
44 | /** |
45 | * cm_control - update the CM_CTRL register. | |
46 | * @mask: bits to change | |
47 | * @set: bits to set | |
48 | */ | |
49 | void cm_control(u32 mask, u32 set) | |
50 | { | |
51 | unsigned long flags; | |
52 | u32 val; | |
53 | ||
bd31b859 | 54 | raw_spin_lock_irqsave(&cm_lock, flags); |
bb4dbefe LW |
55 | val = readl(cm_base + INTEGRATOR_HDR_CTRL_OFFSET) & ~mask; |
56 | writel(val | set, cm_base + INTEGRATOR_HDR_CTRL_OFFSET); | |
bd31b859 | 57 | raw_spin_unlock_irqrestore(&cm_lock, flags); |
1da177e4 LT |
58 | } |
59 | ||
bb4dbefe LW |
60 | void cm_clear_irqs(void) |
61 | { | |
62 | /* disable core module IRQs */ | |
63 | writel(0xffffffffU, cm_base + INTEGRATOR_HDR_IC_OFFSET + | |
64 | IRQ_ENABLE_CLEAR); | |
65 | } | |
66 | ||
67 | static const struct of_device_id cm_match[] = { | |
68 | { .compatible = "arm,core-module-integrator"}, | |
69 | { }, | |
70 | }; | |
71 | ||
72 | void cm_init(void) | |
73 | { | |
74 | struct device_node *cm = of_find_matching_node(NULL, cm_match); | |
bb4dbefe LW |
75 | |
76 | if (!cm) { | |
77 | pr_crit("no core module node found in device tree\n"); | |
78 | return; | |
79 | } | |
80 | cm_base = of_iomap(cm, 0); | |
81 | if (!cm_base) { | |
82 | pr_crit("could not remap core module\n"); | |
83 | return; | |
84 | } | |
85 | cm_clear_irqs(); | |
bb4dbefe | 86 | } |
98c672cf RK |
87 | |
88 | /* | |
89 | * We need to stop things allocating the low memory; ideally we need a | |
90 | * better implementation of GFP_DMA which does not assume that DMA-able | |
91 | * memory starts at zero. | |
92 | */ | |
93 | void __init integrator_reserve(void) | |
94 | { | |
8d717a52 | 95 | memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET); |
98c672cf | 96 | } |