[mirror_ubuntu-zesty-kernel.git] / arch / arm / mach-integrator / integrator_ap.c

/*
 *  linux/arch/arm/mach-integrator/integrator_ap.c
 *
 *  Copyright (C) 2000-2003 Deep Blue Solutions Ltd
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/syscore_ops.h>
#include <linux/amba/bus.h>
#include <linux/amba/kmi.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irqchip/versatile-fpga.h>
#include <linux/mtd/physmap.h>
#include <linux/clk.h>
#include <linux/platform_data/clk-integrator.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/stat.h>
#include <linux/sys_soc.h>
#include <linux/termios.h>
#include <linux/sched_clock.h>
#include <linux/clk-provider.h>

#include <asm/hardware/arm_timer.h>
#include <asm/setup.h>
#include <asm/param.h>		/* HZ */
#include <asm/mach-types.h>

#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>

#include "hardware.h"
#include "cm.h"
#include "common.h"
#include "pci_v3.h"
#include "lm.h"

/* Base address to the AP system controller */
void __iomem *ap_syscon_base;
/* Base address to the external bus interface */
static void __iomem *ebi_base;


/*
 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
 * is the (PA >> 12).
 *
 * Setup a VA for the Integrator interrupt controller (for header #0,
 * just for now).
 */
#define VA_IC_BASE	__io_address(INTEGRATOR_IC_BASE)

/*
 * Logical      Physical
 * ef000000			Cache flush
 * f1100000	11000000	System controller registers
 * f1300000	13000000	Counter/Timer
 * f1400000	14000000	Interrupt controller
 * f1600000	16000000	UART 0
 * f1700000	17000000	UART 1
 * f1a00000	1a000000	Debug LEDs
 * f1b00000	1b000000	GPIO
 */

static struct map_desc ap_io_desc[] __initdata __maybe_unused = {
	{
		.virtual	= IO_ADDRESS(INTEGRATOR_CT_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_CT_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_IC_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_IC_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_UART0_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_UART0_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_DBG_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_DBG_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}
};

static void __init ap_map_io(void)
{
	iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
	pci_v3_early_init();
}

#ifdef CONFIG_PM
static unsigned long ic_irq_enable;

static int irq_suspend(void)
{
	ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
	return 0;
}

static void irq_resume(void)
{
	/* disable all irq sources */
	cm_clear_irqs();
	writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
	writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);

	writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
}
#else
#define irq_suspend NULL
#define irq_resume NULL
#endif

static struct syscore_ops irq_syscore_ops = {
	.suspend	= irq_suspend,
	.resume		= irq_resume,
};

static int __init irq_syscore_init(void)
{
	register_syscore_ops(&irq_syscore_ops);

	return 0;
}

device_initcall(irq_syscore_init);

/*
 * Flash handling.
 */
static int ap_flash_init(struct platform_device *dev)
{
	u32 tmp;

	writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
	       ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);

	tmp = readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) |
		INTEGRATOR_EBI_WRITE_ENABLE;
	writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);

	if (!(readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET)
	      & INTEGRATOR_EBI_WRITE_ENABLE)) {
		writel(0xa05f, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
		writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
		writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
	}
	return 0;
}

static void ap_flash_exit(struct platform_device *dev)
{
	u32 tmp;

	writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
	       ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);

	tmp = readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) &
		~INTEGRATOR_EBI_WRITE_ENABLE;
	writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);

	if (readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) &
	    INTEGRATOR_EBI_WRITE_ENABLE) {
		writel(0xa05f, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
		writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
		writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
	}
}

static void ap_flash_set_vpp(struct platform_device *pdev, int on)
{
	if (on)
		writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
		       ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET);
	else
		writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
		       ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
}

static struct physmap_flash_data ap_flash_data = {
	.width		= 4,
	.init		= ap_flash_init,
	.exit		= ap_flash_exit,
	.set_vpp	= ap_flash_set_vpp,
};

/*
 * For the PL010 found in the Integrator/AP some of the UART control is
 * implemented in the system controller and accessed using a callback
 * from the driver.
 */
static void integrator_uart_set_mctrl(struct amba_device *dev,
				void __iomem *base, unsigned int mctrl)
{
	unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
	u32 phybase = dev->res.start;

	if (phybase == INTEGRATOR_UART0_BASE) {
		/* UART0 */
		rts_mask = 1 << 4;
		dtr_mask = 1 << 5;
	} else {
		/* UART1 */
		rts_mask = 1 << 6;
		dtr_mask = 1 << 7;
	}

	if (mctrl & TIOCM_RTS)
		ctrlc |= rts_mask;
	else
		ctrls |= rts_mask;

	if (mctrl & TIOCM_DTR)
		ctrlc |= dtr_mask;
	else
		ctrls |= dtr_mask;

	__raw_writel(ctrls, ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET);
	__raw_writel(ctrlc, ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
}

struct amba_pl010_data ap_uart_data = {
	.set_mctrl = integrator_uart_set_mctrl,
};

/*
 * Where is the timer (VA)?
 */
#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
#define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
#define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)

static unsigned long timer_reload;

static u64 notrace integrator_read_sched_clock(void)
{
	return -readl((void __iomem *) TIMER2_VA_BASE + TIMER_VALUE);
}

static void integrator_clocksource_init(unsigned long inrate,
					void __iomem *base)
{
	u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
	unsigned long rate = inrate;

	if (rate >= 1500000) {
		rate /= 16;
		ctrl |= TIMER_CTRL_DIV16;
	}

	writel(0xffff, base + TIMER_LOAD);
	writel(ctrl, base + TIMER_CTRL);

	clocksource_mmio_init(base + TIMER_VALUE, "timer2",
			rate, 200, 16, clocksource_mmio_readl_down);
	sched_clock_register(integrator_read_sched_clock, 16, rate);
}

static void __iomem * clkevt_base;

/*
 * IRQ handler for the timer
 */
static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	/* clear the interrupt */
	writel(1, clkevt_base + TIMER_INTCLR);

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
{
	u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;

	/* Disable timer */
	writel(ctrl, clkevt_base + TIMER_CTRL);

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		/* Enable the timer and start the periodic tick */
		writel(timer_reload, clkevt_base + TIMER_LOAD);
		ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
		writel(ctrl, clkevt_base + TIMER_CTRL);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		/* Leave the timer disabled, .set_next_event will enable it */
		ctrl &= ~TIMER_CTRL_PERIODIC;
		writel(ctrl, clkevt_base + TIMER_CTRL);
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_RESUME:
	default:
		/* Just leave in disabled state */
		break;
	}

}

static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
{
	unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);

	writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
	writel(next, clkevt_base + TIMER_LOAD);
	writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);

	return 0;
}

static struct clock_event_device integrator_clockevent = {
	.name		= "timer1",
	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.set_mode	= clkevt_set_mode,
	.set_next_event	= clkevt_set_next_event,
	.rating		= 300,
};

static struct irqaction integrator_timer_irq = {
	.name		= "timer",
	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= integrator_timer_interrupt,
	.dev_id		= &integrator_clockevent,
};

static void integrator_clockevent_init(unsigned long inrate,
				void __iomem *base, int irq)
{
	unsigned long rate = inrate;
	unsigned int ctrl = 0;

	clkevt_base = base;
	/* Calculate and program a divisor */
	if (rate > 0x100000 * HZ) {
		rate /= 256;
		ctrl |= TIMER_CTRL_DIV256;
	} else if (rate > 0x10000 * HZ) {
		rate /= 16;
		ctrl |= TIMER_CTRL_DIV16;
	}
	timer_reload = rate / HZ;
	writel(ctrl, clkevt_base + TIMER_CTRL);

	setup_irq(irq, &integrator_timer_irq);
	clockevents_config_and_register(&integrator_clockevent,
					rate,
					1,
					0xffffU);
}

void __init ap_init_early(void)
{
}

static void __init ap_of_timer_init(void)
{
	struct device_node *node;
	const char *path;
	void __iomem *base;
	int err;
	int irq;
	struct clk *clk;
	unsigned long rate;

	of_clk_init(NULL);

	err = of_property_read_string(of_aliases,
				"arm,timer-primary", &path);
	if (WARN_ON(err))
		return;
	node = of_find_node_by_path(path);
	base = of_iomap(node, 0);
	if (WARN_ON(!base))
		return;

	clk = of_clk_get(node, 0);
	BUG_ON(IS_ERR(clk));
	clk_prepare_enable(clk);
	rate = clk_get_rate(clk);

	writel(0, base + TIMER_CTRL);
	integrator_clocksource_init(rate, base);

	err = of_property_read_string(of_aliases,
				"arm,timer-secondary", &path);
	if (WARN_ON(err))
		return;
	node = of_find_node_by_path(path);
	base = of_iomap(node, 0);
	if (WARN_ON(!base))
		return;
	irq = irq_of_parse_and_map(node, 0);

	clk = of_clk_get(node, 0);
	BUG_ON(IS_ERR(clk));
	clk_prepare_enable(clk);
	rate = clk_get_rate(clk);

	writel(0, base + TIMER_CTRL);
	integrator_clockevent_init(rate, base, irq);
}

static const struct of_device_id fpga_irq_of_match[] __initconst = {
	{ .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
	{ /* Sentinel */ }
};

static void __init ap_init_irq_of(void)
{
	cm_init();
	of_irq_init(fpga_irq_of_match);
}

/* For the Device Tree, add in the UART callbacks as AUXDATA */
static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
		"rtc", NULL),
	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
		"uart0", &ap_uart_data),
	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
		"uart1", &ap_uart_data),
	OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
		"kmi0", NULL),
	OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
		"kmi1", NULL),
	OF_DEV_AUXDATA("cfi-flash", INTEGRATOR_FLASH_BASE,
		"physmap-flash", &ap_flash_data),
	{ /* sentinel */ },
};

static const struct of_device_id ap_syscon_match[] = {
	{ .compatible = "arm,integrator-ap-syscon"},
	{ },
};

static const struct of_device_id ebi_match[] = {
	{ .compatible = "arm,external-bus-interface"},
	{ },
};

static void __init ap_init_of(void)
{
	unsigned long sc_dec;
	struct device_node *syscon;
	struct device_node *ebi;
	struct device *parent;
	struct soc_device *soc_dev;
	struct soc_device_attribute *soc_dev_attr;
	u32 ap_sc_id;
	int i;

	syscon = of_find_matching_node(NULL, ap_syscon_match);
	if (!syscon)
		return;
	ebi = of_find_matching_node(NULL, ebi_match);
	if (!ebi)
		return;

	ap_syscon_base = of_iomap(syscon, 0);
	if (!ap_syscon_base)
		return;
	ebi_base = of_iomap(ebi, 0);
	if (!ebi_base)
		return;

	of_platform_populate(NULL, of_default_bus_match_table,
			ap_auxdata_lookup, NULL);

	ap_sc_id = readl(ap_syscon_base);

	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
	if (!soc_dev_attr)
		return;

	soc_dev_attr->soc_id = "XVC";
	soc_dev_attr->machine = "Integrator/AP";
	soc_dev_attr->family = "Integrator";
	soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
					   'A' + (ap_sc_id & 0x0f));

	soc_dev = soc_device_register(soc_dev_attr);
	if (IS_ERR(soc_dev)) {
		kfree(soc_dev_attr->revision);
		kfree(soc_dev_attr);
		return;
	}

	parent = soc_device_to_device(soc_dev);
	integrator_init_sysfs(parent, ap_sc_id);

	sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET);
	for (i = 0; i < 4; i++) {
		struct lm_device *lmdev;

		if ((sc_dec & (16 << i)) == 0)
			continue;

		lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
		if (!lmdev)
			continue;

		lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
		lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
		lmdev->resource.flags = IORESOURCE_MEM;
		lmdev->irq = irq_of_parse_and_map(syscon, i);
		lmdev->id = i;

		lm_device_register(lmdev);
	}
}

static const char * ap_dt_board_compat[] = {
	"arm,integrator-ap",
	NULL,
};

DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
	.reserve	= integrator_reserve,
	.map_io		= ap_map_io,
	.init_early	= ap_init_early,
	.init_irq	= ap_init_irq_of,
	.handle_irq	= fpga_handle_irq,
	.init_time	= ap_of_timer_init,
	.init_machine	= ap_init_of,
	.restart	= integrator_restart,
	.dt_compat      = ap_dt_board_compat,
MACHINE_END
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-integrator/integrator_ap.c
	3	*
	4	* Copyright (C) 2000-2003 Deep Blue Solutions Ltd
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20	#include <linux/types.h>
	21	#include <linux/kernel.h>
	22	#include <linux/init.h>
	23	#include <linux/list.h>
d052d1be	24	#include <linux/platform_device.h>
1da177e4 LT	25	#include <linux/slab.h>
1da177e4 LT	26	#include <linux/string.h>
b7808056	27	#include <linux/syscore_ops.h>
a62c80e5 RK	28	#include <linux/amba/bus.h>
a62c80e5 RK	29	#include <linux/amba/kmi.h>
6be4826e RK	30	#include <linux/clocksource.h>
	31	#include <linux/clockchips.h>
	32	#include <linux/interrupt.h>
fced80c7	33	#include <linux/io.h>
2389d501	34	#include <linux/irqchip/versatile-fpga.h>
f07e762e	35	#include <linux/mtd/physmap.h>
bb76079a	36	#include <linux/clk.h>
a613163d	37	#include <linux/platform_data/clk-integrator.h>
4980f9bc LW	38	#include <linux/of_irq.h>
4980f9bc LW	39	#include <linux/of_address.h>
4672cddf	40	#include <linux/of_platform.h>
e67ae6be LW	41	#include <linux/stat.h>
e67ae6be LW	42	#include <linux/sys_soc.h>
379df279	43	#include <linux/termios.h>
38ff87f7	44	#include <linux/sched_clock.h>
09c978bc	45	#include <linux/clk-provider.h>
1da177e4	46
6be4826e	47	#include <asm/hardware/arm_timer.h>
1da177e4	48	#include <asm/setup.h>
4e57b681	49	#include <asm/param.h> /* HZ */
1da177e4	50	#include <asm/mach-types.h>
1da177e4	51
1da177e4	52	#include <asm/mach/arch.h>
1da177e4 LT	53	#include <asm/mach/irq.h>
	54	#include <asm/mach/map.h>
	55	#include <asm/mach/time.h>
	56
1b1ef755	57	#include "hardware.h"
bb4dbefe	58	#include "cm.h"
98c672cf	59	#include "common.h"
ae9daf2d	60	#include "pci_v3.h"
c36928ad	61	#include "lm.h"
98c672cf	62
83feba51	63	/* Base address to the AP system controller */
379df279	64	void __iomem *ap_syscon_base;
307b9667 LW	65	/* Base address to the external bus interface */
307b9667 LW	66	static void __iomem *ebi_base;
83feba51	67
83feba51 LW	68
83feba51 LW	69	/*
1da177e4 LT	70	* All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
	71	* is the (PA >> 12).
	72	*
	73	* Setup a VA for the Integrator interrupt controller (for header #0,
	74	* just for now).
	75	*/
c41b16f8	76	#define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE)
1da177e4 LT	77
	78	/*
	79	* Logical Physical
1da177e4	80	* ef000000 Cache flush
1da177e4	81	* f1100000 11000000 System controller registers
1da177e4 LT	82	* f1300000 13000000 Counter/Timer
	83	* f1400000 14000000 Interrupt controller
	84	* f1600000 16000000 UART 0
	85	* f1700000 17000000 UART 1
	86	* f1a00000 1a000000 Debug LEDs
	87	* f1b00000 1b000000 GPIO
	88	*/
	89
060fd1be	90	static struct map_desc ap_io_desc[] __initdata __maybe_unused = {
c8d27298	91	{
c8d27298 DS	92	.virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
	93	.pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
	94	.length = SZ_4K,
	95	.type = MT_DEVICE
	96	}, {
	97	.virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
	98	.pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
	99	.length = SZ_4K,
	100	.type = MT_DEVICE
	101	}, {
	102	.virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
	103	.pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
	104	.length = SZ_4K,
	105	.type = MT_DEVICE
c8d27298 DS	106	}, {
	107	.virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
	108	.pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
	109	.length = SZ_4K,
	110	.type = MT_DEVICE
	111	}, {
da7ba956 RK	112	.virtual = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
da7ba956 RK	113	.pfn = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
c8d27298 DS	114	.length = SZ_4K,
c8d27298 DS	115	.type = MT_DEVICE
c8d27298	116	}
1da177e4 LT	117	};
	118
	119	static void __init ap_map_io(void)
	120	{
	121	iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
ae9daf2d	122	pci_v3_early_init();
1da177e4 LT	123	}
1da177e4 LT	124
1da177e4 LT	125	#ifdef CONFIG_PM
	126	static unsigned long ic_irq_enable;
	127
b7808056	128	static int irq_suspend(void)
1da177e4 LT	129	{
	130	ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
	131	return 0;
	132	}
	133
b7808056	134	static void irq_resume(void)
1da177e4 LT	135	{
1da177e4 LT	136	/* disable all irq sources */
bb4dbefe	137	cm_clear_irqs();
1da177e4 LT	138	writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
	139	writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
	140
	141	writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
1da177e4 LT	142	}
	143	#else
	144	#define irq_suspend NULL
	145	#define irq_resume NULL
	146	#endif
	147
b7808056	148	static struct syscore_ops irq_syscore_ops = {
1da177e4 LT	149	.suspend = irq_suspend,
	150	.resume = irq_resume,
	151	};
	152
b7808056	153	static int __init irq_syscore_init(void)
1da177e4	154	{
b7808056 RW	155	register_syscore_ops(&irq_syscore_ops);
	156
	157	return 0;
1da177e4 LT	158	}
1da177e4 LT	159
b7808056	160	device_initcall(irq_syscore_init);
1da177e4 LT	161
	162	/*
	163	* Flash handling.
	164	*/
f07e762e	165	static int ap_flash_init(struct platform_device *dev)
1da177e4 LT	166	{
	167	u32 tmp;
	168
83feba51 LW	169	writel(INTEGRATOR_SC_CTRL_nFLVPPEN \| INTEGRATOR_SC_CTRL_nFLWP,
83feba51 LW	170	ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
1da177e4	171
307b9667 LW	172	tmp = readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) \|
	173	INTEGRATOR_EBI_WRITE_ENABLE;
	174	writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
1da177e4	175
307b9667 LW	176	if (!(readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET)
	177	& INTEGRATOR_EBI_WRITE_ENABLE)) {
	178	writel(0xa05f, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
	179	writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
	180	writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
1da177e4 LT	181	}
	182	return 0;
	183	}
	184
f07e762e	185	static void ap_flash_exit(struct platform_device *dev)
1da177e4 LT	186	{
	187	u32 tmp;
	188
83feba51 LW	189	writel(INTEGRATOR_SC_CTRL_nFLVPPEN \| INTEGRATOR_SC_CTRL_nFLWP,
83feba51 LW	190	ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
1da177e4	191
307b9667 LW	192	tmp = readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) &
	193	~INTEGRATOR_EBI_WRITE_ENABLE;
	194	writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
1da177e4	195
307b9667 LW	196	if (readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) &
	197	INTEGRATOR_EBI_WRITE_ENABLE) {
	198	writel(0xa05f, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
	199	writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
	200	writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
1da177e4 LT	201	}
	202	}
	203
667f390b	204	static void ap_flash_set_vpp(struct platform_device *pdev, int on)
1da177e4	205	{
83feba51 LW	206	if (on)
	207	writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
	208	ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET);
	209	else
	210	writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
	211	ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
1da177e4 LT	212	}
1da177e4 LT	213
f07e762e	214	static struct physmap_flash_data ap_flash_data = {
1da177e4 LT	215	.width = 4,
	216	.init = ap_flash_init,
	217	.exit = ap_flash_exit,
	218	.set_vpp = ap_flash_set_vpp,
	219	};
	220
379df279 LW	221	/*
	222	* For the PL010 found in the Integrator/AP some of the UART control is
	223	* implemented in the system controller and accessed using a callback
	224	* from the driver.
	225	*/
	226	static void integrator_uart_set_mctrl(struct amba_device *dev,
	227	void __iomem *base, unsigned int mctrl)
	228	{
	229	unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
	230	u32 phybase = dev->res.start;
	231
	232	if (phybase == INTEGRATOR_UART0_BASE) {
	233	/* UART0 */
	234	rts_mask = 1 << 4;
	235	dtr_mask = 1 << 5;
	236	} else {
	237	/* UART1 */
	238	rts_mask = 1 << 6;
	239	dtr_mask = 1 << 7;
	240	}
	241
	242	if (mctrl & TIOCM_RTS)
	243	ctrlc \|= rts_mask;
	244	else
	245	ctrls \|= rts_mask;
	246
	247	if (mctrl & TIOCM_DTR)
	248	ctrlc \|= dtr_mask;
	249	else
	250	ctrls \|= dtr_mask;
	251
	252	__raw_writel(ctrls, ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET);
	253	__raw_writel(ctrlc, ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
	254	}
	255
	256	struct amba_pl010_data ap_uart_data = {
	257	.set_mctrl = integrator_uart_set_mctrl,
	258	};
	259
6be4826e RK	260	/*
	261	* Where is the timer (VA)?
	262	*/
b7a3f8db AB	263	#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
	264	#define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
	265	#define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
6be4826e	266
6be4826e RK	267	static unsigned long timer_reload;
6be4826e RK	268
7a4143fa	269	static u64 notrace integrator_read_sched_clock(void)
a9d6d151 LW	270	{
	271	return -readl((void __iomem *) TIMER2_VA_BASE + TIMER_VALUE);
	272	}
	273
4980f9bc LW	274	static void integrator_clocksource_init(unsigned long inrate,
4980f9bc LW	275	void __iomem *base)
6be4826e	276	{
bb9ea778	277	u32 ctrl = TIMER_CTRL_ENABLE \| TIMER_CTRL_PERIODIC;
bb76079a	278	unsigned long rate = inrate;
6be4826e	279
bb76079a LW	280	if (rate >= 1500000) {
bb76079a LW	281	rate /= 16;
bb9ea778	282	ctrl \|= TIMER_CTRL_DIV16;
6be4826e RK	283	}
6be4826e RK	284
6be4826e	285	writel(0xffff, base + TIMER_LOAD);
bb9ea778	286	writel(ctrl, base + TIMER_CTRL);
6be4826e	287
c5039f52	288	clocksource_mmio_init(base + TIMER_VALUE, "timer2",
bb76079a	289	rate, 200, 16, clocksource_mmio_readl_down);
7a4143fa	290	sched_clock_register(integrator_read_sched_clock, 16, rate);
6be4826e RK	291	}
6be4826e RK	292
4980f9bc	293	static void __iomem * clkevt_base;
6be4826e RK	294
	295	/*
	296	* IRQ handler for the timer
	297	*/
	298	static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
	299	{
	300	struct clock_event_device *evt = dev_id;
	301
	302	/* clear the interrupt */
	303	writel(1, clkevt_base + TIMER_INTCLR);
	304
	305	evt->event_handler(evt);
	306
	307	return IRQ_HANDLED;
	308	}
	309
	310	static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
	311	{
	312	u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
	313
02f56321 LW	314	/* Disable timer */
02f56321 LW	315	writel(ctrl, clkevt_base + TIMER_CTRL);
6be4826e	316
02f56321 LW	317	switch (mode) {
	318	case CLOCK_EVT_MODE_PERIODIC:
	319	/* Enable the timer and start the periodic tick */
6be4826e RK	320	writel(timer_reload, clkevt_base + TIMER_LOAD);
6be4826e RK	321	ctrl \|= TIMER_CTRL_PERIODIC \| TIMER_CTRL_ENABLE;
02f56321 LW	322	writel(ctrl, clkevt_base + TIMER_CTRL);
	323	break;
	324	case CLOCK_EVT_MODE_ONESHOT:
	325	/* Leave the timer disabled, .set_next_event will enable it */
	326	ctrl &= ~TIMER_CTRL_PERIODIC;
	327	writel(ctrl, clkevt_base + TIMER_CTRL);
	328	break;
	329	case CLOCK_EVT_MODE_UNUSED:
	330	case CLOCK_EVT_MODE_SHUTDOWN:
	331	case CLOCK_EVT_MODE_RESUME:
	332	default:
	333	/* Just leave in disabled state */
	334	break;
6be4826e RK	335	}
6be4826e RK	336
6be4826e RK	337	}
	338
	339	static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
	340	{
	341	unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
	342
	343	writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
	344	writel(next, clkevt_base + TIMER_LOAD);
	345	writel(ctrl \| TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
	346
	347	return 0;
	348	}
	349
	350	static struct clock_event_device integrator_clockevent = {
	351	.name = "timer1",
02f56321	352	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
6be4826e RK	353	.set_mode = clkevt_set_mode,
	354	.set_next_event = clkevt_set_next_event,
	355	.rating = 300,
6be4826e RK	356	};
	357
	358	static struct irqaction integrator_timer_irq = {
	359	.name = "timer",
78f6db99	360	.flags = IRQF_TIMER \| IRQF_IRQPOLL,
6be4826e RK	361	.handler = integrator_timer_interrupt,
	362	.dev_id = &integrator_clockevent,
	363	};
	364
4980f9bc LW	365	static void integrator_clockevent_init(unsigned long inrate,
4980f9bc LW	366	void __iomem *base, int irq)
6be4826e	367	{
bb76079a	368	unsigned long rate = inrate;
6be4826e RK	369	unsigned int ctrl = 0;
6be4826e RK	370
4980f9bc	371	clkevt_base = base;
6d8ce712	372	/* Calculate and program a divisor */
bb76079a LW	373	if (rate > 0x100000 * HZ) {
bb76079a LW	374	rate /= 256;
6be4826e	375	ctrl \|= TIMER_CTRL_DIV256;
bb76079a LW	376	} else if (rate > 0x10000 * HZ) {
bb76079a LW	377	rate /= 16;
6be4826e RK	378	ctrl \|= TIMER_CTRL_DIV16;
6be4826e RK	379	}
bb76079a	380	timer_reload = rate / HZ;
6be4826e RK	381	writel(ctrl, clkevt_base + TIMER_CTRL);
6be4826e RK	382
4980f9bc	383	setup_irq(irq, &integrator_timer_irq);
6d8ce712	384	clockevents_config_and_register(&integrator_clockevent,
bb76079a	385	rate,
6d8ce712 LW	386	1,
6d8ce712 LW	387	0xffffU);
6be4826e RK	388	}
6be4826e RK	389
a613163d LW	390	void __init ap_init_early(void)
	391	{
	392	}
	393
6bb27d73	394	static void __init ap_of_timer_init(void)
4980f9bc LW	395	{
	396	struct device_node *node;
	397	const char *path;
	398	void __iomem *base;
	399	int err;
	400	int irq;
	401	struct clk *clk;
	402	unsigned long rate;
	403
09c978bc	404	of_clk_init(NULL);
4980f9bc LW	405
	406	err = of_property_read_string(of_aliases,
	407	"arm,timer-primary", &path);
	408	if (WARN_ON(err))
	409	return;
	410	node = of_find_node_by_path(path);
	411	base = of_iomap(node, 0);
	412	if (WARN_ON(!base))
	413	return;
09c978bc LW	414
	415	clk = of_clk_get(node, 0);
	416	BUG_ON(IS_ERR(clk));
	417	clk_prepare_enable(clk);
	418	rate = clk_get_rate(clk);
	419
4980f9bc LW	420	writel(0, base + TIMER_CTRL);
	421	integrator_clocksource_init(rate, base);
	422
	423	err = of_property_read_string(of_aliases,
	424	"arm,timer-secondary", &path);
	425	if (WARN_ON(err))
	426	return;
	427	node = of_find_node_by_path(path);
	428	base = of_iomap(node, 0);
	429	if (WARN_ON(!base))
	430	return;
	431	irq = irq_of_parse_and_map(node, 0);
09c978bc LW	432
	433	clk = of_clk_get(node, 0);
	434	BUG_ON(IS_ERR(clk));
	435	clk_prepare_enable(clk);
	436	rate = clk_get_rate(clk);
	437
4980f9bc LW	438	writel(0, base + TIMER_CTRL);
	439	integrator_clockevent_init(rate, base, irq);
	440	}
	441
4980f9bc LW	442	static const struct of_device_id fpga_irq_of_match[] __initconst = {
	443	{ .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
	444	{ /* Sentinel */ }
	445	};
	446
	447	static void __init ap_init_irq_of(void)
	448	{
bb4dbefe	449	cm_init();
4980f9bc	450	of_irq_init(fpga_irq_of_match);
4980f9bc LW	451	}
4980f9bc LW	452
4672cddf LW	453	/* For the Device Tree, add in the UART callbacks as AUXDATA */
	454	static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
	455	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
	456	"rtc", NULL),
	457	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
379df279	458	"uart0", &ap_uart_data),
4672cddf	459	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
379df279	460	"uart1", &ap_uart_data),
4672cddf LW	461	OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
	462	"kmi0", NULL),
	463	OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
	464	"kmi1", NULL),
73efd530 LW	465	OF_DEV_AUXDATA("cfi-flash", INTEGRATOR_FLASH_BASE,
73efd530 LW	466	"physmap-flash", &ap_flash_data),
4672cddf LW	467	{ /* sentinel */ },
	468	};
	469
df36680f LW	470	static const struct of_device_id ap_syscon_match[] = {
	471	{ .compatible = "arm,integrator-ap-syscon"},
	472	{ },
	473	};
	474
307b9667 LW	475	static const struct of_device_id ebi_match[] = {
	476	{ .compatible = "arm,external-bus-interface"},
	477	{ },
	478	};
	479
4672cddf LW	480	static void __init ap_init_of(void)
	481	{
	482	unsigned long sc_dec;
e67ae6be	483	struct device_node *syscon;
307b9667	484	struct device_node *ebi;
e67ae6be LW	485	struct device *parent;
	486	struct soc_device *soc_dev;
	487	struct soc_device_attribute *soc_dev_attr;
	488	u32 ap_sc_id;
4672cddf LW	489	int i;
4672cddf LW	490
11f9323a	491	syscon = of_find_matching_node(NULL, ap_syscon_match);
e67ae6be LW	492	if (!syscon)
e67ae6be LW	493	return;
11f9323a	494	ebi = of_find_matching_node(NULL, ebi_match);
307b9667 LW	495	if (!ebi)
307b9667 LW	496	return;
e67ae6be LW	497
	498	ap_syscon_base = of_iomap(syscon, 0);
	499	if (!ap_syscon_base)
	500	return;
307b9667 LW	501	ebi_base = of_iomap(ebi, 0);
	502	if (!ebi_base)
	503	return;
e67ae6be	504
11f9323a LW	505	of_platform_populate(NULL, of_default_bus_match_table,
	506	ap_auxdata_lookup, NULL);
	507
e67ae6be LW	508	ap_sc_id = readl(ap_syscon_base);
	509
	510	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
	511	if (!soc_dev_attr)
	512	return;
	513
11f9323a LW	514	soc_dev_attr->soc_id = "XVC";
11f9323a LW	515	soc_dev_attr->machine = "Integrator/AP";
e67ae6be LW	516	soc_dev_attr->family = "Integrator";
	517	soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
	518	'A' + (ap_sc_id & 0x0f));
	519
	520	soc_dev = soc_device_register(soc_dev_attr);
b269b170	521	if (IS_ERR(soc_dev)) {
e67ae6be LW	522	kfree(soc_dev_attr->revision);
	523	kfree(soc_dev_attr);
	524	return;
	525	}
	526
	527	parent = soc_device_to_device(soc_dev);
b269b170	528	integrator_init_sysfs(parent, ap_sc_id);
e67ae6be	529
83feba51	530	sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET);
4672cddf LW	531	for (i = 0; i < 4; i++) {
	532	struct lm_device *lmdev;
	533
	534	if ((sc_dec & (16 << i)) == 0)
	535	continue;
	536
	537	lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
	538	if (!lmdev)
	539	continue;
	540
	541	lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
	542	lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
	543	lmdev->resource.flags = IORESOURCE_MEM;
a6720258	544	lmdev->irq = irq_of_parse_and_map(syscon, i);
4672cddf LW	545	lmdev->id = i;
	546
	547	lm_device_register(lmdev);
	548	}
	549	}
	550
4980f9bc LW	551	static const char * ap_dt_board_compat[] = {
	552	"arm,integrator-ap",
	553	NULL,
	554	};
	555
	556	DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
	557	.reserve = integrator_reserve,
	558	.map_io = ap_map_io,
4980f9bc LW	559	.init_early = ap_init_early,
	560	.init_irq = ap_init_irq_of,
	561	.handle_irq = fpga_handle_irq,
6bb27d73	562	.init_time = ap_of_timer_init,
4672cddf	563	.init_machine = ap_init_of,
4980f9bc LW	564	.restart = integrator_restart,
	565	.dt_compat = ap_dt_board_compat,
	566	MACHINE_END