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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mach-integrator/integrator_ap.c | |
3 | * | |
4 | * Copyright (C) 2000-2003 Deep Blue Solutions Ltd | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
20 | #include <linux/types.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/list.h> | |
d052d1be | 24 | #include <linux/platform_device.h> |
1da177e4 LT |
25 | #include <linux/slab.h> |
26 | #include <linux/string.h> | |
b7808056 | 27 | #include <linux/syscore_ops.h> |
a62c80e5 RK |
28 | #include <linux/amba/bus.h> |
29 | #include <linux/amba/kmi.h> | |
6be4826e RK |
30 | #include <linux/clocksource.h> |
31 | #include <linux/clockchips.h> | |
32 | #include <linux/interrupt.h> | |
fced80c7 | 33 | #include <linux/io.h> |
2389d501 | 34 | #include <linux/irqchip/versatile-fpga.h> |
f07e762e | 35 | #include <linux/mtd/physmap.h> |
bb76079a | 36 | #include <linux/clk.h> |
a613163d | 37 | #include <linux/platform_data/clk-integrator.h> |
4980f9bc LW |
38 | #include <linux/of_irq.h> |
39 | #include <linux/of_address.h> | |
4672cddf | 40 | #include <linux/of_platform.h> |
e67ae6be LW |
41 | #include <linux/stat.h> |
42 | #include <linux/sys_soc.h> | |
379df279 | 43 | #include <linux/termios.h> |
b71d8429 | 44 | #include <video/vga.h> |
1da177e4 | 45 | |
a09e64fb | 46 | #include <mach/hardware.h> |
a285edcf | 47 | #include <mach/platform.h> |
6be4826e | 48 | #include <asm/hardware/arm_timer.h> |
1da177e4 | 49 | #include <asm/setup.h> |
4e57b681 | 50 | #include <asm/param.h> /* HZ */ |
1da177e4 | 51 | #include <asm/mach-types.h> |
a9d6d151 | 52 | #include <asm/sched_clock.h> |
1da177e4 | 53 | |
a09e64fb | 54 | #include <mach/lm.h> |
695436e3 | 55 | #include <mach/irqs.h> |
1da177e4 LT |
56 | |
57 | #include <asm/mach/arch.h> | |
1da177e4 LT |
58 | #include <asm/mach/irq.h> |
59 | #include <asm/mach/map.h> | |
68ef6322 | 60 | #include <asm/mach/pci.h> |
1da177e4 LT |
61 | #include <asm/mach/time.h> |
62 | ||
98c672cf RK |
63 | #include "common.h" |
64 | ||
83feba51 | 65 | /* Base address to the AP system controller */ |
379df279 | 66 | void __iomem *ap_syscon_base; |
83feba51 LW |
67 | |
68 | /* | |
1da177e4 LT |
69 | * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx |
70 | * is the (PA >> 12). | |
71 | * | |
72 | * Setup a VA for the Integrator interrupt controller (for header #0, | |
73 | * just for now). | |
74 | */ | |
c41b16f8 | 75 | #define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE) |
c41b16f8 RK |
76 | #define VA_EBI_BASE __io_address(INTEGRATOR_EBI_BASE) |
77 | #define VA_CMIC_BASE __io_address(INTEGRATOR_HDR_IC) | |
1da177e4 LT |
78 | |
79 | /* | |
80 | * Logical Physical | |
81 | * e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M) | |
82 | * ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M) | |
83 | * ed000000 62000000 PCI V3 regs PHYS_PCI_V3_BASE (max 64k) | |
68ef6322 | 84 | * fee00000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M) |
1da177e4 LT |
85 | * ef000000 Cache flush |
86 | * f1000000 10000000 Core module registers | |
87 | * f1100000 11000000 System controller registers | |
88 | * f1200000 12000000 EBI registers | |
89 | * f1300000 13000000 Counter/Timer | |
90 | * f1400000 14000000 Interrupt controller | |
91 | * f1600000 16000000 UART 0 | |
92 | * f1700000 17000000 UART 1 | |
93 | * f1a00000 1a000000 Debug LEDs | |
94 | * f1b00000 1b000000 GPIO | |
95 | */ | |
96 | ||
97 | static struct map_desc ap_io_desc[] __initdata = { | |
c8d27298 DS |
98 | { |
99 | .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE), | |
100 | .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE), | |
101 | .length = SZ_4K, | |
102 | .type = MT_DEVICE | |
c8d27298 DS |
103 | }, { |
104 | .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE), | |
105 | .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE), | |
106 | .length = SZ_4K, | |
107 | .type = MT_DEVICE | |
108 | }, { | |
109 | .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE), | |
110 | .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE), | |
111 | .length = SZ_4K, | |
112 | .type = MT_DEVICE | |
113 | }, { | |
114 | .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE), | |
115 | .pfn = __phys_to_pfn(INTEGRATOR_IC_BASE), | |
116 | .length = SZ_4K, | |
117 | .type = MT_DEVICE | |
118 | }, { | |
119 | .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE), | |
120 | .pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE), | |
121 | .length = SZ_4K, | |
122 | .type = MT_DEVICE | |
c8d27298 DS |
123 | }, { |
124 | .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE), | |
125 | .pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE), | |
126 | .length = SZ_4K, | |
127 | .type = MT_DEVICE | |
128 | }, { | |
da7ba956 RK |
129 | .virtual = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE), |
130 | .pfn = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE), | |
c8d27298 DS |
131 | .length = SZ_4K, |
132 | .type = MT_DEVICE | |
133 | }, { | |
b7a3f8db | 134 | .virtual = (unsigned long)PCI_MEMORY_VADDR, |
c8d27298 DS |
135 | .pfn = __phys_to_pfn(PHYS_PCI_MEM_BASE), |
136 | .length = SZ_16M, | |
137 | .type = MT_DEVICE | |
138 | }, { | |
b7a3f8db | 139 | .virtual = (unsigned long)PCI_CONFIG_VADDR, |
c8d27298 DS |
140 | .pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE), |
141 | .length = SZ_16M, | |
142 | .type = MT_DEVICE | |
143 | }, { | |
b7a3f8db | 144 | .virtual = (unsigned long)PCI_V3_VADDR, |
c8d27298 DS |
145 | .pfn = __phys_to_pfn(PHYS_PCI_V3_BASE), |
146 | .length = SZ_64K, | |
147 | .type = MT_DEVICE | |
c8d27298 | 148 | } |
1da177e4 LT |
149 | }; |
150 | ||
151 | static void __init ap_map_io(void) | |
152 | { | |
153 | iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc)); | |
21c8715f | 154 | vga_base = (unsigned long)PCI_MEMORY_VADDR; |
68ef6322 | 155 | pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE)); |
1da177e4 LT |
156 | } |
157 | ||
1da177e4 LT |
158 | #ifdef CONFIG_PM |
159 | static unsigned long ic_irq_enable; | |
160 | ||
b7808056 | 161 | static int irq_suspend(void) |
1da177e4 LT |
162 | { |
163 | ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE); | |
164 | return 0; | |
165 | } | |
166 | ||
b7808056 | 167 | static void irq_resume(void) |
1da177e4 LT |
168 | { |
169 | /* disable all irq sources */ | |
170 | writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR); | |
171 | writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR); | |
172 | writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR); | |
173 | ||
174 | writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET); | |
1da177e4 LT |
175 | } |
176 | #else | |
177 | #define irq_suspend NULL | |
178 | #define irq_resume NULL | |
179 | #endif | |
180 | ||
b7808056 | 181 | static struct syscore_ops irq_syscore_ops = { |
1da177e4 LT |
182 | .suspend = irq_suspend, |
183 | .resume = irq_resume, | |
184 | }; | |
185 | ||
b7808056 | 186 | static int __init irq_syscore_init(void) |
1da177e4 | 187 | { |
b7808056 RW |
188 | register_syscore_ops(&irq_syscore_ops); |
189 | ||
190 | return 0; | |
1da177e4 LT |
191 | } |
192 | ||
b7808056 | 193 | device_initcall(irq_syscore_init); |
1da177e4 LT |
194 | |
195 | /* | |
196 | * Flash handling. | |
197 | */ | |
1da177e4 LT |
198 | #define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET) |
199 | #define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET) | |
200 | ||
f07e762e | 201 | static int ap_flash_init(struct platform_device *dev) |
1da177e4 LT |
202 | { |
203 | u32 tmp; | |
204 | ||
83feba51 LW |
205 | writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, |
206 | ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET); | |
1da177e4 LT |
207 | |
208 | tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE; | |
209 | writel(tmp, EBI_CSR1); | |
210 | ||
211 | if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) { | |
212 | writel(0xa05f, EBI_LOCK); | |
213 | writel(tmp, EBI_CSR1); | |
214 | writel(0, EBI_LOCK); | |
215 | } | |
216 | return 0; | |
217 | } | |
218 | ||
f07e762e | 219 | static void ap_flash_exit(struct platform_device *dev) |
1da177e4 LT |
220 | { |
221 | u32 tmp; | |
222 | ||
83feba51 LW |
223 | writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, |
224 | ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET); | |
1da177e4 LT |
225 | |
226 | tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE; | |
227 | writel(tmp, EBI_CSR1); | |
228 | ||
229 | if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) { | |
230 | writel(0xa05f, EBI_LOCK); | |
231 | writel(tmp, EBI_CSR1); | |
232 | writel(0, EBI_LOCK); | |
233 | } | |
234 | } | |
235 | ||
667f390b | 236 | static void ap_flash_set_vpp(struct platform_device *pdev, int on) |
1da177e4 | 237 | { |
83feba51 LW |
238 | if (on) |
239 | writel(INTEGRATOR_SC_CTRL_nFLVPPEN, | |
240 | ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET); | |
241 | else | |
242 | writel(INTEGRATOR_SC_CTRL_nFLVPPEN, | |
243 | ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET); | |
1da177e4 LT |
244 | } |
245 | ||
f07e762e | 246 | static struct physmap_flash_data ap_flash_data = { |
1da177e4 LT |
247 | .width = 4, |
248 | .init = ap_flash_init, | |
249 | .exit = ap_flash_exit, | |
250 | .set_vpp = ap_flash_set_vpp, | |
251 | }; | |
252 | ||
379df279 LW |
253 | /* |
254 | * For the PL010 found in the Integrator/AP some of the UART control is | |
255 | * implemented in the system controller and accessed using a callback | |
256 | * from the driver. | |
257 | */ | |
258 | static void integrator_uart_set_mctrl(struct amba_device *dev, | |
259 | void __iomem *base, unsigned int mctrl) | |
260 | { | |
261 | unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask; | |
262 | u32 phybase = dev->res.start; | |
263 | ||
264 | if (phybase == INTEGRATOR_UART0_BASE) { | |
265 | /* UART0 */ | |
266 | rts_mask = 1 << 4; | |
267 | dtr_mask = 1 << 5; | |
268 | } else { | |
269 | /* UART1 */ | |
270 | rts_mask = 1 << 6; | |
271 | dtr_mask = 1 << 7; | |
272 | } | |
273 | ||
274 | if (mctrl & TIOCM_RTS) | |
275 | ctrlc |= rts_mask; | |
276 | else | |
277 | ctrls |= rts_mask; | |
278 | ||
279 | if (mctrl & TIOCM_DTR) | |
280 | ctrlc |= dtr_mask; | |
281 | else | |
282 | ctrls |= dtr_mask; | |
283 | ||
284 | __raw_writel(ctrls, ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET); | |
285 | __raw_writel(ctrlc, ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET); | |
286 | } | |
287 | ||
288 | struct amba_pl010_data ap_uart_data = { | |
289 | .set_mctrl = integrator_uart_set_mctrl, | |
290 | }; | |
291 | ||
6be4826e RK |
292 | /* |
293 | * Where is the timer (VA)? | |
294 | */ | |
b7a3f8db AB |
295 | #define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE) |
296 | #define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE) | |
297 | #define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE) | |
6be4826e | 298 | |
6be4826e RK |
299 | static unsigned long timer_reload; |
300 | ||
a9d6d151 LW |
301 | static u32 notrace integrator_read_sched_clock(void) |
302 | { | |
303 | return -readl((void __iomem *) TIMER2_VA_BASE + TIMER_VALUE); | |
304 | } | |
305 | ||
4980f9bc LW |
306 | static void integrator_clocksource_init(unsigned long inrate, |
307 | void __iomem *base) | |
6be4826e | 308 | { |
bb9ea778 | 309 | u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC; |
bb76079a | 310 | unsigned long rate = inrate; |
6be4826e | 311 | |
bb76079a LW |
312 | if (rate >= 1500000) { |
313 | rate /= 16; | |
bb9ea778 | 314 | ctrl |= TIMER_CTRL_DIV16; |
6be4826e RK |
315 | } |
316 | ||
6be4826e | 317 | writel(0xffff, base + TIMER_LOAD); |
bb9ea778 | 318 | writel(ctrl, base + TIMER_CTRL); |
6be4826e | 319 | |
c5039f52 | 320 | clocksource_mmio_init(base + TIMER_VALUE, "timer2", |
bb76079a | 321 | rate, 200, 16, clocksource_mmio_readl_down); |
a9d6d151 | 322 | setup_sched_clock(integrator_read_sched_clock, 16, rate); |
6be4826e RK |
323 | } |
324 | ||
4980f9bc | 325 | static void __iomem * clkevt_base; |
6be4826e RK |
326 | |
327 | /* | |
328 | * IRQ handler for the timer | |
329 | */ | |
330 | static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id) | |
331 | { | |
332 | struct clock_event_device *evt = dev_id; | |
333 | ||
334 | /* clear the interrupt */ | |
335 | writel(1, clkevt_base + TIMER_INTCLR); | |
336 | ||
337 | evt->event_handler(evt); | |
338 | ||
339 | return IRQ_HANDLED; | |
340 | } | |
341 | ||
342 | static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) | |
343 | { | |
344 | u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE; | |
345 | ||
02f56321 LW |
346 | /* Disable timer */ |
347 | writel(ctrl, clkevt_base + TIMER_CTRL); | |
6be4826e | 348 | |
02f56321 LW |
349 | switch (mode) { |
350 | case CLOCK_EVT_MODE_PERIODIC: | |
351 | /* Enable the timer and start the periodic tick */ | |
6be4826e RK |
352 | writel(timer_reload, clkevt_base + TIMER_LOAD); |
353 | ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE; | |
02f56321 LW |
354 | writel(ctrl, clkevt_base + TIMER_CTRL); |
355 | break; | |
356 | case CLOCK_EVT_MODE_ONESHOT: | |
357 | /* Leave the timer disabled, .set_next_event will enable it */ | |
358 | ctrl &= ~TIMER_CTRL_PERIODIC; | |
359 | writel(ctrl, clkevt_base + TIMER_CTRL); | |
360 | break; | |
361 | case CLOCK_EVT_MODE_UNUSED: | |
362 | case CLOCK_EVT_MODE_SHUTDOWN: | |
363 | case CLOCK_EVT_MODE_RESUME: | |
364 | default: | |
365 | /* Just leave in disabled state */ | |
366 | break; | |
6be4826e RK |
367 | } |
368 | ||
6be4826e RK |
369 | } |
370 | ||
371 | static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt) | |
372 | { | |
373 | unsigned long ctrl = readl(clkevt_base + TIMER_CTRL); | |
374 | ||
375 | writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL); | |
376 | writel(next, clkevt_base + TIMER_LOAD); | |
377 | writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL); | |
378 | ||
379 | return 0; | |
380 | } | |
381 | ||
382 | static struct clock_event_device integrator_clockevent = { | |
383 | .name = "timer1", | |
02f56321 | 384 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, |
6be4826e RK |
385 | .set_mode = clkevt_set_mode, |
386 | .set_next_event = clkevt_set_next_event, | |
387 | .rating = 300, | |
6be4826e RK |
388 | }; |
389 | ||
390 | static struct irqaction integrator_timer_irq = { | |
391 | .name = "timer", | |
392 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | |
393 | .handler = integrator_timer_interrupt, | |
394 | .dev_id = &integrator_clockevent, | |
395 | }; | |
396 | ||
4980f9bc LW |
397 | static void integrator_clockevent_init(unsigned long inrate, |
398 | void __iomem *base, int irq) | |
6be4826e | 399 | { |
bb76079a | 400 | unsigned long rate = inrate; |
6be4826e RK |
401 | unsigned int ctrl = 0; |
402 | ||
4980f9bc | 403 | clkevt_base = base; |
6d8ce712 | 404 | /* Calculate and program a divisor */ |
bb76079a LW |
405 | if (rate > 0x100000 * HZ) { |
406 | rate /= 256; | |
6be4826e | 407 | ctrl |= TIMER_CTRL_DIV256; |
bb76079a LW |
408 | } else if (rate > 0x10000 * HZ) { |
409 | rate /= 16; | |
6be4826e RK |
410 | ctrl |= TIMER_CTRL_DIV16; |
411 | } | |
bb76079a | 412 | timer_reload = rate / HZ; |
6be4826e RK |
413 | writel(ctrl, clkevt_base + TIMER_CTRL); |
414 | ||
4980f9bc | 415 | setup_irq(irq, &integrator_timer_irq); |
6d8ce712 | 416 | clockevents_config_and_register(&integrator_clockevent, |
bb76079a | 417 | rate, |
6d8ce712 LW |
418 | 1, |
419 | 0xffffU); | |
6be4826e RK |
420 | } |
421 | ||
a613163d LW |
422 | void __init ap_init_early(void) |
423 | { | |
424 | } | |
425 | ||
4980f9bc LW |
426 | #ifdef CONFIG_OF |
427 | ||
428 | static void __init ap_init_timer_of(void) | |
429 | { | |
430 | struct device_node *node; | |
431 | const char *path; | |
432 | void __iomem *base; | |
433 | int err; | |
434 | int irq; | |
435 | struct clk *clk; | |
436 | unsigned long rate; | |
437 | ||
438 | clk = clk_get_sys("ap_timer", NULL); | |
439 | BUG_ON(IS_ERR(clk)); | |
440 | clk_prepare_enable(clk); | |
441 | rate = clk_get_rate(clk); | |
442 | ||
443 | err = of_property_read_string(of_aliases, | |
444 | "arm,timer-primary", &path); | |
445 | if (WARN_ON(err)) | |
446 | return; | |
447 | node = of_find_node_by_path(path); | |
448 | base = of_iomap(node, 0); | |
449 | if (WARN_ON(!base)) | |
450 | return; | |
451 | writel(0, base + TIMER_CTRL); | |
452 | integrator_clocksource_init(rate, base); | |
453 | ||
454 | err = of_property_read_string(of_aliases, | |
455 | "arm,timer-secondary", &path); | |
456 | if (WARN_ON(err)) | |
457 | return; | |
458 | node = of_find_node_by_path(path); | |
459 | base = of_iomap(node, 0); | |
460 | if (WARN_ON(!base)) | |
461 | return; | |
462 | irq = irq_of_parse_and_map(node, 0); | |
463 | writel(0, base + TIMER_CTRL); | |
464 | integrator_clockevent_init(rate, base, irq); | |
465 | } | |
466 | ||
467 | static struct sys_timer ap_of_timer = { | |
468 | .init = ap_init_timer_of, | |
469 | }; | |
470 | ||
471 | static const struct of_device_id fpga_irq_of_match[] __initconst = { | |
472 | { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, }, | |
473 | { /* Sentinel */ } | |
474 | }; | |
475 | ||
476 | static void __init ap_init_irq_of(void) | |
477 | { | |
478 | /* disable core module IRQs */ | |
479 | writel(0xffffffffU, VA_CMIC_BASE + IRQ_ENABLE_CLEAR); | |
480 | of_irq_init(fpga_irq_of_match); | |
481 | integrator_clk_init(false); | |
482 | } | |
483 | ||
4672cddf LW |
484 | /* For the Device Tree, add in the UART callbacks as AUXDATA */ |
485 | static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = { | |
486 | OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE, | |
487 | "rtc", NULL), | |
488 | OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE, | |
379df279 | 489 | "uart0", &ap_uart_data), |
4672cddf | 490 | OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE, |
379df279 | 491 | "uart1", &ap_uart_data), |
4672cddf LW |
492 | OF_DEV_AUXDATA("arm,primecell", KMI0_BASE, |
493 | "kmi0", NULL), | |
494 | OF_DEV_AUXDATA("arm,primecell", KMI1_BASE, | |
495 | "kmi1", NULL), | |
73efd530 LW |
496 | OF_DEV_AUXDATA("cfi-flash", INTEGRATOR_FLASH_BASE, |
497 | "physmap-flash", &ap_flash_data), | |
4672cddf LW |
498 | { /* sentinel */ }, |
499 | }; | |
500 | ||
501 | static void __init ap_init_of(void) | |
502 | { | |
503 | unsigned long sc_dec; | |
e67ae6be LW |
504 | struct device_node *root; |
505 | struct device_node *syscon; | |
506 | struct device *parent; | |
507 | struct soc_device *soc_dev; | |
508 | struct soc_device_attribute *soc_dev_attr; | |
509 | u32 ap_sc_id; | |
510 | int err; | |
4672cddf LW |
511 | int i; |
512 | ||
e67ae6be LW |
513 | /* Here we create an SoC device for the root node */ |
514 | root = of_find_node_by_path("/"); | |
515 | if (!root) | |
516 | return; | |
517 | syscon = of_find_node_by_path("/syscon"); | |
518 | if (!syscon) | |
519 | return; | |
520 | ||
521 | ap_syscon_base = of_iomap(syscon, 0); | |
522 | if (!ap_syscon_base) | |
523 | return; | |
524 | ||
525 | ap_sc_id = readl(ap_syscon_base); | |
526 | ||
527 | soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); | |
528 | if (!soc_dev_attr) | |
529 | return; | |
530 | ||
531 | err = of_property_read_string(root, "compatible", | |
532 | &soc_dev_attr->soc_id); | |
533 | if (err) | |
534 | return; | |
535 | err = of_property_read_string(root, "model", &soc_dev_attr->machine); | |
536 | if (err) | |
537 | return; | |
538 | soc_dev_attr->family = "Integrator"; | |
539 | soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c", | |
540 | 'A' + (ap_sc_id & 0x0f)); | |
541 | ||
542 | soc_dev = soc_device_register(soc_dev_attr); | |
543 | if (IS_ERR_OR_NULL(soc_dev)) { | |
544 | kfree(soc_dev_attr->revision); | |
545 | kfree(soc_dev_attr); | |
546 | return; | |
547 | } | |
548 | ||
549 | parent = soc_device_to_device(soc_dev); | |
550 | ||
551 | if (!IS_ERR_OR_NULL(parent)) | |
552 | integrator_init_sysfs(parent, ap_sc_id); | |
553 | ||
554 | of_platform_populate(root, of_default_bus_match_table, | |
555 | ap_auxdata_lookup, parent); | |
4672cddf | 556 | |
83feba51 | 557 | sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET); |
4672cddf LW |
558 | for (i = 0; i < 4; i++) { |
559 | struct lm_device *lmdev; | |
560 | ||
561 | if ((sc_dec & (16 << i)) == 0) | |
562 | continue; | |
563 | ||
564 | lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL); | |
565 | if (!lmdev) | |
566 | continue; | |
567 | ||
568 | lmdev->resource.start = 0xc0000000 + 0x10000000 * i; | |
569 | lmdev->resource.end = lmdev->resource.start + 0x0fffffff; | |
570 | lmdev->resource.flags = IORESOURCE_MEM; | |
571 | lmdev->irq = IRQ_AP_EXPINT0 + i; | |
572 | lmdev->id = i; | |
573 | ||
574 | lm_device_register(lmdev); | |
575 | } | |
576 | } | |
577 | ||
4980f9bc LW |
578 | static const char * ap_dt_board_compat[] = { |
579 | "arm,integrator-ap", | |
580 | NULL, | |
581 | }; | |
582 | ||
583 | DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)") | |
584 | .reserve = integrator_reserve, | |
585 | .map_io = ap_map_io, | |
4980f9bc LW |
586 | .init_early = ap_init_early, |
587 | .init_irq = ap_init_irq_of, | |
588 | .handle_irq = fpga_handle_irq, | |
589 | .timer = &ap_of_timer, | |
4672cddf | 590 | .init_machine = ap_init_of, |
4980f9bc LW |
591 | .restart = integrator_restart, |
592 | .dt_compat = ap_dt_board_compat, | |
593 | MACHINE_END | |
594 | ||
595 | #endif | |
596 | ||
597 | #ifdef CONFIG_ATAGS | |
598 | ||
83feba51 LW |
599 | /* |
600 | * For the ATAG boot some static mappings are needed. This will | |
601 | * go away with the ATAG support down the road. | |
602 | */ | |
603 | ||
604 | static struct map_desc ap_io_desc_atag[] __initdata = { | |
605 | { | |
606 | .virtual = IO_ADDRESS(INTEGRATOR_SC_BASE), | |
607 | .pfn = __phys_to_pfn(INTEGRATOR_SC_BASE), | |
608 | .length = SZ_4K, | |
609 | .type = MT_DEVICE | |
610 | }, | |
611 | }; | |
612 | ||
613 | static void __init ap_map_io_atag(void) | |
614 | { | |
615 | iotable_init(ap_io_desc_atag, ARRAY_SIZE(ap_io_desc_atag)); | |
616 | ap_syscon_base = __io_address(INTEGRATOR_SC_BASE); | |
617 | ap_map_io(); | |
618 | } | |
619 | ||
6be4826e | 620 | /* |
4980f9bc LW |
621 | * This is where non-devicetree initialization code is collected and stashed |
622 | * for eventual deletion. | |
6be4826e | 623 | */ |
4980f9bc | 624 | |
73efd530 LW |
625 | static struct resource cfi_flash_resource = { |
626 | .start = INTEGRATOR_FLASH_BASE, | |
627 | .end = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1, | |
628 | .flags = IORESOURCE_MEM, | |
629 | }; | |
630 | ||
631 | static struct platform_device cfi_flash_device = { | |
632 | .name = "physmap-flash", | |
633 | .id = 0, | |
634 | .dev = { | |
635 | .platform_data = &ap_flash_data, | |
636 | }, | |
637 | .num_resources = 1, | |
638 | .resource = &cfi_flash_resource, | |
639 | }; | |
640 | ||
1da177e4 LT |
641 | static void __init ap_init_timer(void) |
642 | { | |
bb76079a LW |
643 | struct clk *clk; |
644 | unsigned long rate; | |
645 | ||
646 | clk = clk_get_sys("ap_timer", NULL); | |
647 | BUG_ON(IS_ERR(clk)); | |
8bb8148c | 648 | clk_prepare_enable(clk); |
bb76079a | 649 | rate = clk_get_rate(clk); |
6be4826e RK |
650 | |
651 | writel(0, TIMER0_VA_BASE + TIMER_CTRL); | |
652 | writel(0, TIMER1_VA_BASE + TIMER_CTRL); | |
653 | writel(0, TIMER2_VA_BASE + TIMER_CTRL); | |
654 | ||
4980f9bc LW |
655 | integrator_clocksource_init(rate, (void __iomem *)TIMER2_VA_BASE); |
656 | integrator_clockevent_init(rate, (void __iomem *)TIMER1_VA_BASE, | |
657 | IRQ_TIMERINT1); | |
1da177e4 LT |
658 | } |
659 | ||
660 | static struct sys_timer ap_timer = { | |
661 | .init = ap_init_timer, | |
1da177e4 LT |
662 | }; |
663 | ||
4980f9bc LW |
664 | #define INTEGRATOR_SC_VALID_INT 0x003fffff |
665 | ||
666 | static void __init ap_init_irq(void) | |
667 | { | |
668 | /* Disable all interrupts initially. */ | |
669 | /* Do the core module ones */ | |
670 | writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR); | |
671 | ||
672 | /* do the header card stuff next */ | |
673 | writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR); | |
674 | writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR); | |
675 | ||
676 | fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START, | |
677 | -1, INTEGRATOR_SC_VALID_INT, NULL); | |
678 | integrator_clk_init(false); | |
679 | } | |
680 | ||
4672cddf LW |
681 | static void __init ap_init(void) |
682 | { | |
683 | unsigned long sc_dec; | |
684 | int i; | |
685 | ||
686 | platform_device_register(&cfi_flash_device); | |
687 | ||
83feba51 | 688 | sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET); |
4672cddf LW |
689 | for (i = 0; i < 4; i++) { |
690 | struct lm_device *lmdev; | |
691 | ||
692 | if ((sc_dec & (16 << i)) == 0) | |
693 | continue; | |
694 | ||
695 | lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL); | |
696 | if (!lmdev) | |
697 | continue; | |
698 | ||
699 | lmdev->resource.start = 0xc0000000 + 0x10000000 * i; | |
700 | lmdev->resource.end = lmdev->resource.start + 0x0fffffff; | |
701 | lmdev->resource.flags = IORESOURCE_MEM; | |
702 | lmdev->irq = IRQ_AP_EXPINT0 + i; | |
703 | lmdev->id = i; | |
704 | ||
705 | lm_device_register(lmdev); | |
706 | } | |
707 | ||
708 | integrator_init(false); | |
709 | } | |
710 | ||
1da177e4 | 711 | MACHINE_START(INTEGRATOR, "ARM-Integrator") |
e9dea0c6 | 712 | /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ |
c5e587a2 | 713 | .atag_offset = 0x100, |
98c672cf | 714 | .reserve = integrator_reserve, |
83feba51 | 715 | .map_io = ap_map_io_atag, |
a613163d | 716 | .init_early = ap_init_early, |
e9dea0c6 | 717 | .init_irq = ap_init_irq, |
3108e6ab | 718 | .handle_irq = fpga_handle_irq, |
1da177e4 | 719 | .timer = &ap_timer, |
e9dea0c6 | 720 | .init_machine = ap_init, |
6338b66f | 721 | .restart = integrator_restart, |
1da177e4 | 722 | MACHINE_END |
4980f9bc LW |
723 | |
724 | #endif |