[mirror_ubuntu-zesty-kernel.git] / arch / arm / mach-integrator / integrator_ap.c

/*
 *  linux/arch/arm/mach-integrator/integrator_ap.c
 *
 *  Copyright (C) 2000-2003 Deep Blue Solutions Ltd
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/syscore_ops.h>
#include <linux/amba/bus.h>
#include <linux/amba/kmi.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/mtd/physmap.h>
#include <linux/clk.h>
#include <video/vga.h>

#include <mach/hardware.h>
#include <mach/platform.h>
#include <asm/hardware/arm_timer.h>
#include <asm/setup.h>
#include <asm/param.h>		/* HZ */
#include <asm/mach-types.h>
#include <asm/sched_clock.h>

#include <mach/lm.h>
#include <mach/irqs.h>

#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>

#include <plat/fpga-irq.h>

#include "common.h"

/* 
 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
 * is the (PA >> 12).
 *
 * Setup a VA for the Integrator interrupt controller (for header #0,
 * just for now).
 */
#define VA_IC_BASE	__io_address(INTEGRATOR_IC_BASE)
#define VA_SC_BASE	__io_address(INTEGRATOR_SC_BASE)
#define VA_EBI_BASE	__io_address(INTEGRATOR_EBI_BASE)
#define VA_CMIC_BASE	__io_address(INTEGRATOR_HDR_IC)

/*
 * Logical      Physical
 * e8000000	40000000	PCI memory		PHYS_PCI_MEM_BASE	(max 512M)
 * ec000000	61000000	PCI config space	PHYS_PCI_CONFIG_BASE	(max 16M)
 * ed000000	62000000	PCI V3 regs		PHYS_PCI_V3_BASE	(max 64k)
 * ee000000	60000000	PCI IO			PHYS_PCI_IO_BASE	(max 16M)
 * ef000000			Cache flush
 * f1000000	10000000	Core module registers
 * f1100000	11000000	System controller registers
 * f1200000	12000000	EBI registers
 * f1300000	13000000	Counter/Timer
 * f1400000	14000000	Interrupt controller
 * f1600000	16000000	UART 0
 * f1700000	17000000	UART 1
 * f1a00000	1a000000	Debug LEDs
 * f1b00000	1b000000	GPIO
 */

static struct map_desc ap_io_desc[] __initdata = {
	{
		.virtual	= IO_ADDRESS(INTEGRATOR_HDR_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_HDR_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_SC_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_SC_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_EBI_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_EBI_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_CT_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_CT_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_IC_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_IC_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_UART0_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_UART0_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_UART1_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_UART1_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_DBG_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_DBG_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= PCI_MEMORY_VADDR,
		.pfn		= __phys_to_pfn(PHYS_PCI_MEM_BASE),
		.length		= SZ_16M,
		.type		= MT_DEVICE
	}, {
		.virtual	= PCI_CONFIG_VADDR,
		.pfn		= __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
		.length		= SZ_16M,
		.type		= MT_DEVICE
	}, {
		.virtual	= PCI_V3_VADDR,
		.pfn		= __phys_to_pfn(PHYS_PCI_V3_BASE),
		.length		= SZ_64K,
		.type		= MT_DEVICE
	}, {
		.virtual	= PCI_IO_VADDR,
		.pfn		= __phys_to_pfn(PHYS_PCI_IO_BASE),
		.length		= SZ_64K,
		.type		= MT_DEVICE
	}
};

static void __init ap_map_io(void)
{
	iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
	vga_base = PCI_MEMORY_VADDR;
}

#define INTEGRATOR_SC_VALID_INT	0x003fffff

static void __init ap_init_irq(void)
{
	/* Disable all interrupts initially. */
	/* Do the core module ones */
	writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);

	/* do the header card stuff next */
	writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
	writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);

	fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START,
		-1, INTEGRATOR_SC_VALID_INT, NULL);
}

#ifdef CONFIG_PM
static unsigned long ic_irq_enable;

static int irq_suspend(void)
{
	ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
	return 0;
}

static void irq_resume(void)
{
	/* disable all irq sources */
	writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
	writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
	writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);

	writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
}
#else
#define irq_suspend NULL
#define irq_resume NULL
#endif

static struct syscore_ops irq_syscore_ops = {
	.suspend	= irq_suspend,
	.resume		= irq_resume,
};

static int __init irq_syscore_init(void)
{
	register_syscore_ops(&irq_syscore_ops);

	return 0;
}

device_initcall(irq_syscore_init);

/*
 * Flash handling.
 */
#define SC_CTRLC (VA_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
#define SC_CTRLS (VA_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
#define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
#define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)

static int ap_flash_init(struct platform_device *dev)
{
	u32 tmp;

	writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);

	tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE;
	writel(tmp, EBI_CSR1);

	if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
		writel(0xa05f, EBI_LOCK);
		writel(tmp, EBI_CSR1);
		writel(0, EBI_LOCK);
	}
	return 0;
}

static void ap_flash_exit(struct platform_device *dev)
{
	u32 tmp;

	writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);

	tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
	writel(tmp, EBI_CSR1);

	if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
		writel(0xa05f, EBI_LOCK);
		writel(tmp, EBI_CSR1);
		writel(0, EBI_LOCK);
	}
}

static void ap_flash_set_vpp(struct platform_device *pdev, int on)
{
	void __iomem *reg = on ? SC_CTRLS : SC_CTRLC;

	writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg);
}

static struct physmap_flash_data ap_flash_data = {
	.width		= 4,
	.init		= ap_flash_init,
	.exit		= ap_flash_exit,
	.set_vpp	= ap_flash_set_vpp,
};

static struct resource cfi_flash_resource = {
	.start		= INTEGRATOR_FLASH_BASE,
	.end		= INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
	.flags		= IORESOURCE_MEM,
};

static struct platform_device cfi_flash_device = {
	.name		= "physmap-flash",
	.id		= 0,
	.dev		= {
		.platform_data	= &ap_flash_data,
	},
	.num_resources	= 1,
	.resource	= &cfi_flash_resource,
};

static void __init ap_init(void)
{
	unsigned long sc_dec;
	int i;

	platform_device_register(&cfi_flash_device);

	sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
	for (i = 0; i < 4; i++) {
		struct lm_device *lmdev;

		if ((sc_dec & (16 << i)) == 0)
			continue;

		lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
		if (!lmdev)
			continue;

		lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
		lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
		lmdev->resource.flags = IORESOURCE_MEM;
		lmdev->irq = IRQ_AP_EXPINT0 + i;
		lmdev->id = i;

		lm_device_register(lmdev);
	}
}

/*
 * Where is the timer (VA)?
 */
#define TIMER0_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER0_BASE)
#define TIMER1_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER1_BASE)
#define TIMER2_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER2_BASE)

static unsigned long timer_reload;

static u32 notrace integrator_read_sched_clock(void)
{
	return -readl((void __iomem *) TIMER2_VA_BASE + TIMER_VALUE);
}

static void integrator_clocksource_init(unsigned long inrate)
{
	void __iomem *base = (void __iomem *)TIMER2_VA_BASE;
	u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
	unsigned long rate = inrate;

	if (rate >= 1500000) {
		rate /= 16;
		ctrl |= TIMER_CTRL_DIV16;
	}

	writel(0xffff, base + TIMER_LOAD);
	writel(ctrl, base + TIMER_CTRL);

	clocksource_mmio_init(base + TIMER_VALUE, "timer2",
			rate, 200, 16, clocksource_mmio_readl_down);
	setup_sched_clock(integrator_read_sched_clock, 16, rate);
}

static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE;

/*
 * IRQ handler for the timer
 */
static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	/* clear the interrupt */
	writel(1, clkevt_base + TIMER_INTCLR);

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
{
	u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;

	/* Disable timer */
	writel(ctrl, clkevt_base + TIMER_CTRL);

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		/* Enable the timer and start the periodic tick */
		writel(timer_reload, clkevt_base + TIMER_LOAD);
		ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
		writel(ctrl, clkevt_base + TIMER_CTRL);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		/* Leave the timer disabled, .set_next_event will enable it */
		ctrl &= ~TIMER_CTRL_PERIODIC;
		writel(ctrl, clkevt_base + TIMER_CTRL);
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_RESUME:
	default:
		/* Just leave in disabled state */
		break;
	}

}

static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
{
	unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);

	writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
	writel(next, clkevt_base + TIMER_LOAD);
	writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);

	return 0;
}

static struct clock_event_device integrator_clockevent = {
	.name		= "timer1",
	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.set_mode	= clkevt_set_mode,
	.set_next_event	= clkevt_set_next_event,
	.rating		= 300,
};

static struct irqaction integrator_timer_irq = {
	.name		= "timer",
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= integrator_timer_interrupt,
	.dev_id		= &integrator_clockevent,
};

static void integrator_clockevent_init(unsigned long inrate)
{
	unsigned long rate = inrate;
	unsigned int ctrl = 0;

	/* Calculate and program a divisor */
	if (rate > 0x100000 * HZ) {
		rate /= 256;
		ctrl |= TIMER_CTRL_DIV256;
	} else if (rate > 0x10000 * HZ) {
		rate /= 16;
		ctrl |= TIMER_CTRL_DIV16;
	}
	timer_reload = rate / HZ;
	writel(ctrl, clkevt_base + TIMER_CTRL);

	setup_irq(IRQ_TIMERINT1, &integrator_timer_irq);
	clockevents_config_and_register(&integrator_clockevent,
					rate,
					1,
					0xffffU);
}

/*
 * Set up timer(s).
 */
static void __init ap_init_timer(void)
{
	struct clk *clk;
	unsigned long rate;

	clk = clk_get_sys("ap_timer", NULL);
	BUG_ON(IS_ERR(clk));
	clk_enable(clk);
	rate = clk_get_rate(clk);

	writel(0, TIMER0_VA_BASE + TIMER_CTRL);
	writel(0, TIMER1_VA_BASE + TIMER_CTRL);
	writel(0, TIMER2_VA_BASE + TIMER_CTRL);

	integrator_clocksource_init(rate);
	integrator_clockevent_init(rate);
}

static struct sys_timer ap_timer = {
	.init		= ap_init_timer,
};

MACHINE_START(INTEGRATOR, "ARM-Integrator")
	/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
	.atag_offset	= 0x100,
	.reserve	= integrator_reserve,
	.map_io		= ap_map_io,
	.nr_irqs	= NR_IRQS_INTEGRATOR_AP,
	.init_early	= integrator_init_early,
	.init_irq	= ap_init_irq,
	.handle_irq	= fpga_handle_irq,
	.timer		= &ap_timer,
	.init_machine	= ap_init,
	.restart	= integrator_restart,
MACHINE_END
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-integrator/integrator_ap.c
	3	*
	4	* Copyright (C) 2000-2003 Deep Blue Solutions Ltd
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20	#include <linux/types.h>
	21	#include <linux/kernel.h>
	22	#include <linux/init.h>
	23	#include <linux/list.h>
d052d1be	24	#include <linux/platform_device.h>
1da177e4 LT	25	#include <linux/slab.h>
1da177e4 LT	26	#include <linux/string.h>
b7808056	27	#include <linux/syscore_ops.h>
a62c80e5 RK	28	#include <linux/amba/bus.h>
a62c80e5 RK	29	#include <linux/amba/kmi.h>
6be4826e RK	30	#include <linux/clocksource.h>
	31	#include <linux/clockchips.h>
	32	#include <linux/interrupt.h>
fced80c7	33	#include <linux/io.h>
f07e762e	34	#include <linux/mtd/physmap.h>
bb76079a	35	#include <linux/clk.h>
b71d8429	36	#include <video/vga.h>
1da177e4	37
a09e64fb	38	#include <mach/hardware.h>
a285edcf	39	#include <mach/platform.h>
6be4826e	40	#include <asm/hardware/arm_timer.h>
1da177e4	41	#include <asm/setup.h>
4e57b681	42	#include <asm/param.h> /* HZ */
1da177e4	43	#include <asm/mach-types.h>
a9d6d151	44	#include <asm/sched_clock.h>
1da177e4	45
a09e64fb	46	#include <mach/lm.h>
695436e3	47	#include <mach/irqs.h>
1da177e4 LT	48
1da177e4 LT	49	#include <asm/mach/arch.h>
1da177e4 LT	50	#include <asm/mach/irq.h>
	51	#include <asm/mach/map.h>
	52	#include <asm/mach/time.h>
	53
c41b16f8 RK	54	#include <plat/fpga-irq.h>
c41b16f8 RK	55
98c672cf RK	56	#include "common.h"
98c672cf RK	57
1da177e4 LT	58	/*
	59	* All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
	60	* is the (PA >> 12).
	61	*
	62	* Setup a VA for the Integrator interrupt controller (for header #0,
	63	* just for now).
	64	*/
c41b16f8 RK	65	#define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE)
	66	#define VA_SC_BASE __io_address(INTEGRATOR_SC_BASE)
	67	#define VA_EBI_BASE __io_address(INTEGRATOR_EBI_BASE)
	68	#define VA_CMIC_BASE __io_address(INTEGRATOR_HDR_IC)
1da177e4 LT	69
	70	/*
	71	* Logical Physical
	72	* e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M)
	73	* ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M)
	74	* ed000000 62000000 PCI V3 regs PHYS_PCI_V3_BASE (max 64k)
	75	* ee000000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M)
	76	* ef000000 Cache flush
	77	* f1000000 10000000 Core module registers
	78	* f1100000 11000000 System controller registers
	79	* f1200000 12000000 EBI registers
	80	* f1300000 13000000 Counter/Timer
	81	* f1400000 14000000 Interrupt controller
	82	* f1600000 16000000 UART 0
	83	* f1700000 17000000 UART 1
	84	* f1a00000 1a000000 Debug LEDs
	85	* f1b00000 1b000000 GPIO
	86	*/
	87
	88	static struct map_desc ap_io_desc[] __initdata = {
c8d27298 DS	89	{
	90	.virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
	91	.pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
	92	.length = SZ_4K,
	93	.type = MT_DEVICE
	94	}, {
	95	.virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
	96	.pfn = __phys_to_pfn(INTEGRATOR_SC_BASE),
	97	.length = SZ_4K,
	98	.type = MT_DEVICE
	99	}, {
	100	.virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
	101	.pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
	102	.length = SZ_4K,
	103	.type = MT_DEVICE
	104	}, {
	105	.virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
	106	.pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
	107	.length = SZ_4K,
	108	.type = MT_DEVICE
	109	}, {
	110	.virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
	111	.pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
	112	.length = SZ_4K,
	113	.type = MT_DEVICE
	114	}, {
	115	.virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
	116	.pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
	117	.length = SZ_4K,
	118	.type = MT_DEVICE
	119	}, {
	120	.virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE),
	121	.pfn = __phys_to_pfn(INTEGRATOR_UART1_BASE),
	122	.length = SZ_4K,
	123	.type = MT_DEVICE
	124	}, {
	125	.virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
	126	.pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
	127	.length = SZ_4K,
	128	.type = MT_DEVICE
	129	}, {
da7ba956 RK	130	.virtual = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
da7ba956 RK	131	.pfn = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
c8d27298 DS	132	.length = SZ_4K,
	133	.type = MT_DEVICE
	134	}, {
	135	.virtual = PCI_MEMORY_VADDR,
	136	.pfn = __phys_to_pfn(PHYS_PCI_MEM_BASE),
	137	.length = SZ_16M,
	138	.type = MT_DEVICE
	139	}, {
	140	.virtual = PCI_CONFIG_VADDR,
	141	.pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
	142	.length = SZ_16M,
	143	.type = MT_DEVICE
	144	}, {
	145	.virtual = PCI_V3_VADDR,
	146	.pfn = __phys_to_pfn(PHYS_PCI_V3_BASE),
	147	.length = SZ_64K,
	148	.type = MT_DEVICE
	149	}, {
	150	.virtual = PCI_IO_VADDR,
	151	.pfn = __phys_to_pfn(PHYS_PCI_IO_BASE),
	152	.length = SZ_64K,
	153	.type = MT_DEVICE
	154	}
1da177e4 LT	155	};
	156
	157	static void __init ap_map_io(void)
	158	{
	159	iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
b71d8429	160	vga_base = PCI_MEMORY_VADDR;
1da177e4 LT	161	}
	162
	163	#define INTEGRATOR_SC_VALID_INT 0x003fffff
	164
1da177e4 LT	165	static void __init ap_init_irq(void)
1da177e4 LT	166	{
1da177e4 LT	167	/* Disable all interrupts initially. */
	168	/* Do the core module ones */
	169	writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
	170
	171	/* do the header card stuff next */
	172	writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
	173	writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
	174
3108e6ab LW	175	fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START,
3108e6ab LW	176	-1, INTEGRATOR_SC_VALID_INT, NULL);
1da177e4 LT	177	}
	178
	179	#ifdef CONFIG_PM
	180	static unsigned long ic_irq_enable;
	181
b7808056	182	static int irq_suspend(void)
1da177e4 LT	183	{
	184	ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
	185	return 0;
	186	}
	187
b7808056	188	static void irq_resume(void)
1da177e4 LT	189	{
	190	/* disable all irq sources */
	191	writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
	192	writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
	193	writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
	194
	195	writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
1da177e4 LT	196	}
	197	#else
	198	#define irq_suspend NULL
	199	#define irq_resume NULL
	200	#endif
	201
b7808056	202	static struct syscore_ops irq_syscore_ops = {
1da177e4 LT	203	.suspend = irq_suspend,
	204	.resume = irq_resume,
	205	};
	206
b7808056	207	static int __init irq_syscore_init(void)
1da177e4	208	{
b7808056 RW	209	register_syscore_ops(&irq_syscore_ops);
	210
	211	return 0;
1da177e4 LT	212	}
1da177e4 LT	213
b7808056	214	device_initcall(irq_syscore_init);
1da177e4 LT	215
	216	/*
	217	* Flash handling.
	218	*/
	219	#define SC_CTRLC (VA_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
	220	#define SC_CTRLS (VA_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
	221	#define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
	222	#define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
	223
f07e762e	224	static int ap_flash_init(struct platform_device *dev)
1da177e4 LT	225	{
	226	u32 tmp;
	227
	228	writel(INTEGRATOR_SC_CTRL_nFLVPPEN \| INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
	229
	230	tmp = readl(EBI_CSR1) \| INTEGRATOR_EBI_WRITE_ENABLE;
	231	writel(tmp, EBI_CSR1);
	232
	233	if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
	234	writel(0xa05f, EBI_LOCK);
	235	writel(tmp, EBI_CSR1);
	236	writel(0, EBI_LOCK);
	237	}
	238	return 0;
	239	}
	240
f07e762e	241	static void ap_flash_exit(struct platform_device *dev)
1da177e4 LT	242	{
	243	u32 tmp;
	244
	245	writel(INTEGRATOR_SC_CTRL_nFLVPPEN \| INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
	246
	247	tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
	248	writel(tmp, EBI_CSR1);
	249
	250	if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
	251	writel(0xa05f, EBI_LOCK);
	252	writel(tmp, EBI_CSR1);
	253	writel(0, EBI_LOCK);
	254	}
	255	}
	256
667f390b	257	static void ap_flash_set_vpp(struct platform_device *pdev, int on)
1da177e4	258	{
c41b16f8	259	void __iomem *reg = on ? SC_CTRLS : SC_CTRLC;
1da177e4 LT	260
	261	writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg);
	262	}
	263
f07e762e	264	static struct physmap_flash_data ap_flash_data = {
1da177e4 LT	265	.width = 4,
	266	.init = ap_flash_init,
	267	.exit = ap_flash_exit,
	268	.set_vpp = ap_flash_set_vpp,
	269	};
	270
	271	static struct resource cfi_flash_resource = {
	272	.start = INTEGRATOR_FLASH_BASE,
	273	.end = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
	274	.flags = IORESOURCE_MEM,
	275	};
	276
	277	static struct platform_device cfi_flash_device = {
f07e762e	278	.name = "physmap-flash",
1da177e4 LT	279	.id = 0,
	280	.dev = {
	281	.platform_data = &ap_flash_data,
	282	},
	283	.num_resources = 1,
	284	.resource = &cfi_flash_resource,
	285	};
	286
	287	static void __init ap_init(void)
	288	{
	289	unsigned long sc_dec;
	290	int i;
	291
	292	platform_device_register(&cfi_flash_device);
	293
	294	sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
	295	for (i = 0; i < 4; i++) {
	296	struct lm_device *lmdev;
	297
	298	if ((sc_dec & (16 << i)) == 0)
	299	continue;
	300
d2a02b93	301	lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
1da177e4 LT	302	if (!lmdev)
	303	continue;
	304
1da177e4 LT	305	lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
	306	lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
	307	lmdev->resource.flags = IORESOURCE_MEM;
	308	lmdev->irq = IRQ_AP_EXPINT0 + i;
	309	lmdev->id = i;
	310
	311	lm_device_register(lmdev);
	312	}
	313	}
	314
6be4826e RK	315	/*
	316	* Where is the timer (VA)?
	317	*/
	318	#define TIMER0_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER0_BASE)
	319	#define TIMER1_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER1_BASE)
	320	#define TIMER2_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER2_BASE)
	321
6be4826e RK	322	static unsigned long timer_reload;
6be4826e RK	323
a9d6d151 LW	324	static u32 notrace integrator_read_sched_clock(void)
	325	{
	326	return -readl((void __iomem *) TIMER2_VA_BASE + TIMER_VALUE);
	327	}
	328
bb76079a	329	static void integrator_clocksource_init(unsigned long inrate)
6be4826e	330	{
c5039f52	331	void __iomem base = (void __iomem )TIMER2_VA_BASE;
bb9ea778	332	u32 ctrl = TIMER_CTRL_ENABLE \| TIMER_CTRL_PERIODIC;
bb76079a	333	unsigned long rate = inrate;
6be4826e	334
bb76079a LW	335	if (rate >= 1500000) {
bb76079a LW	336	rate /= 16;
bb9ea778	337	ctrl \|= TIMER_CTRL_DIV16;
6be4826e RK	338	}
6be4826e RK	339
6be4826e	340	writel(0xffff, base + TIMER_LOAD);
bb9ea778	341	writel(ctrl, base + TIMER_CTRL);
6be4826e	342
c5039f52	343	clocksource_mmio_init(base + TIMER_VALUE, "timer2",
bb76079a	344	rate, 200, 16, clocksource_mmio_readl_down);
a9d6d151	345	setup_sched_clock(integrator_read_sched_clock, 16, rate);
6be4826e RK	346	}
	347
	348	static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE;
	349
	350	/*
	351	* IRQ handler for the timer
	352	*/
	353	static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
	354	{
	355	struct clock_event_device *evt = dev_id;
	356
	357	/* clear the interrupt */
	358	writel(1, clkevt_base + TIMER_INTCLR);
	359
	360	evt->event_handler(evt);
	361
	362	return IRQ_HANDLED;
	363	}
	364
	365	static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
	366	{
	367	u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
	368
02f56321 LW	369	/* Disable timer */
02f56321 LW	370	writel(ctrl, clkevt_base + TIMER_CTRL);
6be4826e	371
02f56321 LW	372	switch (mode) {
	373	case CLOCK_EVT_MODE_PERIODIC:
	374	/* Enable the timer and start the periodic tick */
6be4826e RK	375	writel(timer_reload, clkevt_base + TIMER_LOAD);
6be4826e RK	376	ctrl \|= TIMER_CTRL_PERIODIC \| TIMER_CTRL_ENABLE;
02f56321 LW	377	writel(ctrl, clkevt_base + TIMER_CTRL);
	378	break;
	379	case CLOCK_EVT_MODE_ONESHOT:
	380	/* Leave the timer disabled, .set_next_event will enable it */
	381	ctrl &= ~TIMER_CTRL_PERIODIC;
	382	writel(ctrl, clkevt_base + TIMER_CTRL);
	383	break;
	384	case CLOCK_EVT_MODE_UNUSED:
	385	case CLOCK_EVT_MODE_SHUTDOWN:
	386	case CLOCK_EVT_MODE_RESUME:
	387	default:
	388	/* Just leave in disabled state */
	389	break;
6be4826e RK	390	}
6be4826e RK	391
6be4826e RK	392	}
	393
	394	static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
	395	{
	396	unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
	397
	398	writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
	399	writel(next, clkevt_base + TIMER_LOAD);
	400	writel(ctrl \| TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
	401
	402	return 0;
	403	}
	404
	405	static struct clock_event_device integrator_clockevent = {
	406	.name = "timer1",
02f56321	407	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
6be4826e RK	408	.set_mode = clkevt_set_mode,
	409	.set_next_event = clkevt_set_next_event,
	410	.rating = 300,
6be4826e RK	411	};
	412
	413	static struct irqaction integrator_timer_irq = {
	414	.name = "timer",
	415	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
	416	.handler = integrator_timer_interrupt,
	417	.dev_id = &integrator_clockevent,
	418	};
	419
bb76079a	420	static void integrator_clockevent_init(unsigned long inrate)
6be4826e	421	{
bb76079a	422	unsigned long rate = inrate;
6be4826e RK	423	unsigned int ctrl = 0;
6be4826e RK	424
6d8ce712	425	/* Calculate and program a divisor */
bb76079a LW	426	if (rate > 0x100000 * HZ) {
bb76079a LW	427	rate /= 256;
6be4826e	428	ctrl \|= TIMER_CTRL_DIV256;
bb76079a LW	429	} else if (rate > 0x10000 * HZ) {
bb76079a LW	430	rate /= 16;
6be4826e RK	431	ctrl \|= TIMER_CTRL_DIV16;
6be4826e RK	432	}
bb76079a	433	timer_reload = rate / HZ;
6be4826e RK	434	writel(ctrl, clkevt_base + TIMER_CTRL);
6be4826e RK	435
6be4826e	436	setup_irq(IRQ_TIMERINT1, &integrator_timer_irq);
6d8ce712	437	clockevents_config_and_register(&integrator_clockevent,
bb76079a	438	rate,
6d8ce712 LW	439	1,
6d8ce712 LW	440	0xffffU);
6be4826e RK	441	}
	442
	443	/*
	444	* Set up timer(s).
	445	*/
1da177e4 LT	446	static void __init ap_init_timer(void)
1da177e4 LT	447	{
bb76079a LW	448	struct clk *clk;
	449	unsigned long rate;
	450
	451	clk = clk_get_sys("ap_timer", NULL);
	452	BUG_ON(IS_ERR(clk));
	453	clk_enable(clk);
	454	rate = clk_get_rate(clk);
6be4826e RK	455
	456	writel(0, TIMER0_VA_BASE + TIMER_CTRL);
	457	writel(0, TIMER1_VA_BASE + TIMER_CTRL);
	458	writel(0, TIMER2_VA_BASE + TIMER_CTRL);
	459
bb76079a LW	460	integrator_clocksource_init(rate);
bb76079a LW	461	integrator_clockevent_init(rate);
1da177e4 LT	462	}
	463
	464	static struct sys_timer ap_timer = {
	465	.init = ap_init_timer,
1da177e4 LT	466	};
	467
	468	MACHINE_START(INTEGRATOR, "ARM-Integrator")
e9dea0c6	469	/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
c5e587a2	470	.atag_offset = 0x100,
98c672cf	471	.reserve = integrator_reserve,
c735c987	472	.map_io = ap_map_io,
695436e3	473	.nr_irqs = NR_IRQS_INTEGRATOR_AP,
c735c987	474	.init_early = integrator_init_early,
e9dea0c6	475	.init_irq = ap_init_irq,
3108e6ab	476	.handle_irq = fpga_handle_irq,
1da177e4	477	.timer = &ap_timer,
e9dea0c6	478	.init_machine = ap_init,
6338b66f	479	.restart = integrator_restart,
1da177e4	480	MACHINE_END