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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mach-integrator/integrator_ap.c | |
3 | * | |
4 | * Copyright (C) 2000-2003 Deep Blue Solutions Ltd | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
20 | #include <linux/types.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/list.h> | |
d052d1be | 24 | #include <linux/platform_device.h> |
1da177e4 LT |
25 | #include <linux/slab.h> |
26 | #include <linux/string.h> | |
b7808056 | 27 | #include <linux/syscore_ops.h> |
a62c80e5 RK |
28 | #include <linux/amba/bus.h> |
29 | #include <linux/amba/kmi.h> | |
6be4826e RK |
30 | #include <linux/clocksource.h> |
31 | #include <linux/clockchips.h> | |
32 | #include <linux/interrupt.h> | |
fced80c7 | 33 | #include <linux/io.h> |
f07e762e | 34 | #include <linux/mtd/physmap.h> |
bb76079a | 35 | #include <linux/clk.h> |
b71d8429 | 36 | #include <video/vga.h> |
1da177e4 | 37 | |
a09e64fb | 38 | #include <mach/hardware.h> |
a285edcf | 39 | #include <mach/platform.h> |
6be4826e | 40 | #include <asm/hardware/arm_timer.h> |
1da177e4 LT |
41 | #include <asm/irq.h> |
42 | #include <asm/setup.h> | |
4e57b681 | 43 | #include <asm/param.h> /* HZ */ |
1da177e4 | 44 | #include <asm/mach-types.h> |
1da177e4 | 45 | |
a09e64fb | 46 | #include <mach/lm.h> |
1da177e4 LT |
47 | |
48 | #include <asm/mach/arch.h> | |
1da177e4 LT |
49 | #include <asm/mach/irq.h> |
50 | #include <asm/mach/map.h> | |
51 | #include <asm/mach/time.h> | |
52 | ||
c41b16f8 RK |
53 | #include <plat/fpga-irq.h> |
54 | ||
98c672cf RK |
55 | #include "common.h" |
56 | ||
1da177e4 LT |
57 | /* |
58 | * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx | |
59 | * is the (PA >> 12). | |
60 | * | |
61 | * Setup a VA for the Integrator interrupt controller (for header #0, | |
62 | * just for now). | |
63 | */ | |
c41b16f8 RK |
64 | #define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE) |
65 | #define VA_SC_BASE __io_address(INTEGRATOR_SC_BASE) | |
66 | #define VA_EBI_BASE __io_address(INTEGRATOR_EBI_BASE) | |
67 | #define VA_CMIC_BASE __io_address(INTEGRATOR_HDR_IC) | |
1da177e4 LT |
68 | |
69 | /* | |
70 | * Logical Physical | |
71 | * e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M) | |
72 | * ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M) | |
73 | * ed000000 62000000 PCI V3 regs PHYS_PCI_V3_BASE (max 64k) | |
74 | * ee000000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M) | |
75 | * ef000000 Cache flush | |
76 | * f1000000 10000000 Core module registers | |
77 | * f1100000 11000000 System controller registers | |
78 | * f1200000 12000000 EBI registers | |
79 | * f1300000 13000000 Counter/Timer | |
80 | * f1400000 14000000 Interrupt controller | |
81 | * f1600000 16000000 UART 0 | |
82 | * f1700000 17000000 UART 1 | |
83 | * f1a00000 1a000000 Debug LEDs | |
84 | * f1b00000 1b000000 GPIO | |
85 | */ | |
86 | ||
87 | static struct map_desc ap_io_desc[] __initdata = { | |
c8d27298 DS |
88 | { |
89 | .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE), | |
90 | .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE), | |
91 | .length = SZ_4K, | |
92 | .type = MT_DEVICE | |
93 | }, { | |
94 | .virtual = IO_ADDRESS(INTEGRATOR_SC_BASE), | |
95 | .pfn = __phys_to_pfn(INTEGRATOR_SC_BASE), | |
96 | .length = SZ_4K, | |
97 | .type = MT_DEVICE | |
98 | }, { | |
99 | .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE), | |
100 | .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE), | |
101 | .length = SZ_4K, | |
102 | .type = MT_DEVICE | |
103 | }, { | |
104 | .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE), | |
105 | .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE), | |
106 | .length = SZ_4K, | |
107 | .type = MT_DEVICE | |
108 | }, { | |
109 | .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE), | |
110 | .pfn = __phys_to_pfn(INTEGRATOR_IC_BASE), | |
111 | .length = SZ_4K, | |
112 | .type = MT_DEVICE | |
113 | }, { | |
114 | .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE), | |
115 | .pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE), | |
116 | .length = SZ_4K, | |
117 | .type = MT_DEVICE | |
118 | }, { | |
119 | .virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE), | |
120 | .pfn = __phys_to_pfn(INTEGRATOR_UART1_BASE), | |
121 | .length = SZ_4K, | |
122 | .type = MT_DEVICE | |
123 | }, { | |
124 | .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE), | |
125 | .pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE), | |
126 | .length = SZ_4K, | |
127 | .type = MT_DEVICE | |
128 | }, { | |
da7ba956 RK |
129 | .virtual = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE), |
130 | .pfn = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE), | |
c8d27298 DS |
131 | .length = SZ_4K, |
132 | .type = MT_DEVICE | |
133 | }, { | |
134 | .virtual = PCI_MEMORY_VADDR, | |
135 | .pfn = __phys_to_pfn(PHYS_PCI_MEM_BASE), | |
136 | .length = SZ_16M, | |
137 | .type = MT_DEVICE | |
138 | }, { | |
139 | .virtual = PCI_CONFIG_VADDR, | |
140 | .pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE), | |
141 | .length = SZ_16M, | |
142 | .type = MT_DEVICE | |
143 | }, { | |
144 | .virtual = PCI_V3_VADDR, | |
145 | .pfn = __phys_to_pfn(PHYS_PCI_V3_BASE), | |
146 | .length = SZ_64K, | |
147 | .type = MT_DEVICE | |
148 | }, { | |
149 | .virtual = PCI_IO_VADDR, | |
150 | .pfn = __phys_to_pfn(PHYS_PCI_IO_BASE), | |
151 | .length = SZ_64K, | |
152 | .type = MT_DEVICE | |
153 | } | |
1da177e4 LT |
154 | }; |
155 | ||
156 | static void __init ap_map_io(void) | |
157 | { | |
158 | iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc)); | |
b71d8429 | 159 | vga_base = PCI_MEMORY_VADDR; |
1da177e4 LT |
160 | } |
161 | ||
162 | #define INTEGRATOR_SC_VALID_INT 0x003fffff | |
163 | ||
c41b16f8 RK |
164 | static struct fpga_irq_data sc_irq_data = { |
165 | .base = VA_IC_BASE, | |
166 | .irq_start = 0, | |
167 | .chip.name = "SC", | |
1da177e4 LT |
168 | }; |
169 | ||
170 | static void __init ap_init_irq(void) | |
171 | { | |
1da177e4 LT |
172 | /* Disable all interrupts initially. */ |
173 | /* Do the core module ones */ | |
174 | writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR); | |
175 | ||
176 | /* do the header card stuff next */ | |
177 | writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR); | |
178 | writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR); | |
179 | ||
c41b16f8 | 180 | fpga_irq_init(-1, INTEGRATOR_SC_VALID_INT, &sc_irq_data); |
1da177e4 LT |
181 | } |
182 | ||
183 | #ifdef CONFIG_PM | |
184 | static unsigned long ic_irq_enable; | |
185 | ||
b7808056 | 186 | static int irq_suspend(void) |
1da177e4 LT |
187 | { |
188 | ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE); | |
189 | return 0; | |
190 | } | |
191 | ||
b7808056 | 192 | static void irq_resume(void) |
1da177e4 LT |
193 | { |
194 | /* disable all irq sources */ | |
195 | writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR); | |
196 | writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR); | |
197 | writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR); | |
198 | ||
199 | writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET); | |
1da177e4 LT |
200 | } |
201 | #else | |
202 | #define irq_suspend NULL | |
203 | #define irq_resume NULL | |
204 | #endif | |
205 | ||
b7808056 | 206 | static struct syscore_ops irq_syscore_ops = { |
1da177e4 LT |
207 | .suspend = irq_suspend, |
208 | .resume = irq_resume, | |
209 | }; | |
210 | ||
b7808056 | 211 | static int __init irq_syscore_init(void) |
1da177e4 | 212 | { |
b7808056 RW |
213 | register_syscore_ops(&irq_syscore_ops); |
214 | ||
215 | return 0; | |
1da177e4 LT |
216 | } |
217 | ||
b7808056 | 218 | device_initcall(irq_syscore_init); |
1da177e4 LT |
219 | |
220 | /* | |
221 | * Flash handling. | |
222 | */ | |
223 | #define SC_CTRLC (VA_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET) | |
224 | #define SC_CTRLS (VA_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET) | |
225 | #define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET) | |
226 | #define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET) | |
227 | ||
f07e762e | 228 | static int ap_flash_init(struct platform_device *dev) |
1da177e4 LT |
229 | { |
230 | u32 tmp; | |
231 | ||
232 | writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC); | |
233 | ||
234 | tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE; | |
235 | writel(tmp, EBI_CSR1); | |
236 | ||
237 | if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) { | |
238 | writel(0xa05f, EBI_LOCK); | |
239 | writel(tmp, EBI_CSR1); | |
240 | writel(0, EBI_LOCK); | |
241 | } | |
242 | return 0; | |
243 | } | |
244 | ||
f07e762e | 245 | static void ap_flash_exit(struct platform_device *dev) |
1da177e4 LT |
246 | { |
247 | u32 tmp; | |
248 | ||
249 | writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC); | |
250 | ||
251 | tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE; | |
252 | writel(tmp, EBI_CSR1); | |
253 | ||
254 | if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) { | |
255 | writel(0xa05f, EBI_LOCK); | |
256 | writel(tmp, EBI_CSR1); | |
257 | writel(0, EBI_LOCK); | |
258 | } | |
259 | } | |
260 | ||
667f390b | 261 | static void ap_flash_set_vpp(struct platform_device *pdev, int on) |
1da177e4 | 262 | { |
c41b16f8 | 263 | void __iomem *reg = on ? SC_CTRLS : SC_CTRLC; |
1da177e4 LT |
264 | |
265 | writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg); | |
266 | } | |
267 | ||
f07e762e | 268 | static struct physmap_flash_data ap_flash_data = { |
1da177e4 LT |
269 | .width = 4, |
270 | .init = ap_flash_init, | |
271 | .exit = ap_flash_exit, | |
272 | .set_vpp = ap_flash_set_vpp, | |
273 | }; | |
274 | ||
275 | static struct resource cfi_flash_resource = { | |
276 | .start = INTEGRATOR_FLASH_BASE, | |
277 | .end = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1, | |
278 | .flags = IORESOURCE_MEM, | |
279 | }; | |
280 | ||
281 | static struct platform_device cfi_flash_device = { | |
f07e762e | 282 | .name = "physmap-flash", |
1da177e4 LT |
283 | .id = 0, |
284 | .dev = { | |
285 | .platform_data = &ap_flash_data, | |
286 | }, | |
287 | .num_resources = 1, | |
288 | .resource = &cfi_flash_resource, | |
289 | }; | |
290 | ||
291 | static void __init ap_init(void) | |
292 | { | |
293 | unsigned long sc_dec; | |
294 | int i; | |
295 | ||
296 | platform_device_register(&cfi_flash_device); | |
297 | ||
298 | sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET); | |
299 | for (i = 0; i < 4; i++) { | |
300 | struct lm_device *lmdev; | |
301 | ||
302 | if ((sc_dec & (16 << i)) == 0) | |
303 | continue; | |
304 | ||
d2a02b93 | 305 | lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL); |
1da177e4 LT |
306 | if (!lmdev) |
307 | continue; | |
308 | ||
1da177e4 LT |
309 | lmdev->resource.start = 0xc0000000 + 0x10000000 * i; |
310 | lmdev->resource.end = lmdev->resource.start + 0x0fffffff; | |
311 | lmdev->resource.flags = IORESOURCE_MEM; | |
312 | lmdev->irq = IRQ_AP_EXPINT0 + i; | |
313 | lmdev->id = i; | |
314 | ||
315 | lm_device_register(lmdev); | |
316 | } | |
317 | } | |
318 | ||
6be4826e RK |
319 | /* |
320 | * Where is the timer (VA)? | |
321 | */ | |
322 | #define TIMER0_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER0_BASE) | |
323 | #define TIMER1_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER1_BASE) | |
324 | #define TIMER2_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER2_BASE) | |
325 | ||
6be4826e RK |
326 | static unsigned long timer_reload; |
327 | ||
bb76079a | 328 | static void integrator_clocksource_init(unsigned long inrate) |
6be4826e | 329 | { |
c5039f52 | 330 | void __iomem *base = (void __iomem *)TIMER2_VA_BASE; |
bb9ea778 | 331 | u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC; |
bb76079a | 332 | unsigned long rate = inrate; |
6be4826e | 333 | |
bb76079a LW |
334 | if (rate >= 1500000) { |
335 | rate /= 16; | |
bb9ea778 | 336 | ctrl |= TIMER_CTRL_DIV16; |
6be4826e RK |
337 | } |
338 | ||
6be4826e | 339 | writel(0xffff, base + TIMER_LOAD); |
bb9ea778 | 340 | writel(ctrl, base + TIMER_CTRL); |
6be4826e | 341 | |
c5039f52 | 342 | clocksource_mmio_init(base + TIMER_VALUE, "timer2", |
bb76079a | 343 | rate, 200, 16, clocksource_mmio_readl_down); |
6be4826e RK |
344 | } |
345 | ||
346 | static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE; | |
347 | ||
348 | /* | |
349 | * IRQ handler for the timer | |
350 | */ | |
351 | static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id) | |
352 | { | |
353 | struct clock_event_device *evt = dev_id; | |
354 | ||
355 | /* clear the interrupt */ | |
356 | writel(1, clkevt_base + TIMER_INTCLR); | |
357 | ||
358 | evt->event_handler(evt); | |
359 | ||
360 | return IRQ_HANDLED; | |
361 | } | |
362 | ||
363 | static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) | |
364 | { | |
365 | u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE; | |
366 | ||
02f56321 LW |
367 | /* Disable timer */ |
368 | writel(ctrl, clkevt_base + TIMER_CTRL); | |
6be4826e | 369 | |
02f56321 LW |
370 | switch (mode) { |
371 | case CLOCK_EVT_MODE_PERIODIC: | |
372 | /* Enable the timer and start the periodic tick */ | |
6be4826e RK |
373 | writel(timer_reload, clkevt_base + TIMER_LOAD); |
374 | ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE; | |
02f56321 LW |
375 | writel(ctrl, clkevt_base + TIMER_CTRL); |
376 | break; | |
377 | case CLOCK_EVT_MODE_ONESHOT: | |
378 | /* Leave the timer disabled, .set_next_event will enable it */ | |
379 | ctrl &= ~TIMER_CTRL_PERIODIC; | |
380 | writel(ctrl, clkevt_base + TIMER_CTRL); | |
381 | break; | |
382 | case CLOCK_EVT_MODE_UNUSED: | |
383 | case CLOCK_EVT_MODE_SHUTDOWN: | |
384 | case CLOCK_EVT_MODE_RESUME: | |
385 | default: | |
386 | /* Just leave in disabled state */ | |
387 | break; | |
6be4826e RK |
388 | } |
389 | ||
6be4826e RK |
390 | } |
391 | ||
392 | static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt) | |
393 | { | |
394 | unsigned long ctrl = readl(clkevt_base + TIMER_CTRL); | |
395 | ||
396 | writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL); | |
397 | writel(next, clkevt_base + TIMER_LOAD); | |
398 | writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL); | |
399 | ||
400 | return 0; | |
401 | } | |
402 | ||
403 | static struct clock_event_device integrator_clockevent = { | |
404 | .name = "timer1", | |
02f56321 | 405 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, |
6be4826e RK |
406 | .set_mode = clkevt_set_mode, |
407 | .set_next_event = clkevt_set_next_event, | |
408 | .rating = 300, | |
6be4826e RK |
409 | }; |
410 | ||
411 | static struct irqaction integrator_timer_irq = { | |
412 | .name = "timer", | |
413 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | |
414 | .handler = integrator_timer_interrupt, | |
415 | .dev_id = &integrator_clockevent, | |
416 | }; | |
417 | ||
bb76079a | 418 | static void integrator_clockevent_init(unsigned long inrate) |
6be4826e | 419 | { |
bb76079a | 420 | unsigned long rate = inrate; |
6be4826e RK |
421 | unsigned int ctrl = 0; |
422 | ||
6d8ce712 | 423 | /* Calculate and program a divisor */ |
bb76079a LW |
424 | if (rate > 0x100000 * HZ) { |
425 | rate /= 256; | |
6be4826e | 426 | ctrl |= TIMER_CTRL_DIV256; |
bb76079a LW |
427 | } else if (rate > 0x10000 * HZ) { |
428 | rate /= 16; | |
6be4826e RK |
429 | ctrl |= TIMER_CTRL_DIV16; |
430 | } | |
bb76079a | 431 | timer_reload = rate / HZ; |
6be4826e RK |
432 | writel(ctrl, clkevt_base + TIMER_CTRL); |
433 | ||
6be4826e | 434 | setup_irq(IRQ_TIMERINT1, &integrator_timer_irq); |
6d8ce712 | 435 | clockevents_config_and_register(&integrator_clockevent, |
bb76079a | 436 | rate, |
6d8ce712 LW |
437 | 1, |
438 | 0xffffU); | |
6be4826e RK |
439 | } |
440 | ||
441 | /* | |
442 | * Set up timer(s). | |
443 | */ | |
1da177e4 LT |
444 | static void __init ap_init_timer(void) |
445 | { | |
bb76079a LW |
446 | struct clk *clk; |
447 | unsigned long rate; | |
448 | ||
449 | clk = clk_get_sys("ap_timer", NULL); | |
450 | BUG_ON(IS_ERR(clk)); | |
451 | clk_enable(clk); | |
452 | rate = clk_get_rate(clk); | |
6be4826e RK |
453 | |
454 | writel(0, TIMER0_VA_BASE + TIMER_CTRL); | |
455 | writel(0, TIMER1_VA_BASE + TIMER_CTRL); | |
456 | writel(0, TIMER2_VA_BASE + TIMER_CTRL); | |
457 | ||
bb76079a LW |
458 | integrator_clocksource_init(rate); |
459 | integrator_clockevent_init(rate); | |
1da177e4 LT |
460 | } |
461 | ||
462 | static struct sys_timer ap_timer = { | |
463 | .init = ap_init_timer, | |
1da177e4 LT |
464 | }; |
465 | ||
466 | MACHINE_START(INTEGRATOR, "ARM-Integrator") | |
e9dea0c6 | 467 | /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ |
c5e587a2 | 468 | .atag_offset = 0x100, |
98c672cf | 469 | .reserve = integrator_reserve, |
c735c987 RK |
470 | .map_io = ap_map_io, |
471 | .init_early = integrator_init_early, | |
e9dea0c6 | 472 | .init_irq = ap_init_irq, |
1da177e4 | 473 | .timer = &ap_timer, |
e9dea0c6 | 474 | .init_machine = ap_init, |
6338b66f | 475 | .restart = integrator_restart, |
1da177e4 | 476 | MACHINE_END |