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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mach-integrator/integrator_cp.c | |
3 | * | |
4 | * Copyright (C) 2003 Deep Blue Solutions Ltd | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License. | |
9 | */ | |
10 | #include <linux/types.h> | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/list.h> | |
d052d1be | 14 | #include <linux/platform_device.h> |
1da177e4 | 15 | #include <linux/dma-mapping.h> |
1da177e4 | 16 | #include <linux/string.h> |
edbaa603 | 17 | #include <linux/device.h> |
a62c80e5 RK |
18 | #include <linux/amba/bus.h> |
19 | #include <linux/amba/kmi.h> | |
20 | #include <linux/amba/clcd.h> | |
11c32d7b | 21 | #include <linux/platform_data/video-clcd-versatile.h> |
6ef297f8 | 22 | #include <linux/amba/mmci.h> |
fced80c7 | 23 | #include <linux/io.h> |
44fa72d1 | 24 | #include <linux/irqchip.h> |
5a0e3ad6 | 25 | #include <linux/gfp.h> |
046dfa0a | 26 | #include <linux/mtd/physmap.h> |
4980f9bc LW |
27 | #include <linux/of_irq.h> |
28 | #include <linux/of_address.h> | |
4672cddf | 29 | #include <linux/of_platform.h> |
a79528e9 | 30 | #include <linux/sched_clock.h> |
1da177e4 | 31 | |
1da177e4 LT |
32 | #include <asm/setup.h> |
33 | #include <asm/mach-types.h> | |
1da177e4 | 34 | #include <asm/mach/arch.h> |
1da177e4 | 35 | #include <asm/mach/irq.h> |
1da177e4 LT |
36 | #include <asm/mach/map.h> |
37 | #include <asm/mach/time.h> | |
38 | ||
1b1ef755 | 39 | #include "hardware.h" |
bb4dbefe | 40 | #include "cm.h" |
98c672cf RK |
41 | #include "common.h" |
42 | ||
e6fae083 LW |
43 | /* Base address to the CP controller */ |
44 | static void __iomem *intcp_con_base; | |
45 | ||
1da177e4 | 46 | #define INTCP_PA_FLASH_BASE 0x24000000 |
1da177e4 LT |
47 | |
48 | #define INTCP_PA_CLCD_BASE 0xc0000000 | |
49 | ||
1da177e4 LT |
50 | #define INTCP_FLASHPROG 0x04 |
51 | #define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0) | |
52 | #define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1) | |
53 | ||
54 | /* | |
55 | * Logical Physical | |
608914b3 | 56 | * f1000000 10000000 Core module registers |
1da177e4 LT |
57 | * f1300000 13000000 Counter/Timer |
58 | * f1400000 14000000 Interrupt controller | |
59 | * f1600000 16000000 UART 0 | |
60 | * f1700000 17000000 UART 1 | |
61 | * f1a00000 1a000000 Debug LEDs | |
da7ba956 RK |
62 | * fc900000 c9000000 GPIO |
63 | * fca00000 ca000000 SIC | |
1da177e4 LT |
64 | */ |
65 | ||
060fd1be | 66 | static struct map_desc intcp_io_desc[] __initdata __maybe_unused = { |
c8d27298 | 67 | { |
608914b3 LW |
68 | .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE), |
69 | .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE), | |
70 | .length = SZ_4K, | |
71 | .type = MT_DEVICE | |
72 | }, { | |
c8d27298 DS |
73 | .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE), |
74 | .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE), | |
75 | .length = SZ_4K, | |
76 | .type = MT_DEVICE | |
77 | }, { | |
78 | .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE), | |
79 | .pfn = __phys_to_pfn(INTEGRATOR_IC_BASE), | |
80 | .length = SZ_4K, | |
81 | .type = MT_DEVICE | |
82 | }, { | |
83 | .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE), | |
84 | .pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE), | |
85 | .length = SZ_4K, | |
86 | .type = MT_DEVICE | |
c8d27298 DS |
87 | }, { |
88 | .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE), | |
89 | .pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE), | |
90 | .length = SZ_4K, | |
91 | .type = MT_DEVICE | |
92 | }, { | |
da7ba956 RK |
93 | .virtual = IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE), |
94 | .pfn = __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE), | |
c8d27298 DS |
95 | .length = SZ_4K, |
96 | .type = MT_DEVICE | |
97 | }, { | |
da7ba956 RK |
98 | .virtual = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE), |
99 | .pfn = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE), | |
c8d27298 DS |
100 | .length = SZ_4K, |
101 | .type = MT_DEVICE | |
c8d27298 | 102 | } |
1da177e4 LT |
103 | }; |
104 | ||
105 | static void __init intcp_map_io(void) | |
106 | { | |
107 | iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc)); | |
108 | } | |
109 | ||
1da177e4 LT |
110 | /* |
111 | * Flash handling. | |
112 | */ | |
046dfa0a | 113 | static int intcp_flash_init(struct platform_device *dev) |
1da177e4 LT |
114 | { |
115 | u32 val; | |
116 | ||
e6fae083 | 117 | val = readl(intcp_con_base + INTCP_FLASHPROG); |
1da177e4 | 118 | val |= CINTEGRATOR_FLASHPROG_FLWREN; |
e6fae083 | 119 | writel(val, intcp_con_base + INTCP_FLASHPROG); |
1da177e4 LT |
120 | |
121 | return 0; | |
122 | } | |
123 | ||
046dfa0a | 124 | static void intcp_flash_exit(struct platform_device *dev) |
1da177e4 LT |
125 | { |
126 | u32 val; | |
127 | ||
e6fae083 | 128 | val = readl(intcp_con_base + INTCP_FLASHPROG); |
1da177e4 | 129 | val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN); |
e6fae083 | 130 | writel(val, intcp_con_base + INTCP_FLASHPROG); |
1da177e4 LT |
131 | } |
132 | ||
667f390b | 133 | static void intcp_flash_set_vpp(struct platform_device *pdev, int on) |
1da177e4 LT |
134 | { |
135 | u32 val; | |
136 | ||
e6fae083 | 137 | val = readl(intcp_con_base + INTCP_FLASHPROG); |
1da177e4 LT |
138 | if (on) |
139 | val |= CINTEGRATOR_FLASHPROG_FLVPPEN; | |
140 | else | |
141 | val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN; | |
e6fae083 | 142 | writel(val, intcp_con_base + INTCP_FLASHPROG); |
1da177e4 LT |
143 | } |
144 | ||
046dfa0a | 145 | static struct physmap_flash_data intcp_flash_data = { |
1da177e4 LT |
146 | .width = 4, |
147 | .init = intcp_flash_init, | |
148 | .exit = intcp_flash_exit, | |
149 | .set_vpp = intcp_flash_set_vpp, | |
150 | }; | |
151 | ||
1da177e4 LT |
152 | /* |
153 | * It seems that the card insertion interrupt remains active after | |
154 | * we've acknowledged it. We therefore ignore the interrupt, and | |
155 | * rely on reading it from the SIC. This also means that we must | |
156 | * clear the latched interrupt. | |
157 | */ | |
158 | static unsigned int mmc_status(struct device *dev) | |
159 | { | |
b7a3f8db | 160 | unsigned int status = readl(__io_address(0xca000000 + 4)); |
e6fae083 | 161 | writel(8, intcp_con_base + 8); |
1da177e4 LT |
162 | |
163 | return status & 8; | |
164 | } | |
165 | ||
6ef297f8 | 166 | static struct mmci_platform_data mmc_data = { |
1da177e4 LT |
167 | .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, |
168 | .status = mmc_status, | |
7fb2bbf4 RK |
169 | .gpio_wp = -1, |
170 | .gpio_cd = -1, | |
1da177e4 LT |
171 | }; |
172 | ||
1da177e4 LT |
173 | /* |
174 | * CLCD support | |
175 | */ | |
1da177e4 LT |
176 | /* |
177 | * Ensure VGA is selected. | |
178 | */ | |
179 | static void cp_clcd_enable(struct clcd_fb *fb) | |
180 | { | |
e6b9c1f8 | 181 | struct fb_var_screeninfo *var = &fb->fb.var; |
30aeadd4 JA |
182 | u32 val = CM_CTRL_STATIC1 | CM_CTRL_STATIC2 |
183 | | CM_CTRL_LCDEN0 | CM_CTRL_LCDEN1; | |
4774e226 | 184 | |
e6b9c1f8 RK |
185 | if (var->bits_per_pixel <= 8 || |
186 | (var->bits_per_pixel == 16 && var->green.length == 5)) | |
187 | /* Pseudocolor, RGB555, BGR555 */ | |
188 | val |= CM_CTRL_LCDMUXSEL_VGA555_TFT555; | |
4774e226 | 189 | else if (fb->fb.var.bits_per_pixel <= 16) |
e6b9c1f8 RK |
190 | /* truecolor RGB565 */ |
191 | val |= CM_CTRL_LCDMUXSEL_VGA565_TFT555; | |
4774e226 RK |
192 | else |
193 | val = 0; /* no idea for this, don't trust the docs */ | |
194 | ||
195 | cm_control(CM_CTRL_LCDMUXSEL_MASK| | |
196 | CM_CTRL_LCDEN0| | |
197 | CM_CTRL_LCDEN1| | |
198 | CM_CTRL_STATIC1| | |
199 | CM_CTRL_STATIC2| | |
200 | CM_CTRL_STATIC| | |
201 | CM_CTRL_n24BITEN, val); | |
1da177e4 LT |
202 | } |
203 | ||
1da177e4 LT |
204 | static int cp_clcd_setup(struct clcd_fb *fb) |
205 | { | |
9dfec4fe RK |
206 | fb->panel = versatile_clcd_get_panel("VGA"); |
207 | if (!fb->panel) | |
208 | return -EINVAL; | |
1da177e4 | 209 | |
9dfec4fe | 210 | return versatile_clcd_setup_dma(fb, SZ_1M); |
1da177e4 LT |
211 | } |
212 | ||
213 | static struct clcd_board clcd_data = { | |
214 | .name = "Integrator/CP", | |
9dfec4fe | 215 | .caps = CLCD_CAP_5551 | CLCD_CAP_RGB565 | CLCD_CAP_888, |
1da177e4 LT |
216 | .check = clcdfb_check, |
217 | .decode = clcdfb_decode, | |
218 | .enable = cp_clcd_enable, | |
219 | .setup = cp_clcd_setup, | |
9dfec4fe RK |
220 | .mmap = versatile_clcd_mmap_dma, |
221 | .remove = versatile_clcd_remove_dma, | |
1da177e4 LT |
222 | }; |
223 | ||
d77e270c RK |
224 | #define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28) |
225 | ||
a79528e9 LW |
226 | static u64 notrace intcp_read_sched_clock(void) |
227 | { | |
228 | return readl(REFCOUNTER); | |
229 | } | |
230 | ||
c735c987 RK |
231 | static void __init intcp_init_early(void) |
232 | { | |
a79528e9 | 233 | sched_clock_register(intcp_read_sched_clock, 32, 24000000); |
c735c987 RK |
234 | } |
235 | ||
4980f9bc | 236 | static void __init intcp_init_irq_of(void) |
1da177e4 | 237 | { |
bb4dbefe | 238 | cm_init(); |
44fa72d1 | 239 | irqchip_init(); |
4980f9bc | 240 | } |
1da177e4 | 241 | |
4672cddf LW |
242 | /* |
243 | * For the Device Tree, add in the UART, MMC and CLCD specifics as AUXDATA | |
244 | * and enforce the bus names since these are used for clock lookups. | |
245 | */ | |
246 | static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = { | |
247 | OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE, | |
248 | "rtc", NULL), | |
249 | OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE, | |
379df279 | 250 | "uart0", NULL), |
4672cddf | 251 | OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE, |
379df279 | 252 | "uart1", NULL), |
4672cddf LW |
253 | OF_DEV_AUXDATA("arm,primecell", KMI0_BASE, |
254 | "kmi0", NULL), | |
255 | OF_DEV_AUXDATA("arm,primecell", KMI1_BASE, | |
256 | "kmi1", NULL), | |
257 | OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_MMC_BASE, | |
258 | "mmci", &mmc_data), | |
259 | OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_AACI_BASE, | |
260 | "aaci", &mmc_data), | |
261 | OF_DEV_AUXDATA("arm,primecell", INTCP_PA_CLCD_BASE, | |
262 | "clcd", &clcd_data), | |
73efd530 LW |
263 | OF_DEV_AUXDATA("cfi-flash", INTCP_PA_FLASH_BASE, |
264 | "physmap-flash", &intcp_flash_data), | |
4672cddf LW |
265 | { /* sentinel */ }, |
266 | }; | |
267 | ||
df36680f LW |
268 | static const struct of_device_id intcp_syscon_match[] = { |
269 | { .compatible = "arm,integrator-cp-syscon"}, | |
270 | { }, | |
271 | }; | |
272 | ||
4672cddf LW |
273 | static void __init intcp_init_of(void) |
274 | { | |
64100a03 | 275 | struct device_node *cpcon; |
64100a03 | 276 | |
11f9323a | 277 | cpcon = of_find_matching_node(NULL, intcp_syscon_match); |
64100a03 LW |
278 | if (!cpcon) |
279 | return; | |
280 | ||
281 | intcp_con_base = of_iomap(cpcon, 0); | |
282 | if (!intcp_con_base) | |
283 | return; | |
284 | ||
11f9323a LW |
285 | of_platform_populate(NULL, of_default_bus_match_table, |
286 | intcp_auxdata_lookup, NULL); | |
4672cddf LW |
287 | } |
288 | ||
4980f9bc LW |
289 | static const char * intcp_dt_board_compat[] = { |
290 | "arm,integrator-cp", | |
291 | NULL, | |
292 | }; | |
1da177e4 | 293 | |
4980f9bc LW |
294 | DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)") |
295 | .reserve = integrator_reserve, | |
296 | .map_io = intcp_map_io, | |
4980f9bc LW |
297 | .init_early = intcp_init_early, |
298 | .init_irq = intcp_init_irq_of, | |
4672cddf | 299 | .init_machine = intcp_init_of, |
4980f9bc LW |
300 | .dt_compat = intcp_dt_board_compat, |
301 | MACHINE_END |